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Revert "microblaze_mmu_v2: Update signal returning address"
[linux/fpc-iii.git] / sound / soc / codecs / cs42l52.c
blob628daf6a1d97e8fee699f8d87ea92ec6dbf5fdaf
1 /*
2 * cs42l52.c -- CS42L52 ALSA SoC audio driver
3 *
4 * Copyright 2012 CirrusLogic, Inc.
5 *
6 * Author: Georgi Vlaev <joe@nucleusys.com>
7 * Author: Brian Austin <brian.austin@cirrus.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/pm.h>
21 #include <linux/i2c.h>
22 #include <linux/input.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
25 #include <linux/workqueue.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/soc-dapm.h>
33 #include <sound/initval.h>
34 #include <sound/tlv.h>
35 #include <sound/cs42l52.h>
36 #include "cs42l52.h"
37
38 struct sp_config {
39 u8 spc, format, spfs;
40 u32 srate;
41 };
42
43 struct cs42l52_private {
44 struct regmap *regmap;
45 struct snd_soc_codec *codec;
46 struct device *dev;
47 struct sp_config config;
48 struct cs42l52_platform_data pdata;
49 u32 sysclk;
50 u8 mclksel;
51 u32 mclk;
52 u8 flags;
53 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
54 struct input_dev *beep;
55 struct work_struct beep_work;
56 int beep_rate;
57 #endif
58 };
59
60 static const struct reg_default cs42l52_reg_defaults[] = {
61 { CS42L52_PWRCTL1, 0x9F }, /* r02 PWRCTL 1 */
62 { CS42L52_PWRCTL2, 0x07 }, /* r03 PWRCTL 2 */
63 { CS42L52_PWRCTL3, 0xFF }, /* r04 PWRCTL 3 */
64 { CS42L52_CLK_CTL, 0xA0 }, /* r05 Clocking Ctl */
65 { CS42L52_IFACE_CTL1, 0x00 }, /* r06 Interface Ctl 1 */
66 { CS42L52_ADC_PGA_A, 0x80 }, /* r08 Input A Select */
67 { CS42L52_ADC_PGA_B, 0x80 }, /* r09 Input B Select */
68 { CS42L52_ANALOG_HPF_CTL, 0xA5 }, /* r0A Analog HPF Ctl */
69 { CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
70 { CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */
71 { CS42L52_PB_CTL1, 0x60 }, /* r0D Playback Ctl 1 */
72 { CS42L52_MISC_CTL, 0x02 }, /* r0E Misc. Ctl */
73 { CS42L52_PB_CTL2, 0x00 }, /* r0F Playback Ctl 2 */
74 { CS42L52_MICA_CTL, 0x00 }, /* r10 MICA Amp Ctl */
75 { CS42L52_MICB_CTL, 0x00 }, /* r11 MICB Amp Ctl */
76 { CS42L52_PGAA_CTL, 0x00 }, /* r12 PGAA Vol, Misc. */
77 { CS42L52_PGAB_CTL, 0x00 }, /* r13 PGAB Vol, Misc. */
78 { CS42L52_PASSTHRUA_VOL, 0x00 }, /* r14 Bypass A Vol */
79 { CS42L52_PASSTHRUB_VOL, 0x00 }, /* r15 Bypass B Vol */
80 { CS42L52_ADCA_VOL, 0x00 }, /* r16 ADCA Volume */
81 { CS42L52_ADCB_VOL, 0x00 }, /* r17 ADCB Volume */
82 { CS42L52_ADCA_MIXER_VOL, 0x80 }, /* r18 ADCA Mixer Volume */
83 { CS42L52_ADCB_MIXER_VOL, 0x80 }, /* r19 ADCB Mixer Volume */
84 { CS42L52_PCMA_MIXER_VOL, 0x00 }, /* r1A PCMA Mixer Volume */
85 { CS42L52_PCMB_MIXER_VOL, 0x00 }, /* r1B PCMB Mixer Volume */
86 { CS42L52_BEEP_FREQ, 0x00 }, /* r1C Beep Freq on Time */
87 { CS42L52_BEEP_VOL, 0x00 }, /* r1D Beep Volume off Time */
88 { CS42L52_BEEP_TONE_CTL, 0x00 }, /* r1E Beep Tone Cfg. */
89 { CS42L52_TONE_CTL, 0x00 }, /* r1F Tone Ctl */
90 { CS42L52_MASTERA_VOL, 0x88 }, /* r20 Master A Volume */
91 { CS42L52_MASTERB_VOL, 0x00 }, /* r21 Master B Volume */
92 { CS42L52_HPA_VOL, 0x00 }, /* r22 Headphone A Volume */
93 { CS42L52_HPB_VOL, 0x00 }, /* r23 Headphone B Volume */
94 { CS42L52_SPKA_VOL, 0x00 }, /* r24 Speaker A Volume */
95 { CS42L52_SPKB_VOL, 0x00 }, /* r25 Speaker B Volume */
96 { CS42L52_ADC_PCM_MIXER, 0x00 }, /* r26 Channel Mixer and Swap */
97 { CS42L52_LIMITER_CTL1, 0x00 }, /* r27 Limit Ctl 1 Thresholds */
98 { CS42L52_LIMITER_CTL2, 0x7F }, /* r28 Limit Ctl 2 Release Rate */
99 { CS42L52_LIMITER_AT_RATE, 0xC0 }, /* r29 Limiter Attack Rate */
100 { CS42L52_ALC_CTL, 0x00 }, /* r2A ALC Ctl 1 Attack Rate */
101 { CS42L52_ALC_RATE, 0x3F }, /* r2B ALC Release Rate */
102 { CS42L52_ALC_THRESHOLD, 0x3f }, /* r2C ALC Thresholds */
103 { CS42L52_NOISE_GATE_CTL, 0x00 }, /* r2D Noise Gate Ctl */
104 { CS42L52_CLK_STATUS, 0x00 }, /* r2E Overflow and Clock Status */
105 { CS42L52_BATT_COMPEN, 0x00 }, /* r2F battery Compensation */
106 { CS42L52_BATT_LEVEL, 0x00 }, /* r30 VP Battery Level */
107 { CS42L52_SPK_STATUS, 0x00 }, /* r31 Speaker Status */
108 { CS42L52_TEM_CTL, 0x3B }, /* r32 Temp Ctl */
109 { CS42L52_THE_FOLDBACK, 0x00 }, /* r33 Foldback */
110 };
111
112 static bool cs42l52_readable_register(struct device *dev, unsigned int reg)
113 {
114 switch (reg) {
115 case CS42L52_CHIP:
116 case CS42L52_PWRCTL1:
117 case CS42L52_PWRCTL2:
118 case CS42L52_PWRCTL3:
119 case CS42L52_CLK_CTL:
120 case CS42L52_IFACE_CTL1:
121 case CS42L52_IFACE_CTL2:
122 case CS42L52_ADC_PGA_A:
123 case CS42L52_ADC_PGA_B:
124 case CS42L52_ANALOG_HPF_CTL:
125 case CS42L52_ADC_HPF_FREQ:
126 case CS42L52_ADC_MISC_CTL:
127 case CS42L52_PB_CTL1:
128 case CS42L52_MISC_CTL:
129 case CS42L52_PB_CTL2:
130 case CS42L52_MICA_CTL:
131 case CS42L52_MICB_CTL:
132 case CS42L52_PGAA_CTL:
133 case CS42L52_PGAB_CTL:
134 case CS42L52_PASSTHRUA_VOL:
135 case CS42L52_PASSTHRUB_VOL:
136 case CS42L52_ADCA_VOL:
137 case CS42L52_ADCB_VOL:
138 case CS42L52_ADCA_MIXER_VOL:
139 case CS42L52_ADCB_MIXER_VOL:
140 case CS42L52_PCMA_MIXER_VOL:
141 case CS42L52_PCMB_MIXER_VOL:
142 case CS42L52_BEEP_FREQ:
143 case CS42L52_BEEP_VOL:
144 case CS42L52_BEEP_TONE_CTL:
145 case CS42L52_TONE_CTL:
146 case CS42L52_MASTERA_VOL:
147 case CS42L52_MASTERB_VOL:
148 case CS42L52_HPA_VOL:
149 case CS42L52_HPB_VOL:
150 case CS42L52_SPKA_VOL:
151 case CS42L52_SPKB_VOL:
152 case CS42L52_ADC_PCM_MIXER:
153 case CS42L52_LIMITER_CTL1:
154 case CS42L52_LIMITER_CTL2:
155 case CS42L52_LIMITER_AT_RATE:
156 case CS42L52_ALC_CTL:
157 case CS42L52_ALC_RATE:
158 case CS42L52_ALC_THRESHOLD:
159 case CS42L52_NOISE_GATE_CTL:
160 case CS42L52_CLK_STATUS:
161 case CS42L52_BATT_COMPEN:
162 case CS42L52_BATT_LEVEL:
163 case CS42L52_SPK_STATUS:
164 case CS42L52_TEM_CTL:
165 case CS42L52_THE_FOLDBACK:
166 case CS42L52_CHARGE_PUMP:
167 return true;
168 default:
169 return false;
170 }
171 }
172
173 static bool cs42l52_volatile_register(struct device *dev, unsigned int reg)
174 {
175 switch (reg) {
176 case CS42L52_IFACE_CTL2:
177 case CS42L52_CLK_STATUS:
178 case CS42L52_BATT_LEVEL:
179 case CS42L52_SPK_STATUS:
180 case CS42L52_CHARGE_PUMP:
181 return 1;
182 default:
183 return 0;
184 }
185 }
186
187 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
188
189 static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
190
191 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
192
193 static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
194
195 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
196
197 static const unsigned int limiter_tlv[] = {
198 TLV_DB_RANGE_HEAD(2),
199 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
200 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0),
201 };
202
203 static const char * const cs42l52_adca_text[] = {
204 "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
205
206 static const char * const cs42l52_adcb_text[] = {
207 "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
208
209 static const struct soc_enum adca_enum =
210 SOC_ENUM_SINGLE(CS42L52_ADC_PGA_A, 5,
211 ARRAY_SIZE(cs42l52_adca_text), cs42l52_adca_text);
212
213 static const struct soc_enum adcb_enum =
214 SOC_ENUM_SINGLE(CS42L52_ADC_PGA_B, 5,
215 ARRAY_SIZE(cs42l52_adcb_text), cs42l52_adcb_text);
216
217 static const struct snd_kcontrol_new adca_mux =
218 SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum);
219
220 static const struct snd_kcontrol_new adcb_mux =
221 SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum);
222
223 static const char * const mic_bias_level_text[] = {
224 "0.5 +VA", "0.6 +VA", "0.7 +VA",
225 "0.8 +VA", "0.83 +VA", "0.91 +VA"
226 };
227
228 static const struct soc_enum mic_bias_level_enum =
229 SOC_ENUM_SINGLE(CS42L52_IFACE_CTL1, 0,
230 ARRAY_SIZE(mic_bias_level_text), mic_bias_level_text);
231
232 static const char * const cs42l52_mic_text[] = { "Single", "Differential" };
233
234 static const struct soc_enum mica_enum =
235 SOC_ENUM_SINGLE(CS42L52_MICA_CTL, 5,
236 ARRAY_SIZE(cs42l52_mic_text), cs42l52_mic_text);
237
238 static const struct soc_enum micb_enum =
239 SOC_ENUM_SINGLE(CS42L52_MICB_CTL, 5,
240 ARRAY_SIZE(cs42l52_mic_text), cs42l52_mic_text);
241
242 static const struct snd_kcontrol_new mica_mux =
243 SOC_DAPM_ENUM("Left Mic Input Capture Mux", mica_enum);
244
245 static const struct snd_kcontrol_new micb_mux =
246 SOC_DAPM_ENUM("Right Mic Input Capture Mux", micb_enum);
247
248 static const char * const digital_output_mux_text[] = {"ADC", "DSP"};
249
250 static const struct soc_enum digital_output_mux_enum =
251 SOC_ENUM_SINGLE(CS42L52_ADC_MISC_CTL, 6,
252 ARRAY_SIZE(digital_output_mux_text),
253 digital_output_mux_text);
254
255 static const struct snd_kcontrol_new digital_output_mux =
256 SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum);
257
258 static const char * const hp_gain_num_text[] = {
259 "0.3959", "0.4571", "0.5111", "0.6047",
260 "0.7099", "0.8399", "1.000", "1.1430"
261 };
262
263 static const struct soc_enum hp_gain_enum =
264 SOC_ENUM_SINGLE(CS42L52_PB_CTL1, 4,
265 ARRAY_SIZE(hp_gain_num_text), hp_gain_num_text);
266
267 static const char * const beep_pitch_text[] = {
268 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
269 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
270 };
271
272 static const struct soc_enum beep_pitch_enum =
273 SOC_ENUM_SINGLE(CS42L52_BEEP_FREQ, 4,
274 ARRAY_SIZE(beep_pitch_text), beep_pitch_text);
275
276 static const char * const beep_ontime_text[] = {
277 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
278 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
279 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
280 };
281
282 static const struct soc_enum beep_ontime_enum =
283 SOC_ENUM_SINGLE(CS42L52_BEEP_FREQ, 0,
284 ARRAY_SIZE(beep_ontime_text), beep_ontime_text);
285
286 static const char * const beep_offtime_text[] = {
287 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
288 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
289 };
290
291 static const struct soc_enum beep_offtime_enum =
292 SOC_ENUM_SINGLE(CS42L52_BEEP_VOL, 5,
293 ARRAY_SIZE(beep_offtime_text), beep_offtime_text);
294
295 static const char * const beep_config_text[] = {
296 "Off", "Single", "Multiple", "Continuous"
297 };
298
299 static const struct soc_enum beep_config_enum =
300 SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 6,
301 ARRAY_SIZE(beep_config_text), beep_config_text);
302
303 static const char * const beep_bass_text[] = {
304 "50 Hz", "100 Hz", "200 Hz", "250 Hz"
305 };
306
307 static const struct soc_enum beep_bass_enum =
308 SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 1,
309 ARRAY_SIZE(beep_bass_text), beep_bass_text);
310
311 static const char * const beep_treble_text[] = {
312 "5 kHz", "7 kHz", "10 kHz", " 15 kHz"
313 };
314
315 static const struct soc_enum beep_treble_enum =
316 SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 3,
317 ARRAY_SIZE(beep_treble_text), beep_treble_text);
318
319 static const char * const ng_threshold_text[] = {
320 "-34dB", "-37dB", "-40dB", "-43dB",
321 "-46dB", "-52dB", "-58dB", "-64dB"
322 };
323
324 static const struct soc_enum ng_threshold_enum =
325 SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 2,
326 ARRAY_SIZE(ng_threshold_text), ng_threshold_text);
327
328 static const char * const cs42l52_ng_delay_text[] = {
329 "50ms", "100ms", "150ms", "200ms"};
330
331 static const struct soc_enum ng_delay_enum =
332 SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 0,
333 ARRAY_SIZE(cs42l52_ng_delay_text), cs42l52_ng_delay_text);
334
335 static const char * const cs42l52_ng_type_text[] = {
336 "Apply Specific", "Apply All"
337 };
338
339 static const struct soc_enum ng_type_enum =
340 SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 6,
341 ARRAY_SIZE(cs42l52_ng_type_text), cs42l52_ng_type_text);
342
343 static const char * const left_swap_text[] = {
344 "Left", "LR 2", "Right"};
345
346 static const char * const right_swap_text[] = {
347 "Right", "LR 2", "Left"};
348
349 static const unsigned int swap_values[] = { 0, 1, 3 };
350
351 static const struct soc_enum adca_swap_enum =
352 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 1,
353 ARRAY_SIZE(left_swap_text),
354 left_swap_text,
355 swap_values);
356
357 static const struct snd_kcontrol_new adca_mixer =
358 SOC_DAPM_ENUM("Route", adca_swap_enum);
359
360 static const struct soc_enum pcma_swap_enum =
361 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 1,
362 ARRAY_SIZE(left_swap_text),
363 left_swap_text,
364 swap_values);
365
366 static const struct snd_kcontrol_new pcma_mixer =
367 SOC_DAPM_ENUM("Route", pcma_swap_enum);
368
369 static const struct soc_enum adcb_swap_enum =
370 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 1,
371 ARRAY_SIZE(right_swap_text),
372 right_swap_text,
373 swap_values);
374
375 static const struct snd_kcontrol_new adcb_mixer =
376 SOC_DAPM_ENUM("Route", adcb_swap_enum);
377
378 static const struct soc_enum pcmb_swap_enum =
379 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 1,
380 ARRAY_SIZE(right_swap_text),
381 right_swap_text,
382 swap_values);
383
384 static const struct snd_kcontrol_new pcmb_mixer =
385 SOC_DAPM_ENUM("Route", pcmb_swap_enum);
386
387
388 static const struct snd_kcontrol_new passthrul_ctl =
389 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0);
390
391 static const struct snd_kcontrol_new passthrur_ctl =
392 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0);
393
394 static const struct snd_kcontrol_new spkl_ctl =
395 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1);
396
397 static const struct snd_kcontrol_new spkr_ctl =
398 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1);
399
400 static const struct snd_kcontrol_new hpl_ctl =
401 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1);
402
403 static const struct snd_kcontrol_new hpr_ctl =
404 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1);
405
406 static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
407
408 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL,
409 CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv),
410
411 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL,
412 CS42L52_HPB_VOL, 0, 0x34, 0xCC, hpd_tlv),
413
414 SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
415
416 SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
417 CS42L52_SPKB_VOL, 7, 0x1, 0xff, hl_tlv),
418
419 SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
420 CS42L52_PASSTHRUB_VOL, 6, 0x18, 0x90, pga_tlv),
421
422 SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0),
423
424 SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL,
425 CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv),
426
427 SOC_ENUM("MIC Bias Level", mic_bias_level_enum),
428
429 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL,
430 CS42L52_ADCB_VOL, 7, 0x80, 0xA0, ipd_tlv),
431 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
432 CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL,
433 6, 0x7f, 0x19, ipd_tlv),
434
435 SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0),
436
437 SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL,
438 CS42L52_ADCB_MIXER_VOL, 7, 1, 1),
439
440 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL,
441 CS42L52_PGAB_CTL, 0, 0x28, 0x30, pga_tlv),
442
443 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
444 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
445 6, 0x7f, 0x19, hl_tlv),
446 SOC_DOUBLE_R("PCM Mixer Switch",
447 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
448
449 SOC_ENUM("Beep Config", beep_config_enum),
450 SOC_ENUM("Beep Pitch", beep_pitch_enum),
451 SOC_ENUM("Beep on Time", beep_ontime_enum),
452 SOC_ENUM("Beep off Time", beep_offtime_enum),
453 SOC_SINGLE_TLV("Beep Volume", CS42L52_BEEP_VOL, 0, 0x1f, 0x07, hl_tlv),
454 SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1),
455 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
456 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
457
458 SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1),
459 SOC_SINGLE_TLV("Treble Gain Volume",
460 CS42L52_TONE_CTL, 4, 15, 1, hl_tlv),
461 SOC_SINGLE_TLV("Bass Gain Volume",
462 CS42L52_TONE_CTL, 0, 15, 1, hl_tlv),
463
464 /* Limiter */
465 SOC_SINGLE_TLV("Limiter Max Threshold Volume",
466 CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv),
467 SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
468 CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv),
469 SOC_SINGLE_TLV("Limiter Release Rate Volume",
470 CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv),
471 SOC_SINGLE_TLV("Limiter Attack Rate Volume",
472 CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv),
473
474 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
475 SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
476 SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
477
478 /* ALC */
479 SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL,
480 0, 63, 0, limiter_tlv),
481 SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE,
482 0, 63, 0, limiter_tlv),
483 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD,
484 5, 7, 0, limiter_tlv),
485 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD,
486 2, 7, 0, limiter_tlv),
487
488 SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL,
489 CS42L52_PGAB_CTL, 7, 1, 1),
490 SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL,
491 CS42L52_PGAB_CTL, 6, 1, 1),
492 SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0),
493
494 /* Noise gate */
495 SOC_ENUM("NG Type Switch", ng_type_enum),
496 SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0),
497 SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1),
498 SOC_ENUM("NG Threshold", ng_threshold_enum),
499 SOC_ENUM("NG Delay", ng_delay_enum),
500
501 SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0),
502
503 SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1),
504 SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1),
505 SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
506 SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0),
507 SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0),
508
509 SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0),
510 SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0),
511 SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0),
512
513 SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0),
514 SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0),
515 SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0),
516 SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0),
517
518 SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0),
519 SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0),
520
521 SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0),
522 SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0),
523
524 SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0),
525 SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0),
526
527 };
528
529 static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = {
530
531 SND_SOC_DAPM_INPUT("AIN1L"),
532 SND_SOC_DAPM_INPUT("AIN1R"),
533 SND_SOC_DAPM_INPUT("AIN2L"),
534 SND_SOC_DAPM_INPUT("AIN2R"),
535 SND_SOC_DAPM_INPUT("AIN3L"),
536 SND_SOC_DAPM_INPUT("AIN3R"),
537 SND_SOC_DAPM_INPUT("AIN4L"),
538 SND_SOC_DAPM_INPUT("AIN4R"),
539 SND_SOC_DAPM_INPUT("MICA"),
540 SND_SOC_DAPM_INPUT("MICB"),
541 SND_SOC_DAPM_SIGGEN("Beep"),
542
543 SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL, 0,
544 SND_SOC_NOPM, 0, 0),
545 SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL, 0,
546 SND_SOC_NOPM, 0, 0),
547
548 SND_SOC_DAPM_MUX("MICA Mux", SND_SOC_NOPM, 0, 0, &mica_mux),
549 SND_SOC_DAPM_MUX("MICB Mux", SND_SOC_NOPM, 0, 0, &micb_mux),
550
551 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1),
552 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1),
553 SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0),
554 SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0),
555
556 SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux),
557 SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux),
558
559 SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM,
560 0, 0, &adca_mixer),
561 SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM,
562 0, 0, &adcb_mixer),
563
564 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM,
565 0, 0, &digital_output_mux),
566
567 SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0),
568 SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0),
569
570 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0),
571 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0),
572
573 SND_SOC_DAPM_AIF_IN("AIFINL", NULL, 0,
574 SND_SOC_NOPM, 0, 0),
575 SND_SOC_DAPM_AIF_IN("AIFINR", NULL, 0,
576 SND_SOC_NOPM, 0, 0),
577
578 SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0),
579 SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0),
580
581 SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL,
582 6, 0, &passthrul_ctl),
583 SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL,
584 7, 0, &passthrur_ctl),
585
586 SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM,
587 0, 0, &pcma_mixer),
588 SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM,
589 0, 0, &pcmb_mixer),
590
591 SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl),
592 SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl),
593
594 SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl),
595 SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl),
596
597 SND_SOC_DAPM_OUTPUT("HPOUTA"),
598 SND_SOC_DAPM_OUTPUT("HPOUTB"),
599 SND_SOC_DAPM_OUTPUT("SPKOUTA"),
600 SND_SOC_DAPM_OUTPUT("SPKOUTB"),
601
602 };
603
604 static const struct snd_soc_dapm_route cs42l52_audio_map[] = {
605
606 {"Capture", NULL, "AIFOUTL"},
607 {"Capture", NULL, "AIFOUTL"},
608
609 {"AIFOUTL", NULL, "Output Mux"},
610 {"AIFOUTR", NULL, "Output Mux"},
611
612 {"Output Mux", "ADC", "ADC Left"},
613 {"Output Mux", "ADC", "ADC Right"},
614
615 {"ADC Left", NULL, "Charge Pump"},
616 {"ADC Right", NULL, "Charge Pump"},
617
618 {"Charge Pump", NULL, "ADC Left Mux"},
619 {"Charge Pump", NULL, "ADC Right Mux"},
620
621 {"ADC Left Mux", "Input1A", "AIN1L"},
622 {"ADC Right Mux", "Input1B", "AIN1R"},
623 {"ADC Left Mux", "Input2A", "AIN2L"},
624 {"ADC Right Mux", "Input2B", "AIN2R"},
625 {"ADC Left Mux", "Input3A", "AIN3L"},
626 {"ADC Right Mux", "Input3B", "AIN3R"},
627 {"ADC Left Mux", "Input4A", "AIN4L"},
628 {"ADC Right Mux", "Input4B", "AIN4R"},
629 {"ADC Left Mux", "PGA Input Left", "PGA Left"},
630 {"ADC Right Mux", "PGA Input Right" , "PGA Right"},
631
632 {"PGA Left", "Switch", "AIN1L"},
633 {"PGA Right", "Switch", "AIN1R"},
634 {"PGA Left", "Switch", "AIN2L"},
635 {"PGA Right", "Switch", "AIN2R"},
636 {"PGA Left", "Switch", "AIN3L"},
637 {"PGA Right", "Switch", "AIN3R"},
638 {"PGA Left", "Switch", "AIN4L"},
639 {"PGA Right", "Switch", "AIN4R"},
640
641 {"PGA Left", "Switch", "PGA MICA"},
642 {"PGA MICA", NULL, "MICA"},
643
644 {"PGA Right", "Switch", "PGA MICB"},
645 {"PGA MICB", NULL, "MICB"},
646
647 {"HPOUTA", NULL, "HP Left Amp"},
648 {"HPOUTB", NULL, "HP Right Amp"},
649 {"HP Left Amp", NULL, "Bypass Left"},
650 {"HP Right Amp", NULL, "Bypass Right"},
651 {"Bypass Left", "Switch", "PGA Left"},
652 {"Bypass Right", "Switch", "PGA Right"},
653 {"HP Left Amp", "Switch", "DAC Left"},
654 {"HP Right Amp", "Switch", "DAC Right"},
655
656 {"SPKOUTA", NULL, "SPK Left Amp"},
657 {"SPKOUTB", NULL, "SPK Right Amp"},
658
659 {"SPK Left Amp", NULL, "Beep"},
660 {"SPK Right Amp", NULL, "Beep"},
661 {"SPK Left Amp", "Switch", "Playback"},
662 {"SPK Right Amp", "Switch", "Playback"},
663
664 {"DAC Left", NULL, "Beep"},
665 {"DAC Right", NULL, "Beep"},
666 {"DAC Left", NULL, "Playback"},
667 {"DAC Right", NULL, "Playback"},
668
669 {"Output Mux", "DSP", "Playback"},
670 {"Output Mux", "DSP", "Playback"},
671
672 {"AIFINL", NULL, "Playback"},
673 {"AIFINR", NULL, "Playback"},
674
675 };
676
677 struct cs42l52_clk_para {
678 u32 mclk;
679 u32 rate;
680 u8 speed;
681 u8 group;
682 u8 videoclk;
683 u8 ratio;
684 u8 mclkdiv2;
685 };
686
687 static const struct cs42l52_clk_para clk_map_table[] = {
688 /*8k*/
689 {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
690 {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
691 {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
692 {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
693 {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
694
695 /*11.025k*/
696 {11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
697 {16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
698
699 /*16k*/
700 {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
701 {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
702 {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
703 {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
704 {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1},
705
706 /*22.05k*/
707 {11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
708 {16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
709
710 /* 32k */
711 {12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
712 {18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
713 {12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
714 {24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
715 {27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
716
717 /* 44.1k */
718 {11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
719 {16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
720
721 /* 48k */
722 {12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
723 {18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
724 {12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
725 {24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
726 {27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1},
727
728 /* 88.2k */
729 {11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
730 {16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
731
732 /* 96k */
733 {12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
734 {18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
735 {12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
736 {24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
737 };
738
739 static int cs42l52_get_clk(int mclk, int rate)
740 {
741 int i, ret = 0;
742 u_int mclk1, mclk2 = 0;
743
744 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
745 if (clk_map_table[i].rate == rate) {
746 mclk1 = clk_map_table[i].mclk;
747 if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
748 mclk2 = mclk1;
749 ret = i;
750 }
751 }
752 }
753 if (ret > ARRAY_SIZE(clk_map_table))
754 return -EINVAL;
755 return ret;
756 }
757
758 static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai,
759 int clk_id, unsigned int freq, int dir)
760 {
761 struct snd_soc_codec *codec = codec_dai->codec;
762 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
763
764 if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) {
765 cs42l52->sysclk = freq;
766 } else {
767 dev_err(codec->dev, "Invalid freq paramter\n");
768 return -EINVAL;
769 }
770 return 0;
771 }
772
773 static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
774 {
775 struct snd_soc_codec *codec = codec_dai->codec;
776 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
777 int ret = 0;
778 u8 iface = 0;
779
780 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
781 case SND_SOC_DAIFMT_CBM_CFM:
782 iface = CS42L52_IFACE_CTL1_MASTER;
783 break;
784 case SND_SOC_DAIFMT_CBS_CFS:
785 iface = CS42L52_IFACE_CTL1_SLAVE;
786 break;
787 default:
788 return -EINVAL;
789 }
790
791 /* interface format */
792 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
793 case SND_SOC_DAIFMT_I2S:
794 iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S |
795 CS42L52_IFACE_CTL1_DAC_FMT_I2S;
796 break;
797 case SND_SOC_DAIFMT_RIGHT_J:
798 iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J;
799 break;
800 case SND_SOC_DAIFMT_LEFT_J:
801 iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J |
802 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J;
803 break;
804 case SND_SOC_DAIFMT_DSP_A:
805 iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN;
806 break;
807 case SND_SOC_DAIFMT_DSP_B:
808 break;
809 default:
810 return -EINVAL;
811 }
812
813 /* clock inversion */
814 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
815 case SND_SOC_DAIFMT_NB_NF:
816 break;
817 case SND_SOC_DAIFMT_IB_IF:
818 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
819 break;
820 case SND_SOC_DAIFMT_IB_NF:
821 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
822 break;
823 case SND_SOC_DAIFMT_NB_IF:
824 break;
825 default:
826 ret = -EINVAL;
827 }
828 cs42l52->config.format = iface;
829 snd_soc_write(codec, CS42L52_IFACE_CTL1, cs42l52->config.format);
830
831 return 0;
832 }
833
834 static int cs42l52_digital_mute(struct snd_soc_dai *dai, int mute)
835 {
836 struct snd_soc_codec *codec = dai->codec;
837
838 if (mute)
839 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
840 CS42L52_PB_CTL1_MUTE_MASK,
841 CS42L52_PB_CTL1_MUTE);
842 else
843 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
844 CS42L52_PB_CTL1_MUTE_MASK,
845 CS42L52_PB_CTL1_UNMUTE);
846
847 return 0;
848 }
849
850 static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream,
851 struct snd_pcm_hw_params *params,
852 struct snd_soc_dai *dai)
853 {
854 struct snd_soc_codec *codec = dai->codec;
855 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
856 u32 clk = 0;
857 int index;
858
859 index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
860 if (index >= 0) {
861 cs42l52->sysclk = clk_map_table[index].mclk;
862
863 clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) |
864 (clk_map_table[index].group << CLK_32K_SR_SHIFT) |
865 (clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) |
866 (clk_map_table[index].ratio << CLK_RATIO_SHIFT) |
867 clk_map_table[index].mclkdiv2;
868
869 snd_soc_write(codec, CS42L52_CLK_CTL, clk);
870 } else {
871 dev_err(codec->dev, "can't get correct mclk\n");
872 return -EINVAL;
873 }
874
875 return 0;
876 }
877
878 static int cs42l52_set_bias_level(struct snd_soc_codec *codec,
879 enum snd_soc_bias_level level)
880 {
881 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
882
883 switch (level) {
884 case SND_SOC_BIAS_ON:
885 break;
886 case SND_SOC_BIAS_PREPARE:
887 snd_soc_update_bits(codec, CS42L52_PWRCTL1,
888 CS42L52_PWRCTL1_PDN_CODEC, 0);
889 break;
890 case SND_SOC_BIAS_STANDBY:
891 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
892 regcache_cache_only(cs42l52->regmap, false);
893 regcache_sync(cs42l52->regmap);
894 }
895 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
896 break;
897 case SND_SOC_BIAS_OFF:
898 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
899 regcache_cache_only(cs42l52->regmap, true);
900 break;
901 }
902 codec->dapm.bias_level = level;
903
904 return 0;
905 }
906
907 #define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
908
909 #define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
910 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
911 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
912 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
913
914 static struct snd_soc_dai_ops cs42l52_ops = {
915 .hw_params = cs42l52_pcm_hw_params,
916 .digital_mute = cs42l52_digital_mute,
917 .set_fmt = cs42l52_set_fmt,
918 .set_sysclk = cs42l52_set_sysclk,
919 };
920
921 static struct snd_soc_dai_driver cs42l52_dai = {
922 .name = "cs42l52",
923 .playback = {
924 .stream_name = "Playback",
925 .channels_min = 1,
926 .channels_max = 2,
927 .rates = CS42L52_RATES,
928 .formats = CS42L52_FORMATS,
929 },
930 .capture = {
931 .stream_name = "Capture",
932 .channels_min = 1,
933 .channels_max = 2,
934 .rates = CS42L52_RATES,
935 .formats = CS42L52_FORMATS,
936 },
937 .ops = &cs42l52_ops,
938 };
939
940 static int cs42l52_suspend(struct snd_soc_codec *codec)
941 {
942 cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
943
944 return 0;
945 }
946
947 static int cs42l52_resume(struct snd_soc_codec *codec)
948 {
949 cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
950
951 return 0;
952 }
953
954 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
955 static int beep_rates[] = {
956 261, 522, 585, 667, 706, 774, 889, 1000,
957 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
958 };
959
960 static void cs42l52_beep_work(struct work_struct *work)
961 {
962 struct cs42l52_private *cs42l52 =
963 container_of(work, struct cs42l52_private, beep_work);
964 struct snd_soc_codec *codec = cs42l52->codec;
965 struct snd_soc_dapm_context *dapm = &codec->dapm;
966 int i;
967 int val = 0;
968 int best = 0;
969
970 if (cs42l52->beep_rate) {
971 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
972 if (abs(cs42l52->beep_rate - beep_rates[i]) <
973 abs(cs42l52->beep_rate - beep_rates[best]))
974 best = i;
975 }
976
977 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
978 beep_rates[best], cs42l52->beep_rate);
979
980 val = (best << CS42L52_BEEP_RATE_SHIFT);
981
982 snd_soc_dapm_enable_pin(dapm, "Beep");
983 } else {
984 dev_dbg(codec->dev, "Disabling beep\n");
985 snd_soc_dapm_disable_pin(dapm, "Beep");
986 }
987
988 snd_soc_update_bits(codec, CS42L52_BEEP_FREQ,
989 CS42L52_BEEP_RATE_MASK, val);
990
991 snd_soc_dapm_sync(dapm);
992 }
993
994 /* For usability define a way of injecting beep events for the device -
995 * many systems will not have a keyboard.
996 */
997 static int cs42l52_beep_event(struct input_dev *dev, unsigned int type,
998 unsigned int code, int hz)
999 {
1000 struct snd_soc_codec *codec = input_get_drvdata(dev);
1001 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1002
1003 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1004
1005 switch (code) {
1006 case SND_BELL:
1007 if (hz)
1008 hz = 261;
1009 case SND_TONE:
1010 break;
1011 default:
1012 return -1;
1013 }
1014
1015 /* Kick the beep from a workqueue */
1016 cs42l52->beep_rate = hz;
1017 schedule_work(&cs42l52->beep_work);
1018 return 0;
1019 }
1020
1021 static ssize_t cs42l52_beep_set(struct device *dev,
1022 struct device_attribute *attr,
1023 const char *buf, size_t count)
1024 {
1025 struct cs42l52_private *cs42l52 = dev_get_drvdata(dev);
1026 long int time;
1027 int ret;
1028
1029 ret = kstrtol(buf, 10, &time);
1030 if (ret != 0)
1031 return ret;
1032
1033 input_event(cs42l52->beep, EV_SND, SND_TONE, time);
1034
1035 return count;
1036 }
1037
1038 static DEVICE_ATTR(beep, 0200, NULL, cs42l52_beep_set);
1039
1040 static void cs42l52_init_beep(struct snd_soc_codec *codec)
1041 {
1042 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1043 int ret;
1044
1045 cs42l52->beep = input_allocate_device();
1046 if (!cs42l52->beep) {
1047 dev_err(codec->dev, "Failed to allocate beep device\n");
1048 return;
1049 }
1050
1051 INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
1052 cs42l52->beep_rate = 0;
1053
1054 cs42l52->beep->name = "CS42L52 Beep Generator";
1055 cs42l52->beep->phys = dev_name(codec->dev);
1056 cs42l52->beep->id.bustype = BUS_I2C;
1057
1058 cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
1059 cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1060 cs42l52->beep->event = cs42l52_beep_event;
1061 cs42l52->beep->dev.parent = codec->dev;
1062 input_set_drvdata(cs42l52->beep, codec);
1063
1064 ret = input_register_device(cs42l52->beep);
1065 if (ret != 0) {
1066 input_free_device(cs42l52->beep);
1067 cs42l52->beep = NULL;
1068 dev_err(codec->dev, "Failed to register beep device\n");
1069 }
1070
1071 ret = device_create_file(codec->dev, &dev_attr_beep);
1072 if (ret != 0) {
1073 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1074 ret);
1075 }
1076 }
1077
1078 static void cs42l52_free_beep(struct snd_soc_codec *codec)
1079 {
1080 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1081
1082 device_remove_file(codec->dev, &dev_attr_beep);
1083 input_unregister_device(cs42l52->beep);
1084 cancel_work_sync(&cs42l52->beep_work);
1085 cs42l52->beep = NULL;
1086
1087 snd_soc_update_bits(codec, CS42L52_BEEP_TONE_CTL,
1088 CS42L52_BEEP_EN_MASK, 0);
1089 }
1090 #else
1091 static void cs42l52_init_beep(struct snd_soc_codec *codec)
1092 {
1093 }
1094
1095 static void cs42l52_free_beep(struct snd_soc_codec *codec)
1096 {
1097 }
1098 #endif
1099
1100 static int cs42l52_probe(struct snd_soc_codec *codec)
1101 {
1102 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1103 int ret;
1104
1105 codec->control_data = cs42l52->regmap;
1106 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1107 if (ret < 0) {
1108 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1109 return ret;
1110 }
1111 regcache_cache_only(cs42l52->regmap, true);
1112
1113 cs42l52_init_beep(codec);
1114
1115 cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1116
1117 cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1118 cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1119
1120 /* Set Platform MICx CFG */
1121 snd_soc_update_bits(codec, CS42L52_MICA_CTL,
1122 CS42L52_MIC_CTL_TYPE_MASK,
1123 cs42l52->pdata.mica_cfg <<
1124 CS42L52_MIC_CTL_TYPE_SHIFT);
1125
1126 snd_soc_update_bits(codec, CS42L52_MICB_CTL,
1127 CS42L52_MIC_CTL_TYPE_MASK,
1128 cs42l52->pdata.micb_cfg <<
1129 CS42L52_MIC_CTL_TYPE_SHIFT);
1130
1131 /* if Single Ended, Get Mic_Select */
1132 if (cs42l52->pdata.mica_cfg)
1133 snd_soc_update_bits(codec, CS42L52_MICA_CTL,
1134 CS42L52_MIC_CTL_MIC_SEL_MASK,
1135 cs42l52->pdata.mica_sel <<
1136 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1137 if (cs42l52->pdata.micb_cfg)
1138 snd_soc_update_bits(codec, CS42L52_MICB_CTL,
1139 CS42L52_MIC_CTL_MIC_SEL_MASK,
1140 cs42l52->pdata.micb_sel <<
1141 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1142
1143 /* Set Platform Charge Pump Freq */
1144 snd_soc_update_bits(codec, CS42L52_CHARGE_PUMP,
1145 CS42L52_CHARGE_PUMP_MASK,
1146 cs42l52->pdata.chgfreq <<
1147 CS42L52_CHARGE_PUMP_SHIFT);
1148
1149 /* Set Platform Bias Level */
1150 snd_soc_update_bits(codec, CS42L52_IFACE_CTL2,
1151 CS42L52_IFACE_CTL2_BIAS_LVL,
1152 cs42l52->pdata.micbias_lvl);
1153
1154 return ret;
1155 }
1156
1157 static int cs42l52_remove(struct snd_soc_codec *codec)
1158 {
1159 cs42l52_free_beep(codec);
1160 cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
1161
1162 return 0;
1163 }
1164
1165 static struct snd_soc_codec_driver soc_codec_dev_cs42l52 = {
1166 .probe = cs42l52_probe,
1167 .remove = cs42l52_remove,
1168 .suspend = cs42l52_suspend,
1169 .resume = cs42l52_resume,
1170 .set_bias_level = cs42l52_set_bias_level,
1171
1172 .dapm_widgets = cs42l52_dapm_widgets,
1173 .num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets),
1174 .dapm_routes = cs42l52_audio_map,
1175 .num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map),
1176
1177 .controls = cs42l52_snd_controls,
1178 .num_controls = ARRAY_SIZE(cs42l52_snd_controls),
1179 };
1180
1181 /* Current and threshold powerup sequence Pg37 */
1182 static const struct reg_default cs42l52_threshold_patch[] = {
1183
1184 { 0x00, 0x99 },
1185 { 0x3E, 0xBA },
1186 { 0x47, 0x80 },
1187 { 0x32, 0xBB },
1188 { 0x32, 0x3B },
1189 { 0x00, 0x00 },
1190
1191 };
1192
1193 static struct regmap_config cs42l52_regmap = {
1194 .reg_bits = 8,
1195 .val_bits = 8,
1196
1197 .max_register = CS42L52_MAX_REGISTER,
1198 .reg_defaults = cs42l52_reg_defaults,
1199 .num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults),
1200 .readable_reg = cs42l52_readable_register,
1201 .volatile_reg = cs42l52_volatile_register,
1202 .cache_type = REGCACHE_RBTREE,
1203 };
1204
1205 static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1206 const struct i2c_device_id *id)
1207 {
1208 struct cs42l52_private *cs42l52;
1209 int ret;
1210 unsigned int devid = 0;
1211 unsigned int reg;
1212
1213 cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l52_private),
1214 GFP_KERNEL);
1215 if (cs42l52 == NULL)
1216 return -ENOMEM;
1217 cs42l52->dev = &i2c_client->dev;
1218
1219 cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap);
1220 if (IS_ERR(cs42l52->regmap)) {
1221 ret = PTR_ERR(cs42l52->regmap);
1222 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1223 return ret;
1224 }
1225
1226 i2c_set_clientdata(i2c_client, cs42l52);
1227
1228 if (dev_get_platdata(&i2c_client->dev))
1229 memcpy(&cs42l52->pdata, dev_get_platdata(&i2c_client->dev),
1230 sizeof(cs42l52->pdata));
1231
1232 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1233 ARRAY_SIZE(cs42l52_threshold_patch));
1234 if (ret != 0)
1235 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
1236 ret);
1237
1238 ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, &reg);
1239 devid = reg & CS42L52_CHIP_ID_MASK;
1240 if (devid != CS42L52_CHIP_ID) {
1241 ret = -ENODEV;
1242 dev_err(&i2c_client->dev,
1243 "CS42L52 Device ID (%X). Expected %X\n",
1244 devid, CS42L52_CHIP_ID);
1245 return ret;
1246 }
1247
1248 regcache_cache_only(cs42l52->regmap, true);
1249
1250 ret = snd_soc_register_codec(&i2c_client->dev,
1251 &soc_codec_dev_cs42l52, &cs42l52_dai, 1);
1252 if (ret < 0)
1253 return ret;
1254 return 0;
1255 }
1256
1257 static int cs42l52_i2c_remove(struct i2c_client *client)
1258 {
1259 snd_soc_unregister_codec(&client->dev);
1260 return 0;
1261 }
1262
1263 static const struct i2c_device_id cs42l52_id[] = {
1264 { "cs42l52", 0 },
1265 { }
1266 };
1267 MODULE_DEVICE_TABLE(i2c, cs42l52_id);
1268
1269 static struct i2c_driver cs42l52_i2c_driver = {
1270 .driver = {
1271 .name = "cs42l52",
1272 .owner = THIS_MODULE,
1273 },
1274 .id_table = cs42l52_id,
1275 .probe = cs42l52_i2c_probe,
1276 .remove = __devexit_p(cs42l52_i2c_remove),
1277 };
1278
1279 module_i2c_driver(cs42l52_i2c_driver);
1280
1281 MODULE_DESCRIPTION("ASoC CS42L52 driver");
1282 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1283 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1284 MODULE_LICENSE("GPL");
Linux with added FPC-III support