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Revert "microblaze_mmu_v2: Update signal returning address"
[linux/fpc-iii.git] / sound / soc / codecs / wm8580.c
blob7c68226376e415a5e058bb10153531b68d49c990
1 /*
2 * wm8580.c -- WM8580 ALSA Soc Audio driver
3 *
4 * Copyright 2008-11 Wolfson Microelectronics PLC.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Notes:
12 * The WM8580 is a multichannel codec with S/PDIF support, featuring six
13 * DAC channels and two ADC channels.
14 *
15 * Currently only the primary audio interface is supported - S/PDIF and
16 * the secondary audio interfaces are not.
17 */
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/pm.h>
25 #include <linux/i2c.h>
26 #include <linux/regulator/consumer.h>
27 #include <linux/slab.h>
28 #include <linux/of_device.h>
29
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/tlv.h>
35 #include <sound/initval.h>
36 #include <asm/div64.h>
37
38 #include "wm8580.h"
39
40 /* WM8580 register space */
41 #define WM8580_PLLA1 0x00
42 #define WM8580_PLLA2 0x01
43 #define WM8580_PLLA3 0x02
44 #define WM8580_PLLA4 0x03
45 #define WM8580_PLLB1 0x04
46 #define WM8580_PLLB2 0x05
47 #define WM8580_PLLB3 0x06
48 #define WM8580_PLLB4 0x07
49 #define WM8580_CLKSEL 0x08
50 #define WM8580_PAIF1 0x09
51 #define WM8580_PAIF2 0x0A
52 #define WM8580_SAIF1 0x0B
53 #define WM8580_PAIF3 0x0C
54 #define WM8580_PAIF4 0x0D
55 #define WM8580_SAIF2 0x0E
56 #define WM8580_DAC_CONTROL1 0x0F
57 #define WM8580_DAC_CONTROL2 0x10
58 #define WM8580_DAC_CONTROL3 0x11
59 #define WM8580_DAC_CONTROL4 0x12
60 #define WM8580_DAC_CONTROL5 0x13
61 #define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
62 #define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
63 #define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
64 #define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
65 #define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
66 #define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
67 #define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
68 #define WM8580_ADC_CONTROL1 0x1D
69 #define WM8580_SPDTXCHAN0 0x1E
70 #define WM8580_SPDTXCHAN1 0x1F
71 #define WM8580_SPDTXCHAN2 0x20
72 #define WM8580_SPDTXCHAN3 0x21
73 #define WM8580_SPDTXCHAN4 0x22
74 #define WM8580_SPDTXCHAN5 0x23
75 #define WM8580_SPDMODE 0x24
76 #define WM8580_INTMASK 0x25
77 #define WM8580_GPO1 0x26
78 #define WM8580_GPO2 0x27
79 #define WM8580_GPO3 0x28
80 #define WM8580_GPO4 0x29
81 #define WM8580_GPO5 0x2A
82 #define WM8580_INTSTAT 0x2B
83 #define WM8580_SPDRXCHAN1 0x2C
84 #define WM8580_SPDRXCHAN2 0x2D
85 #define WM8580_SPDRXCHAN3 0x2E
86 #define WM8580_SPDRXCHAN4 0x2F
87 #define WM8580_SPDRXCHAN5 0x30
88 #define WM8580_SPDSTAT 0x31
89 #define WM8580_PWRDN1 0x32
90 #define WM8580_PWRDN2 0x33
91 #define WM8580_READBACK 0x34
92 #define WM8580_RESET 0x35
93
94 #define WM8580_MAX_REGISTER 0x35
95
96 #define WM8580_DACOSR 0x40
97
98 /* PLLB4 (register 7h) */
99 #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
100 #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
101 #define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
102 #define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
103
104 #define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
105 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
106 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
107 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
108
109 /* CLKSEL (register 8h) */
110 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
111 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
112 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
113
114 /* AIF control 1 (registers 9h-bh) */
115 #define WM8580_AIF_RATE_MASK 0x7
116 #define WM8580_AIF_BCLKSEL_MASK 0x18
117
118 #define WM8580_AIF_MS 0x20
119
120 #define WM8580_AIF_CLKSRC_MASK 0xc0
121 #define WM8580_AIF_CLKSRC_PLLA 0x40
122 #define WM8580_AIF_CLKSRC_PLLB 0x40
123 #define WM8580_AIF_CLKSRC_MCLK 0xc0
124
125 /* AIF control 2 (registers ch-eh) */
126 #define WM8580_AIF_FMT_MASK 0x03
127 #define WM8580_AIF_FMT_RIGHTJ 0x00
128 #define WM8580_AIF_FMT_LEFTJ 0x01
129 #define WM8580_AIF_FMT_I2S 0x02
130 #define WM8580_AIF_FMT_DSP 0x03
131
132 #define WM8580_AIF_LENGTH_MASK 0x0c
133 #define WM8580_AIF_LENGTH_16 0x00
134 #define WM8580_AIF_LENGTH_20 0x04
135 #define WM8580_AIF_LENGTH_24 0x08
136 #define WM8580_AIF_LENGTH_32 0x0c
137
138 #define WM8580_AIF_LRP 0x10
139 #define WM8580_AIF_BCP 0x20
140
141 /* Powerdown Register 1 (register 32h) */
142 #define WM8580_PWRDN1_PWDN 0x001
143 #define WM8580_PWRDN1_ALLDACPD 0x040
144
145 /* Powerdown Register 2 (register 33h) */
146 #define WM8580_PWRDN2_OSSCPD 0x001
147 #define WM8580_PWRDN2_PLLAPD 0x002
148 #define WM8580_PWRDN2_PLLBPD 0x004
149 #define WM8580_PWRDN2_SPDIFPD 0x008
150 #define WM8580_PWRDN2_SPDIFTXD 0x010
151 #define WM8580_PWRDN2_SPDIFRXD 0x020
152
153 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
154
155 /*
156 * wm8580 register cache
157 * We can't read the WM8580 register space when we
158 * are using 2 wire for device control, so we cache them instead.
159 */
160 static const u16 wm8580_reg[] = {
161 0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
162 0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
163 0x0010, 0x0002, 0x0002, 0x00c2, /*R11*/
164 0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
165 0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
166 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
167 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
168 0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
169 0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
170 0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
171 0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
172 0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
173 0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
174 0x0000, 0x0000 /*R53*/
175 };
176
177 struct pll_state {
178 unsigned int in;
179 unsigned int out;
180 };
181
182 #define WM8580_NUM_SUPPLIES 3
183 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
184 "AVDD",
185 "DVDD",
186 "PVDD",
187 };
188
189 /* codec private data */
190 struct wm8580_priv {
191 enum snd_soc_control_type control_type;
192 struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
193 struct pll_state a;
194 struct pll_state b;
195 int sysclk[2];
196 };
197
198 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
199
200 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
201 struct snd_ctl_elem_value *ucontrol)
202 {
203 struct soc_mixer_control *mc =
204 (struct soc_mixer_control *)kcontrol->private_value;
205 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
206 u16 *reg_cache = codec->reg_cache;
207 unsigned int reg = mc->reg;
208 unsigned int reg2 = mc->rreg;
209 int ret;
210
211 /* Clear the register cache so we write without VU set */
212 reg_cache[reg] = 0;
213 reg_cache[reg2] = 0;
214
215 ret = snd_soc_put_volsw(kcontrol, ucontrol);
216 if (ret < 0)
217 return ret;
218
219 /* Now write again with the volume update bit set */
220 snd_soc_update_bits(codec, reg, 0x100, 0x100);
221 snd_soc_update_bits(codec, reg2, 0x100, 0x100);
222
223 return 0;
224 }
225
226 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
227 SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume",
228 WM8580_DIGITAL_ATTENUATION_DACL1,
229 WM8580_DIGITAL_ATTENUATION_DACR1,
230 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
231 SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume",
232 WM8580_DIGITAL_ATTENUATION_DACL2,
233 WM8580_DIGITAL_ATTENUATION_DACR2,
234 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
235 SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume",
236 WM8580_DIGITAL_ATTENUATION_DACL3,
237 WM8580_DIGITAL_ATTENUATION_DACR3,
238 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv),
239
240 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
241 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
242 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
243
244 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0),
245 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0),
246 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0),
247
248 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
249 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
250 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
251 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
252
253 SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
254 SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
255 };
256
257 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
258 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
259 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
260 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
261
262 SND_SOC_DAPM_OUTPUT("VOUT1L"),
263 SND_SOC_DAPM_OUTPUT("VOUT1R"),
264 SND_SOC_DAPM_OUTPUT("VOUT2L"),
265 SND_SOC_DAPM_OUTPUT("VOUT2R"),
266 SND_SOC_DAPM_OUTPUT("VOUT3L"),
267 SND_SOC_DAPM_OUTPUT("VOUT3R"),
268
269 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
270
271 SND_SOC_DAPM_INPUT("AINL"),
272 SND_SOC_DAPM_INPUT("AINR"),
273 };
274
275 static const struct snd_soc_dapm_route wm8580_dapm_routes[] = {
276 { "VOUT1L", NULL, "DAC1" },
277 { "VOUT1R", NULL, "DAC1" },
278
279 { "VOUT2L", NULL, "DAC2" },
280 { "VOUT2R", NULL, "DAC2" },
281
282 { "VOUT3L", NULL, "DAC3" },
283 { "VOUT3R", NULL, "DAC3" },
284
285 { "ADC", NULL, "AINL" },
286 { "ADC", NULL, "AINR" },
287 };
288
289 /* PLL divisors */
290 struct _pll_div {
291 u32 prescale:1;
292 u32 postscale:1;
293 u32 freqmode:2;
294 u32 n:4;
295 u32 k:24;
296 };
297
298 /* The size in bits of the pll divide */
299 #define FIXED_PLL_SIZE (1 << 22)
300
301 /* PLL rate to output rate divisions */
302 static struct {
303 unsigned int div;
304 unsigned int freqmode;
305 unsigned int postscale;
306 } post_table[] = {
307 { 2, 0, 0 },
308 { 4, 0, 1 },
309 { 4, 1, 0 },
310 { 8, 1, 1 },
311 { 8, 2, 0 },
312 { 16, 2, 1 },
313 { 12, 3, 0 },
314 { 24, 3, 1 }
315 };
316
317 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
318 unsigned int source)
319 {
320 u64 Kpart;
321 unsigned int K, Ndiv, Nmod;
322 int i;
323
324 pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
325
326 /* Scale the output frequency up; the PLL should run in the
327 * region of 90-100MHz.
328 */
329 for (i = 0; i < ARRAY_SIZE(post_table); i++) {
330 if (target * post_table[i].div >= 90000000 &&
331 target * post_table[i].div <= 100000000) {
332 pll_div->freqmode = post_table[i].freqmode;
333 pll_div->postscale = post_table[i].postscale;
334 target *= post_table[i].div;
335 break;
336 }
337 }
338
339 if (i == ARRAY_SIZE(post_table)) {
340 printk(KERN_ERR "wm8580: Unable to scale output frequency "
341 "%u\n", target);
342 return -EINVAL;
343 }
344
345 Ndiv = target / source;
346
347 if (Ndiv < 5) {
348 source /= 2;
349 pll_div->prescale = 1;
350 Ndiv = target / source;
351 } else
352 pll_div->prescale = 0;
353
354 if ((Ndiv < 5) || (Ndiv > 13)) {
355 printk(KERN_ERR
356 "WM8580 N=%u outside supported range\n", Ndiv);
357 return -EINVAL;
358 }
359
360 pll_div->n = Ndiv;
361 Nmod = target % source;
362 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
363
364 do_div(Kpart, source);
365
366 K = Kpart & 0xFFFFFFFF;
367
368 pll_div->k = K;
369
370 pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
371 pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
372 pll_div->postscale);
373
374 return 0;
375 }
376
377 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
378 int source, unsigned int freq_in, unsigned int freq_out)
379 {
380 int offset;
381 struct snd_soc_codec *codec = codec_dai->codec;
382 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
383 struct pll_state *state;
384 struct _pll_div pll_div;
385 unsigned int reg;
386 unsigned int pwr_mask;
387 int ret;
388
389 /* GCC isn't able to work out the ifs below for initialising/using
390 * pll_div so suppress warnings.
391 */
392 memset(&pll_div, 0, sizeof(pll_div));
393
394 switch (pll_id) {
395 case WM8580_PLLA:
396 state = &wm8580->a;
397 offset = 0;
398 pwr_mask = WM8580_PWRDN2_PLLAPD;
399 break;
400 case WM8580_PLLB:
401 state = &wm8580->b;
402 offset = 4;
403 pwr_mask = WM8580_PWRDN2_PLLBPD;
404 break;
405 default:
406 return -ENODEV;
407 }
408
409 if (freq_in && freq_out) {
410 ret = pll_factors(&pll_div, freq_out, freq_in);
411 if (ret != 0)
412 return ret;
413 }
414
415 state->in = freq_in;
416 state->out = freq_out;
417
418 /* Always disable the PLL - it is not safe to leave it running
419 * while reprogramming it.
420 */
421 snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, pwr_mask);
422
423 if (!freq_in || !freq_out)
424 return 0;
425
426 snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
427 snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
428 snd_soc_write(codec, WM8580_PLLA3 + offset,
429 (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
430
431 reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
432 reg &= ~0x1b;
433 reg |= pll_div.prescale | pll_div.postscale << 1 |
434 pll_div.freqmode << 3;
435
436 snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
437
438 /* All done, turn it on */
439 snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, 0);
440
441 return 0;
442 }
443
444 static const int wm8580_sysclk_ratios[] = {
445 128, 192, 256, 384, 512, 768, 1152,
446 };
447
448 /*
449 * Set PCM DAI bit size and sample rate.
450 */
451 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
452 struct snd_pcm_hw_params *params,
453 struct snd_soc_dai *dai)
454 {
455 struct snd_soc_pcm_runtime *rtd = substream->private_data;
456 struct snd_soc_codec *codec = rtd->codec;
457 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
458 u16 paifa = 0;
459 u16 paifb = 0;
460 int i, ratio, osr;
461
462 /* bit size */
463 switch (params_format(params)) {
464 case SNDRV_PCM_FORMAT_S16_LE:
465 paifa |= 0x8;
466 break;
467 case SNDRV_PCM_FORMAT_S20_3LE:
468 paifa |= 0x0;
469 paifb |= WM8580_AIF_LENGTH_20;
470 break;
471 case SNDRV_PCM_FORMAT_S24_LE:
472 paifa |= 0x0;
473 paifb |= WM8580_AIF_LENGTH_24;
474 break;
475 case SNDRV_PCM_FORMAT_S32_LE:
476 paifa |= 0x0;
477 paifb |= WM8580_AIF_LENGTH_32;
478 break;
479 default:
480 return -EINVAL;
481 }
482
483 /* Look up the SYSCLK ratio; accept only exact matches */
484 ratio = wm8580->sysclk[dai->driver->id] / params_rate(params);
485 for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
486 if (ratio == wm8580_sysclk_ratios[i])
487 break;
488 if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
489 dev_err(codec->dev, "Invalid clock ratio %d/%d\n",
490 wm8580->sysclk[dai->driver->id], params_rate(params));
491 return -EINVAL;
492 }
493 paifa |= i;
494 dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n",
495 wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
496
497 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
498 switch (ratio) {
499 case 128:
500 case 192:
501 osr = WM8580_DACOSR;
502 dev_dbg(codec->dev, "Selecting 64x OSR\n");
503 break;
504 default:
505 osr = 0;
506 dev_dbg(codec->dev, "Selecting 128x OSR\n");
507 break;
508 }
509
510 snd_soc_update_bits(codec, WM8580_PAIF3, WM8580_DACOSR, osr);
511 }
512
513 snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id,
514 WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
515 paifa);
516 snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id,
517 WM8580_AIF_LENGTH_MASK, paifb);
518 return 0;
519 }
520
521 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
522 unsigned int fmt)
523 {
524 struct snd_soc_codec *codec = codec_dai->codec;
525 unsigned int aifa;
526 unsigned int aifb;
527 int can_invert_lrclk;
528
529 aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
530 aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
531
532 aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
533
534 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
535 case SND_SOC_DAIFMT_CBS_CFS:
536 aifa &= ~WM8580_AIF_MS;
537 break;
538 case SND_SOC_DAIFMT_CBM_CFM:
539 aifa |= WM8580_AIF_MS;
540 break;
541 default:
542 return -EINVAL;
543 }
544
545 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
546 case SND_SOC_DAIFMT_I2S:
547 can_invert_lrclk = 1;
548 aifb |= WM8580_AIF_FMT_I2S;
549 break;
550 case SND_SOC_DAIFMT_RIGHT_J:
551 can_invert_lrclk = 1;
552 aifb |= WM8580_AIF_FMT_RIGHTJ;
553 break;
554 case SND_SOC_DAIFMT_LEFT_J:
555 can_invert_lrclk = 1;
556 aifb |= WM8580_AIF_FMT_LEFTJ;
557 break;
558 case SND_SOC_DAIFMT_DSP_A:
559 can_invert_lrclk = 0;
560 aifb |= WM8580_AIF_FMT_DSP;
561 break;
562 case SND_SOC_DAIFMT_DSP_B:
563 can_invert_lrclk = 0;
564 aifb |= WM8580_AIF_FMT_DSP;
565 aifb |= WM8580_AIF_LRP;
566 break;
567 default:
568 return -EINVAL;
569 }
570
571 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
572 case SND_SOC_DAIFMT_NB_NF:
573 break;
574
575 case SND_SOC_DAIFMT_IB_IF:
576 if (!can_invert_lrclk)
577 return -EINVAL;
578 aifb |= WM8580_AIF_BCP;
579 aifb |= WM8580_AIF_LRP;
580 break;
581
582 case SND_SOC_DAIFMT_IB_NF:
583 aifb |= WM8580_AIF_BCP;
584 break;
585
586 case SND_SOC_DAIFMT_NB_IF:
587 if (!can_invert_lrclk)
588 return -EINVAL;
589 aifb |= WM8580_AIF_LRP;
590 break;
591
592 default:
593 return -EINVAL;
594 }
595
596 snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
597 snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
598
599 return 0;
600 }
601
602 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
603 int div_id, int div)
604 {
605 struct snd_soc_codec *codec = codec_dai->codec;
606 unsigned int reg;
607
608 switch (div_id) {
609 case WM8580_MCLK:
610 reg = snd_soc_read(codec, WM8580_PLLB4);
611 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
612
613 switch (div) {
614 case WM8580_CLKSRC_MCLK:
615 /* Input */
616 break;
617
618 case WM8580_CLKSRC_PLLA:
619 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
620 break;
621 case WM8580_CLKSRC_PLLB:
622 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
623 break;
624
625 case WM8580_CLKSRC_OSC:
626 reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
627 break;
628
629 default:
630 return -EINVAL;
631 }
632 snd_soc_write(codec, WM8580_PLLB4, reg);
633 break;
634
635 case WM8580_CLKOUTSRC:
636 reg = snd_soc_read(codec, WM8580_PLLB4);
637 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
638
639 switch (div) {
640 case WM8580_CLKSRC_NONE:
641 break;
642
643 case WM8580_CLKSRC_PLLA:
644 reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
645 break;
646
647 case WM8580_CLKSRC_PLLB:
648 reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
649 break;
650
651 case WM8580_CLKSRC_OSC:
652 reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
653 break;
654
655 default:
656 return -EINVAL;
657 }
658 snd_soc_write(codec, WM8580_PLLB4, reg);
659 break;
660
661 default:
662 return -EINVAL;
663 }
664
665 return 0;
666 }
667
668 static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
669 unsigned int freq, int dir)
670 {
671 struct snd_soc_codec *codec = dai->codec;
672 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
673 int ret, sel, sel_mask, sel_shift;
674
675 switch (dai->driver->id) {
676 case WM8580_DAI_PAIFRX:
677 sel_mask = 0x3;
678 sel_shift = 0;
679 break;
680
681 case WM8580_DAI_PAIFTX:
682 sel_mask = 0xc;
683 sel_shift = 2;
684 break;
685
686 default:
687 BUG_ON("Unknown DAI driver ID\n");
688 return -EINVAL;
689 }
690
691 switch (clk_id) {
692 case WM8580_CLKSRC_ADCMCLK:
693 if (dai->driver->id != WM8580_DAI_PAIFTX)
694 return -EINVAL;
695 sel = 0 << sel_shift;
696 break;
697 case WM8580_CLKSRC_PLLA:
698 sel = 1 << sel_shift;
699 break;
700 case WM8580_CLKSRC_PLLB:
701 sel = 2 << sel_shift;
702 break;
703 case WM8580_CLKSRC_MCLK:
704 sel = 3 << sel_shift;
705 break;
706 default:
707 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
708 return -EINVAL;
709 }
710
711 /* We really should validate PLL settings but not yet */
712 wm8580->sysclk[dai->driver->id] = freq;
713
714 ret = snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel);
715 if (ret < 0)
716 return ret;
717
718 return 0;
719 }
720
721 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
722 {
723 struct snd_soc_codec *codec = codec_dai->codec;
724 unsigned int reg;
725
726 reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
727
728 if (mute)
729 reg |= WM8580_DAC_CONTROL5_MUTEALL;
730 else
731 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
732
733 snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
734
735 return 0;
736 }
737
738 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
739 enum snd_soc_bias_level level)
740 {
741 switch (level) {
742 case SND_SOC_BIAS_ON:
743 case SND_SOC_BIAS_PREPARE:
744 break;
745
746 case SND_SOC_BIAS_STANDBY:
747 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
748 /* Power up and get individual control of the DACs */
749 snd_soc_update_bits(codec, WM8580_PWRDN1,
750 WM8580_PWRDN1_PWDN |
751 WM8580_PWRDN1_ALLDACPD, 0);
752
753 /* Make VMID high impedance */
754 snd_soc_update_bits(codec, WM8580_ADC_CONTROL1,
755 0x100, 0);
756 }
757 break;
758
759 case SND_SOC_BIAS_OFF:
760 snd_soc_update_bits(codec, WM8580_PWRDN1,
761 WM8580_PWRDN1_PWDN, WM8580_PWRDN1_PWDN);
762 break;
763 }
764 codec->dapm.bias_level = level;
765 return 0;
766 }
767
768 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
769 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
770
771 static const struct snd_soc_dai_ops wm8580_dai_ops_playback = {
772 .set_sysclk = wm8580_set_sysclk,
773 .hw_params = wm8580_paif_hw_params,
774 .set_fmt = wm8580_set_paif_dai_fmt,
775 .set_clkdiv = wm8580_set_dai_clkdiv,
776 .set_pll = wm8580_set_dai_pll,
777 .digital_mute = wm8580_digital_mute,
778 };
779
780 static const struct snd_soc_dai_ops wm8580_dai_ops_capture = {
781 .set_sysclk = wm8580_set_sysclk,
782 .hw_params = wm8580_paif_hw_params,
783 .set_fmt = wm8580_set_paif_dai_fmt,
784 .set_clkdiv = wm8580_set_dai_clkdiv,
785 .set_pll = wm8580_set_dai_pll,
786 };
787
788 static struct snd_soc_dai_driver wm8580_dai[] = {
789 {
790 .name = "wm8580-hifi-playback",
791 .id = WM8580_DAI_PAIFRX,
792 .playback = {
793 .stream_name = "Playback",
794 .channels_min = 1,
795 .channels_max = 6,
796 .rates = SNDRV_PCM_RATE_8000_192000,
797 .formats = WM8580_FORMATS,
798 },
799 .ops = &wm8580_dai_ops_playback,
800 },
801 {
802 .name = "wm8580-hifi-capture",
803 .id = WM8580_DAI_PAIFTX,
804 .capture = {
805 .stream_name = "Capture",
806 .channels_min = 2,
807 .channels_max = 2,
808 .rates = SNDRV_PCM_RATE_8000_192000,
809 .formats = WM8580_FORMATS,
810 },
811 .ops = &wm8580_dai_ops_capture,
812 },
813 };
814
815 static int wm8580_probe(struct snd_soc_codec *codec)
816 {
817 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
818 int ret = 0,i;
819
820 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8580->control_type);
821 if (ret < 0) {
822 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
823 return ret;
824 }
825
826 for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
827 wm8580->supplies[i].supply = wm8580_supply_names[i];
828
829 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies),
830 wm8580->supplies);
831 if (ret != 0) {
832 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
833 return ret;
834 }
835
836 ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
837 wm8580->supplies);
838 if (ret != 0) {
839 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
840 goto err_regulator_get;
841 }
842
843 /* Get the codec into a known state */
844 ret = snd_soc_write(codec, WM8580_RESET, 0);
845 if (ret != 0) {
846 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
847 goto err_regulator_enable;
848 }
849
850 wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
851
852 return 0;
853
854 err_regulator_enable:
855 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
856 err_regulator_get:
857 regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
858 return ret;
859 }
860
861 /* power down chip */
862 static int wm8580_remove(struct snd_soc_codec *codec)
863 {
864 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
865
866 wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
867
868 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
869 regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
870
871 return 0;
872 }
873
874 static struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
875 .probe = wm8580_probe,
876 .remove = wm8580_remove,
877 .set_bias_level = wm8580_set_bias_level,
878 .reg_cache_size = ARRAY_SIZE(wm8580_reg),
879 .reg_word_size = sizeof(u16),
880 .reg_cache_default = wm8580_reg,
881
882 .controls = wm8580_snd_controls,
883 .num_controls = ARRAY_SIZE(wm8580_snd_controls),
884 .dapm_widgets = wm8580_dapm_widgets,
885 .num_dapm_widgets = ARRAY_SIZE(wm8580_dapm_widgets),
886 .dapm_routes = wm8580_dapm_routes,
887 .num_dapm_routes = ARRAY_SIZE(wm8580_dapm_routes),
888 };
889
890 static const struct of_device_id wm8580_of_match[] = {
891 { .compatible = "wlf,wm8580" },
892 { },
893 };
894
895 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
896 static int wm8580_i2c_probe(struct i2c_client *i2c,
897 const struct i2c_device_id *id)
898 {
899 struct wm8580_priv *wm8580;
900 int ret;
901
902 wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
903 if (wm8580 == NULL)
904 return -ENOMEM;
905
906 i2c_set_clientdata(i2c, wm8580);
907 wm8580->control_type = SND_SOC_I2C;
908
909 ret = snd_soc_register_codec(&i2c->dev,
910 &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
911 if (ret < 0)
912 kfree(wm8580);
913 return ret;
914 }
915
916 static int wm8580_i2c_remove(struct i2c_client *client)
917 {
918 snd_soc_unregister_codec(&client->dev);
919 kfree(i2c_get_clientdata(client));
920 return 0;
921 }
922
923 static const struct i2c_device_id wm8580_i2c_id[] = {
924 { "wm8580", 0 },
925 { }
926 };
927 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
928
929 static struct i2c_driver wm8580_i2c_driver = {
930 .driver = {
931 .name = "wm8580",
932 .owner = THIS_MODULE,
933 .of_match_table = wm8580_of_match,
934 },
935 .probe = wm8580_i2c_probe,
936 .remove = wm8580_i2c_remove,
937 .id_table = wm8580_i2c_id,
938 };
939 #endif
940
941 static int __init wm8580_modinit(void)
942 {
943 int ret = 0;
944
945 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
946 ret = i2c_add_driver(&wm8580_i2c_driver);
947 if (ret != 0) {
948 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
949 }
950 #endif
951
952 return ret;
953 }
954 module_init(wm8580_modinit);
955
956 static void __exit wm8580_exit(void)
957 {
958 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
959 i2c_del_driver(&wm8580_i2c_driver);
960 #endif
961 }
962 module_exit(wm8580_exit);
963
964 MODULE_DESCRIPTION("ASoC WM8580 driver");
965 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
966 MODULE_LICENSE("GPL");
Linux with added FPC-III support