2 * wm8903.c -- WM8903 ALSA SoC Audio driver
4 * Copyright 2008-12 Wolfson Microelectronics
5 * Copyright 2011-2012 NVIDIA, Inc.
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * - TDM mode configuration.
15 * - Digital microphone support.
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/gpio.h>
25 #include <linux/i2c.h>
26 #include <linux/regmap.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <sound/core.h>
30 #include <sound/jack.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/tlv.h>
34 #include <sound/soc.h>
35 #include <sound/initval.h>
36 #include <sound/wm8903.h>
37 #include <trace/events/asoc.h>
41 /* Register defaults at reset */
42 static const struct reg_default wm8903_reg_defaults
[] = {
43 { 4, 0x0018 }, /* R4 - Bias Control 0 */
44 { 5, 0x0000 }, /* R5 - VMID Control 0 */
45 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
46 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
47 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
48 { 12, 0x0000 }, /* R12 - Power Management 0 */
49 { 13, 0x0000 }, /* R13 - Power Management 1 */
50 { 14, 0x0000 }, /* R14 - Power Management 2 */
51 { 15, 0x0000 }, /* R15 - Power Management 3 */
52 { 16, 0x0000 }, /* R16 - Power Management 4 */
53 { 17, 0x0000 }, /* R17 - Power Management 5 */
54 { 18, 0x0000 }, /* R18 - Power Management 6 */
55 { 20, 0x0400 }, /* R20 - Clock Rates 0 */
56 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */
57 { 22, 0x0000 }, /* R22 - Clock Rates 2 */
58 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
59 { 25, 0x0242 }, /* R25 - Audio Interface 1 */
60 { 26, 0x0008 }, /* R26 - Audio Interface 2 */
61 { 27, 0x0022 }, /* R27 - Audio Interface 3 */
62 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
63 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
64 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
65 { 33, 0x0000 }, /* R33 - DAC Digital 1 */
66 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
67 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
68 { 38, 0x0000 }, /* R38 - ADC Digital 0 */
69 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */
70 { 40, 0x09BF }, /* R40 - DRC 0 */
71 { 41, 0x3241 }, /* R41 - DRC 1 */
72 { 42, 0x0020 }, /* R42 - DRC 2 */
73 { 43, 0x0000 }, /* R43 - DRC 3 */
74 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
75 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
76 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
77 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
78 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */
79 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */
80 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */
81 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */
82 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */
83 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */
84 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
85 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
86 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
87 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
88 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */
89 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */
90 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */
91 { 67, 0x0010 }, /* R67 - DC Servo 0 */
92 { 69, 0x00A4 }, /* R69 - DC Servo 2 */
93 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
94 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
95 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
96 { 104, 0x0000 }, /* R104 - Class W 0 */
97 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
98 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
99 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
100 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
101 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
102 { 114, 0x0000 }, /* R114 - Control Interface */
103 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */
104 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */
105 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */
106 { 119, 0x0220 }, /* R119 - GPIO Control 4 */
107 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */
108 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */
109 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */
110 { 126, 0x0000 }, /* R126 - Interrupt Control */
111 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */
112 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */
113 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */
114 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */
118 struct wm8903_platform_data
*pdata
;
120 struct snd_soc_codec
*codec
;
121 struct regmap
*regmap
;
132 /* Reference count */
135 struct snd_soc_jack
*mic_jack
;
141 #ifdef CONFIG_GPIOLIB
142 struct gpio_chip gpio_chip
;
146 static bool wm8903_readable_register(struct device
*dev
, unsigned int reg
)
149 case WM8903_SW_RESET_AND_ID
:
150 case WM8903_REVISION_NUMBER
:
151 case WM8903_BIAS_CONTROL_0
:
152 case WM8903_VMID_CONTROL_0
:
153 case WM8903_MIC_BIAS_CONTROL_0
:
154 case WM8903_ANALOGUE_DAC_0
:
155 case WM8903_ANALOGUE_ADC_0
:
156 case WM8903_POWER_MANAGEMENT_0
:
157 case WM8903_POWER_MANAGEMENT_1
:
158 case WM8903_POWER_MANAGEMENT_2
:
159 case WM8903_POWER_MANAGEMENT_3
:
160 case WM8903_POWER_MANAGEMENT_4
:
161 case WM8903_POWER_MANAGEMENT_5
:
162 case WM8903_POWER_MANAGEMENT_6
:
163 case WM8903_CLOCK_RATES_0
:
164 case WM8903_CLOCK_RATES_1
:
165 case WM8903_CLOCK_RATES_2
:
166 case WM8903_AUDIO_INTERFACE_0
:
167 case WM8903_AUDIO_INTERFACE_1
:
168 case WM8903_AUDIO_INTERFACE_2
:
169 case WM8903_AUDIO_INTERFACE_3
:
170 case WM8903_DAC_DIGITAL_VOLUME_LEFT
:
171 case WM8903_DAC_DIGITAL_VOLUME_RIGHT
:
172 case WM8903_DAC_DIGITAL_0
:
173 case WM8903_DAC_DIGITAL_1
:
174 case WM8903_ADC_DIGITAL_VOLUME_LEFT
:
175 case WM8903_ADC_DIGITAL_VOLUME_RIGHT
:
176 case WM8903_ADC_DIGITAL_0
:
177 case WM8903_DIGITAL_MICROPHONE_0
:
182 case WM8903_ANALOGUE_LEFT_INPUT_0
:
183 case WM8903_ANALOGUE_RIGHT_INPUT_0
:
184 case WM8903_ANALOGUE_LEFT_INPUT_1
:
185 case WM8903_ANALOGUE_RIGHT_INPUT_1
:
186 case WM8903_ANALOGUE_LEFT_MIX_0
:
187 case WM8903_ANALOGUE_RIGHT_MIX_0
:
188 case WM8903_ANALOGUE_SPK_MIX_LEFT_0
:
189 case WM8903_ANALOGUE_SPK_MIX_LEFT_1
:
190 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0
:
191 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1
:
192 case WM8903_ANALOGUE_OUT1_LEFT
:
193 case WM8903_ANALOGUE_OUT1_RIGHT
:
194 case WM8903_ANALOGUE_OUT2_LEFT
:
195 case WM8903_ANALOGUE_OUT2_RIGHT
:
196 case WM8903_ANALOGUE_OUT3_LEFT
:
197 case WM8903_ANALOGUE_OUT3_RIGHT
:
198 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0
:
199 case WM8903_DC_SERVO_0
:
200 case WM8903_DC_SERVO_2
:
201 case WM8903_DC_SERVO_READBACK_1
:
202 case WM8903_DC_SERVO_READBACK_2
:
203 case WM8903_DC_SERVO_READBACK_3
:
204 case WM8903_DC_SERVO_READBACK_4
:
205 case WM8903_ANALOGUE_HP_0
:
206 case WM8903_ANALOGUE_LINEOUT_0
:
207 case WM8903_CHARGE_PUMP_0
:
208 case WM8903_CLASS_W_0
:
209 case WM8903_WRITE_SEQUENCER_0
:
210 case WM8903_WRITE_SEQUENCER_1
:
211 case WM8903_WRITE_SEQUENCER_2
:
212 case WM8903_WRITE_SEQUENCER_3
:
213 case WM8903_WRITE_SEQUENCER_4
:
214 case WM8903_CONTROL_INTERFACE
:
215 case WM8903_GPIO_CONTROL_1
:
216 case WM8903_GPIO_CONTROL_2
:
217 case WM8903_GPIO_CONTROL_3
:
218 case WM8903_GPIO_CONTROL_4
:
219 case WM8903_GPIO_CONTROL_5
:
220 case WM8903_INTERRUPT_STATUS_1
:
221 case WM8903_INTERRUPT_STATUS_1_MASK
:
222 case WM8903_INTERRUPT_POLARITY_1
:
223 case WM8903_INTERRUPT_CONTROL
:
224 case WM8903_CLOCK_RATE_TEST_4
:
225 case WM8903_ANALOGUE_OUTPUT_BIAS_0
:
232 static bool wm8903_volatile_register(struct device
*dev
, unsigned int reg
)
235 case WM8903_SW_RESET_AND_ID
:
236 case WM8903_REVISION_NUMBER
:
237 case WM8903_INTERRUPT_STATUS_1
:
238 case WM8903_WRITE_SEQUENCER_4
:
239 case WM8903_DC_SERVO_READBACK_1
:
240 case WM8903_DC_SERVO_READBACK_2
:
241 case WM8903_DC_SERVO_READBACK_3
:
242 case WM8903_DC_SERVO_READBACK_4
:
250 static int wm8903_cp_event(struct snd_soc_dapm_widget
*w
,
251 struct snd_kcontrol
*kcontrol
, int event
)
253 WARN_ON(event
!= SND_SOC_DAPM_POST_PMU
);
259 static int wm8903_dcs_event(struct snd_soc_dapm_widget
*w
,
260 struct snd_kcontrol
*kcontrol
, int event
)
262 struct snd_soc_codec
*codec
= w
->codec
;
263 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
266 case SND_SOC_DAPM_POST_PMU
:
267 wm8903
->dcs_pending
|= 1 << w
->shift
;
269 case SND_SOC_DAPM_PRE_PMD
:
270 snd_soc_update_bits(codec
, WM8903_DC_SERVO_0
,
278 #define WM8903_DCS_MODE_WRITE_STOP 0
279 #define WM8903_DCS_MODE_START_STOP 2
281 static void wm8903_seq_notifier(struct snd_soc_dapm_context
*dapm
,
282 enum snd_soc_dapm_type event
, int subseq
)
284 struct snd_soc_codec
*codec
= container_of(dapm
,
285 struct snd_soc_codec
, dapm
);
286 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
287 int dcs_mode
= WM8903_DCS_MODE_WRITE_STOP
;
290 /* Complete any pending DC servo starts */
291 if (wm8903
->dcs_pending
) {
292 dev_dbg(codec
->dev
, "Starting DC servo for %x\n",
293 wm8903
->dcs_pending
);
295 /* If we've no cached values then we need to do startup */
296 for (i
= 0; i
< ARRAY_SIZE(wm8903
->dcs_cache
); i
++) {
297 if (!(wm8903
->dcs_pending
& (1 << i
)))
300 if (wm8903
->dcs_cache
[i
]) {
302 "Restore DC servo %d value %x\n",
303 3 - i
, wm8903
->dcs_cache
[i
]);
305 snd_soc_write(codec
, WM8903_DC_SERVO_4
+ i
,
306 wm8903
->dcs_cache
[i
] & 0xff);
309 "Calibrate DC servo %d\n", 3 - i
);
310 dcs_mode
= WM8903_DCS_MODE_START_STOP
;
314 /* Don't trust the cache for analogue */
315 if (wm8903
->class_w_users
)
316 dcs_mode
= WM8903_DCS_MODE_START_STOP
;
318 snd_soc_update_bits(codec
, WM8903_DC_SERVO_2
,
319 WM8903_DCS_MODE_MASK
, dcs_mode
);
321 snd_soc_update_bits(codec
, WM8903_DC_SERVO_0
,
322 WM8903_DCS_ENA_MASK
, wm8903
->dcs_pending
);
325 case WM8903_DCS_MODE_WRITE_STOP
:
328 case WM8903_DCS_MODE_START_STOP
:
331 /* Cache the measured offsets for digital */
332 if (wm8903
->class_w_users
)
335 for (i
= 0; i
< ARRAY_SIZE(wm8903
->dcs_cache
); i
++) {
336 if (!(wm8903
->dcs_pending
& (1 << i
)))
339 val
= snd_soc_read(codec
,
340 WM8903_DC_SERVO_READBACK_1
+ i
);
341 dev_dbg(codec
->dev
, "DC servo %d: %x\n",
343 wm8903
->dcs_cache
[i
] = val
;
348 pr_warn("DCS mode %d delay not set\n", dcs_mode
);
352 wm8903
->dcs_pending
= 0;
357 * When used with DAC outputs only the WM8903 charge pump supports
358 * operation in class W mode, providing very low power consumption
359 * when used with digital sources. Enable and disable this mode
360 * automatically depending on the mixer configuration.
362 * All the relevant controls are simple switches.
364 static int wm8903_class_w_put(struct snd_kcontrol
*kcontrol
,
365 struct snd_ctl_elem_value
*ucontrol
)
367 struct snd_soc_dapm_widget_list
*wlist
= snd_kcontrol_chip(kcontrol
);
368 struct snd_soc_dapm_widget
*widget
= wlist
->widgets
[0];
369 struct snd_soc_codec
*codec
= widget
->codec
;
370 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
374 reg
= snd_soc_read(codec
, WM8903_CLASS_W_0
);
376 /* Turn it off if we're about to enable bypass */
377 if (ucontrol
->value
.integer
.value
[0]) {
378 if (wm8903
->class_w_users
== 0) {
379 dev_dbg(codec
->dev
, "Disabling Class W\n");
380 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
&
381 ~(WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
));
383 wm8903
->class_w_users
++;
386 /* Implement the change */
387 ret
= snd_soc_dapm_put_volsw(kcontrol
, ucontrol
);
389 /* If we've just disabled the last bypass path turn Class W on */
390 if (!ucontrol
->value
.integer
.value
[0]) {
391 if (wm8903
->class_w_users
== 1) {
392 dev_dbg(codec
->dev
, "Enabling Class W\n");
393 snd_soc_write(codec
, WM8903_CLASS_W_0
, reg
|
394 WM8903_CP_DYN_FREQ
| WM8903_CP_DYN_V
);
396 wm8903
->class_w_users
--;
399 dev_dbg(codec
->dev
, "Bypass use count now %d\n",
400 wm8903
->class_w_users
);
405 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
406 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
407 .info = snd_soc_info_volsw, \
408 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
409 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
412 static int wm8903_deemph
[] = { 0, 32000, 44100, 48000 };
414 static int wm8903_set_deemph(struct snd_soc_codec
*codec
)
416 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
419 /* If we're using deemphasis select the nearest available sample
422 if (wm8903
->deemph
) {
424 for (i
= 2; i
< ARRAY_SIZE(wm8903_deemph
); i
++) {
425 if (abs(wm8903_deemph
[i
] - wm8903
->fs
) <
426 abs(wm8903_deemph
[best
] - wm8903
->fs
))
430 val
= best
<< WM8903_DEEMPH_SHIFT
;
436 dev_dbg(codec
->dev
, "Set deemphasis %d (%dHz)\n",
437 best
, wm8903_deemph
[best
]);
439 return snd_soc_update_bits(codec
, WM8903_DAC_DIGITAL_1
,
440 WM8903_DEEMPH_MASK
, val
);
443 static int wm8903_get_deemph(struct snd_kcontrol
*kcontrol
,
444 struct snd_ctl_elem_value
*ucontrol
)
446 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
447 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
449 ucontrol
->value
.enumerated
.item
[0] = wm8903
->deemph
;
454 static int wm8903_put_deemph(struct snd_kcontrol
*kcontrol
,
455 struct snd_ctl_elem_value
*ucontrol
)
457 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
458 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
459 int deemph
= ucontrol
->value
.enumerated
.item
[0];
465 mutex_lock(&codec
->mutex
);
466 if (wm8903
->deemph
!= deemph
) {
467 wm8903
->deemph
= deemph
;
469 wm8903_set_deemph(codec
);
473 mutex_unlock(&codec
->mutex
);
478 /* ALSA can only do steps of .01dB */
479 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -7200, 75, 1);
481 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv
, -3600, 300, 0);
482 static const DECLARE_TLV_DB_SCALE(out_tlv
, -5700, 100, 0);
484 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh
, 0, 75, 0);
485 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp
, -2250, 75, 0);
486 static const DECLARE_TLV_DB_SCALE(drc_tlv_min
, 0, 600, 0);
487 static const DECLARE_TLV_DB_SCALE(drc_tlv_max
, 1200, 600, 0);
488 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup
, -300, 50, 0);
490 static const char *hpf_mode_text
[] = {
491 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
494 static const struct soc_enum hpf_mode
=
495 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0
, 5, 4, hpf_mode_text
);
497 static const char *osr_text
[] = {
498 "Low power", "High performance"
501 static const struct soc_enum adc_osr
=
502 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0
, 0, 2, osr_text
);
504 static const struct soc_enum dac_osr
=
505 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 0, 2, osr_text
);
507 static const char *drc_slope_text
[] = {
508 "1", "1/2", "1/4", "1/8", "1/16", "0"
511 static const struct soc_enum drc_slope_r0
=
512 SOC_ENUM_SINGLE(WM8903_DRC_2
, 3, 6, drc_slope_text
);
514 static const struct soc_enum drc_slope_r1
=
515 SOC_ENUM_SINGLE(WM8903_DRC_2
, 0, 6, drc_slope_text
);
517 static const char *drc_attack_text
[] = {
519 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
520 "46.4ms", "92.8ms", "185.6ms"
523 static const struct soc_enum drc_attack
=
524 SOC_ENUM_SINGLE(WM8903_DRC_1
, 12, 11, drc_attack_text
);
526 static const char *drc_decay_text
[] = {
527 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
531 static const struct soc_enum drc_decay
=
532 SOC_ENUM_SINGLE(WM8903_DRC_1
, 8, 9, drc_decay_text
);
534 static const char *drc_ff_delay_text
[] = {
535 "5 samples", "9 samples"
538 static const struct soc_enum drc_ff_delay
=
539 SOC_ENUM_SINGLE(WM8903_DRC_0
, 5, 2, drc_ff_delay_text
);
541 static const char *drc_qr_decay_text
[] = {
542 "0.725ms", "1.45ms", "5.8ms"
545 static const struct soc_enum drc_qr_decay
=
546 SOC_ENUM_SINGLE(WM8903_DRC_1
, 4, 3, drc_qr_decay_text
);
548 static const char *drc_smoothing_text
[] = {
549 "Low", "Medium", "High"
552 static const struct soc_enum drc_smoothing
=
553 SOC_ENUM_SINGLE(WM8903_DRC_0
, 11, 3, drc_smoothing_text
);
555 static const char *soft_mute_text
[] = {
556 "Fast (fs/2)", "Slow (fs/32)"
559 static const struct soc_enum soft_mute
=
560 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 10, 2, soft_mute_text
);
562 static const char *mute_mode_text
[] = {
566 static const struct soc_enum mute_mode
=
567 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1
, 9, 2, mute_mode_text
);
569 static const char *companding_text
[] = {
573 static const struct soc_enum dac_companding
=
574 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 0, 2, companding_text
);
576 static const struct soc_enum adc_companding
=
577 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 2, 2, companding_text
);
579 static const char *input_mode_text
[] = {
580 "Single-Ended", "Differential Line", "Differential Mic"
583 static const struct soc_enum linput_mode_enum
=
584 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 0, 3, input_mode_text
);
586 static const struct soc_enum rinput_mode_enum
=
587 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 0, 3, input_mode_text
);
589 static const char *linput_mux_text
[] = {
590 "IN1L", "IN2L", "IN3L"
593 static const struct soc_enum linput_enum
=
594 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 2, 3, linput_mux_text
);
596 static const struct soc_enum linput_inv_enum
=
597 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1
, 4, 3, linput_mux_text
);
599 static const char *rinput_mux_text
[] = {
600 "IN1R", "IN2R", "IN3R"
603 static const struct soc_enum rinput_enum
=
604 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 2, 3, rinput_mux_text
);
606 static const struct soc_enum rinput_inv_enum
=
607 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1
, 4, 3, rinput_mux_text
);
610 static const char *sidetone_text
[] = {
611 "None", "Left", "Right"
614 static const struct soc_enum lsidetone_enum
=
615 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 2, 3, sidetone_text
);
617 static const struct soc_enum rsidetone_enum
=
618 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0
, 0, 3, sidetone_text
);
620 static const char *adcinput_text
[] = {
624 static const struct soc_enum adcinput_enum
=
625 SOC_ENUM_SINGLE(WM8903_CLOCK_RATE_TEST_4
, 9, 2, adcinput_text
);
627 static const char *aif_text
[] = {
631 static const struct soc_enum lcapture_enum
=
632 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 7, 2, aif_text
);
634 static const struct soc_enum rcapture_enum
=
635 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 6, 2, aif_text
);
637 static const struct soc_enum lplay_enum
=
638 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 5, 2, aif_text
);
640 static const struct soc_enum rplay_enum
=
641 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0
, 4, 2, aif_text
);
643 static const struct snd_kcontrol_new wm8903_snd_controls
[] = {
645 /* Input PGAs - No TLV since the scale depends on PGA mode */
646 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0
,
648 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0
,
650 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1
,
653 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0
,
655 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0
,
657 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1
,
661 SOC_ENUM("ADC OSR", adc_osr
),
662 SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0
, 4, 1, 0),
663 SOC_ENUM("HPF Mode", hpf_mode
),
664 SOC_SINGLE("DRC Switch", WM8903_DRC_0
, 15, 1, 0),
665 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0
),
666 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1
),
667 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3
, 5, 124, 1,
669 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3
, 0, 30, 1, drc_tlv_amp
),
670 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1
, 2, 3, 1, drc_tlv_min
),
671 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1
, 0, 3, 0, drc_tlv_max
),
672 SOC_ENUM("DRC Attack Rate", drc_attack
),
673 SOC_ENUM("DRC Decay Rate", drc_decay
),
674 SOC_ENUM("DRC FF Delay", drc_ff_delay
),
675 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0
, 1, 1, 0),
676 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0
, 2, 1, 0),
677 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0
, 6, 3, 0, drc_tlv_max
),
678 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay
),
679 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0
, 3, 1, 0),
680 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0
, 0, 1, 0),
681 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing
),
682 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0
, 6, 18, 0, drc_tlv_startup
),
684 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT
,
685 WM8903_ADC_DIGITAL_VOLUME_RIGHT
, 1, 120, 0, digital_tlv
),
686 SOC_ENUM("ADC Companding Mode", adc_companding
),
687 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 3, 1, 0),
689 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0
, 4, 8,
690 12, 0, digital_sidetone_tlv
),
693 SOC_ENUM("DAC OSR", dac_osr
),
694 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT
,
695 WM8903_DAC_DIGITAL_VOLUME_RIGHT
, 1, 120, 0, digital_tlv
),
696 SOC_ENUM("DAC Soft Mute Rate", soft_mute
),
697 SOC_ENUM("DAC Mute Mode", mute_mode
),
698 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1
, 12, 1, 0),
699 SOC_ENUM("DAC Companding Mode", dac_companding
),
700 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0
, 1, 1, 0),
701 SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
702 wm8903_get_deemph
, wm8903_put_deemph
),
705 SOC_DOUBLE_R("Headphone Switch",
706 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
708 SOC_DOUBLE_R("Headphone ZC Switch",
709 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
711 SOC_DOUBLE_R_TLV("Headphone Volume",
712 WM8903_ANALOGUE_OUT1_LEFT
, WM8903_ANALOGUE_OUT1_RIGHT
,
716 SOC_DOUBLE_R("Line Out Switch",
717 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
719 SOC_DOUBLE_R("Line Out ZC Switch",
720 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
722 SOC_DOUBLE_R_TLV("Line Out Volume",
723 WM8903_ANALOGUE_OUT2_LEFT
, WM8903_ANALOGUE_OUT2_RIGHT
,
727 SOC_DOUBLE_R("Speaker Switch",
728 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 8, 1, 1),
729 SOC_DOUBLE_R("Speaker ZC Switch",
730 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
, 6, 1, 0),
731 SOC_DOUBLE_R_TLV("Speaker Volume",
732 WM8903_ANALOGUE_OUT3_LEFT
, WM8903_ANALOGUE_OUT3_RIGHT
,
736 static const struct snd_kcontrol_new linput_mode_mux
=
737 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum
);
739 static const struct snd_kcontrol_new rinput_mode_mux
=
740 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum
);
742 static const struct snd_kcontrol_new linput_mux
=
743 SOC_DAPM_ENUM("Left Input Mux", linput_enum
);
745 static const struct snd_kcontrol_new linput_inv_mux
=
746 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum
);
748 static const struct snd_kcontrol_new rinput_mux
=
749 SOC_DAPM_ENUM("Right Input Mux", rinput_enum
);
751 static const struct snd_kcontrol_new rinput_inv_mux
=
752 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum
);
754 static const struct snd_kcontrol_new lsidetone_mux
=
755 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum
);
757 static const struct snd_kcontrol_new rsidetone_mux
=
758 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum
);
760 static const struct snd_kcontrol_new adcinput_mux
=
761 SOC_DAPM_ENUM("ADC Input", adcinput_enum
);
763 static const struct snd_kcontrol_new lcapture_mux
=
764 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum
);
766 static const struct snd_kcontrol_new rcapture_mux
=
767 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum
);
769 static const struct snd_kcontrol_new lplay_mux
=
770 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum
);
772 static const struct snd_kcontrol_new rplay_mux
=
773 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum
);
775 static const struct snd_kcontrol_new left_output_mixer
[] = {
776 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 3, 1, 0),
777 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 2, 1, 0),
778 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 1, 1, 0),
779 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0
, 0, 1, 0),
782 static const struct snd_kcontrol_new right_output_mixer
[] = {
783 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 3, 1, 0),
784 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 2, 1, 0),
785 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 1, 1, 0),
786 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0
, 0, 1, 0),
789 static const struct snd_kcontrol_new left_speaker_mixer
[] = {
790 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 3, 1, 0),
791 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 2, 1, 0),
792 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
, 1, 1, 0),
793 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0
,
797 static const struct snd_kcontrol_new right_speaker_mixer
[] = {
798 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 3, 1, 0),
799 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
, 2, 1, 0),
800 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
802 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0
,
806 static const struct snd_soc_dapm_widget wm8903_dapm_widgets
[] = {
807 SND_SOC_DAPM_INPUT("IN1L"),
808 SND_SOC_DAPM_INPUT("IN1R"),
809 SND_SOC_DAPM_INPUT("IN2L"),
810 SND_SOC_DAPM_INPUT("IN2R"),
811 SND_SOC_DAPM_INPUT("IN3L"),
812 SND_SOC_DAPM_INPUT("IN3R"),
813 SND_SOC_DAPM_INPUT("DMICDAT"),
815 SND_SOC_DAPM_OUTPUT("HPOUTL"),
816 SND_SOC_DAPM_OUTPUT("HPOUTR"),
817 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
818 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
819 SND_SOC_DAPM_OUTPUT("LOP"),
820 SND_SOC_DAPM_OUTPUT("LON"),
821 SND_SOC_DAPM_OUTPUT("ROP"),
822 SND_SOC_DAPM_OUTPUT("RON"),
824 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0
, 0, 0, NULL
, 0),
826 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM
, 0, 0, &linput_mux
),
827 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
829 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM
, 0, 0, &linput_mode_mux
),
831 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM
, 0, 0, &rinput_mux
),
832 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM
, 0, 0,
834 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM
, 0, 0, &rinput_mode_mux
),
836 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0
, 1, 0, NULL
, 0),
837 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0
, 0, 0, NULL
, 0),
839 SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM
, 0, 0, &adcinput_mux
),
840 SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM
, 0, 0, &adcinput_mux
),
842 SND_SOC_DAPM_ADC("ADCL", NULL
, WM8903_POWER_MANAGEMENT_6
, 1, 0),
843 SND_SOC_DAPM_ADC("ADCR", NULL
, WM8903_POWER_MANAGEMENT_6
, 0, 0),
845 SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM
, 0, 0, &lcapture_mux
),
846 SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM
, 0, 0, &rcapture_mux
),
848 SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM
, 0, 0),
849 SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM
, 0, 0),
851 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM
, 0, 0, &lsidetone_mux
),
852 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM
, 0, 0, &rsidetone_mux
),
854 SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM
, 0, 0),
855 SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM
, 0, 0),
857 SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM
, 0, 0, &lplay_mux
),
858 SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM
, 0, 0, &rplay_mux
),
860 SND_SOC_DAPM_DAC("DACL", NULL
, WM8903_POWER_MANAGEMENT_6
, 3, 0),
861 SND_SOC_DAPM_DAC("DACR", NULL
, WM8903_POWER_MANAGEMENT_6
, 2, 0),
863 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1
, 1, 0,
864 left_output_mixer
, ARRAY_SIZE(left_output_mixer
)),
865 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1
, 0, 0,
866 right_output_mixer
, ARRAY_SIZE(right_output_mixer
)),
868 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 1, 0,
869 left_speaker_mixer
, ARRAY_SIZE(left_speaker_mixer
)),
870 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4
, 0, 0,
871 right_speaker_mixer
, ARRAY_SIZE(right_speaker_mixer
)),
873 SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2
,
875 SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2
,
878 SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3
, 1, 0,
880 SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3
, 0, 0,
883 SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0
, 7, 0, NULL
, 0),
884 SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0
, 6, 0, NULL
, 0),
885 SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0
, 5, 0, NULL
, 0),
886 SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0
, 4, 0, NULL
, 0),
887 SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0
, 3, 0, NULL
, 0),
888 SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0
, 2, 0, NULL
, 0),
889 SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0
, 1, 0, NULL
, 0),
890 SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0
, 0, 0, NULL
, 0),
892 SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0
, 7, 0,
894 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0
, 6, 0,
896 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0
, 5, 0,
898 SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0
, 4, 0,
900 SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0
, 3, 0,
902 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0
, 2, 0,
904 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0
, 1, 0,
906 SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0
, 0, 0,
909 SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0
, 4, 0, NULL
, 0),
910 SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM
, 3, 0, wm8903_dcs_event
,
911 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
912 SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM
, 2, 0, wm8903_dcs_event
,
913 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
914 SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM
, 1, 0, wm8903_dcs_event
,
915 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
916 SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM
, 0, 0, wm8903_dcs_event
,
917 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_PRE_PMD
),
919 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 1, 0,
921 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5
, 0, 0,
924 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0
, 0, 0,
925 wm8903_cp_event
, SND_SOC_DAPM_POST_PMU
),
926 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2
, 1, 0, NULL
, 0),
927 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2
, 2, 0, NULL
, 0),
930 static const struct snd_soc_dapm_route wm8903_intercon
[] = {
932 { "CLK_DSP", NULL
, "CLK_SYS" },
933 { "MICBIAS", NULL
, "CLK_SYS" },
934 { "HPL_DCS", NULL
, "CLK_SYS" },
935 { "HPR_DCS", NULL
, "CLK_SYS" },
936 { "LINEOUTL_DCS", NULL
, "CLK_SYS" },
937 { "LINEOUTR_DCS", NULL
, "CLK_SYS" },
939 { "Left Input Mux", "IN1L", "IN1L" },
940 { "Left Input Mux", "IN2L", "IN2L" },
941 { "Left Input Mux", "IN3L", "IN3L" },
943 { "Left Input Inverting Mux", "IN1L", "IN1L" },
944 { "Left Input Inverting Mux", "IN2L", "IN2L" },
945 { "Left Input Inverting Mux", "IN3L", "IN3L" },
947 { "Right Input Mux", "IN1R", "IN1R" },
948 { "Right Input Mux", "IN2R", "IN2R" },
949 { "Right Input Mux", "IN3R", "IN3R" },
951 { "Right Input Inverting Mux", "IN1R", "IN1R" },
952 { "Right Input Inverting Mux", "IN2R", "IN2R" },
953 { "Right Input Inverting Mux", "IN3R", "IN3R" },
955 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
956 { "Left Input Mode Mux", "Differential Line",
958 { "Left Input Mode Mux", "Differential Line",
959 "Left Input Inverting Mux" },
960 { "Left Input Mode Mux", "Differential Mic",
962 { "Left Input Mode Mux", "Differential Mic",
963 "Left Input Inverting Mux" },
965 { "Right Input Mode Mux", "Single-Ended",
966 "Right Input Inverting Mux" },
967 { "Right Input Mode Mux", "Differential Line",
969 { "Right Input Mode Mux", "Differential Line",
970 "Right Input Inverting Mux" },
971 { "Right Input Mode Mux", "Differential Mic",
973 { "Right Input Mode Mux", "Differential Mic",
974 "Right Input Inverting Mux" },
976 { "Left Input PGA", NULL
, "Left Input Mode Mux" },
977 { "Right Input PGA", NULL
, "Right Input Mode Mux" },
979 { "Left ADC Input", "ADC", "Left Input PGA" },
980 { "Left ADC Input", "DMIC", "DMICDAT" },
981 { "Right ADC Input", "ADC", "Right Input PGA" },
982 { "Right ADC Input", "DMIC", "DMICDAT" },
984 { "Left Capture Mux", "Left", "ADCL" },
985 { "Left Capture Mux", "Right", "ADCR" },
987 { "Right Capture Mux", "Left", "ADCL" },
988 { "Right Capture Mux", "Right", "ADCR" },
990 { "AIFTXL", NULL
, "Left Capture Mux" },
991 { "AIFTXR", NULL
, "Right Capture Mux" },
993 { "ADCL", NULL
, "Left ADC Input" },
994 { "ADCL", NULL
, "CLK_DSP" },
995 { "ADCR", NULL
, "Right ADC Input" },
996 { "ADCR", NULL
, "CLK_DSP" },
998 { "Left Playback Mux", "Left", "AIFRXL" },
999 { "Left Playback Mux", "Right", "AIFRXR" },
1001 { "Right Playback Mux", "Left", "AIFRXL" },
1002 { "Right Playback Mux", "Right", "AIFRXR" },
1004 { "DACL Sidetone", "Left", "ADCL" },
1005 { "DACL Sidetone", "Right", "ADCR" },
1006 { "DACR Sidetone", "Left", "ADCL" },
1007 { "DACR Sidetone", "Right", "ADCR" },
1009 { "DACL", NULL
, "Left Playback Mux" },
1010 { "DACL", NULL
, "DACL Sidetone" },
1011 { "DACL", NULL
, "CLK_DSP" },
1013 { "DACR", NULL
, "Right Playback Mux" },
1014 { "DACR", NULL
, "DACR Sidetone" },
1015 { "DACR", NULL
, "CLK_DSP" },
1017 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1018 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1019 { "Left Output Mixer", "DACL Switch", "DACL" },
1020 { "Left Output Mixer", "DACR Switch", "DACR" },
1022 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1023 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1024 { "Right Output Mixer", "DACL Switch", "DACL" },
1025 { "Right Output Mixer", "DACR Switch", "DACR" },
1027 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1028 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1029 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1030 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1032 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1033 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1034 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1035 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1037 { "Left Line Output PGA", NULL
, "Left Output Mixer" },
1038 { "Right Line Output PGA", NULL
, "Right Output Mixer" },
1040 { "Left Headphone Output PGA", NULL
, "Left Output Mixer" },
1041 { "Right Headphone Output PGA", NULL
, "Right Output Mixer" },
1043 { "Left Speaker PGA", NULL
, "Left Speaker Mixer" },
1044 { "Right Speaker PGA", NULL
, "Right Speaker Mixer" },
1046 { "HPL_ENA", NULL
, "Left Headphone Output PGA" },
1047 { "HPR_ENA", NULL
, "Right Headphone Output PGA" },
1048 { "HPL_ENA_DLY", NULL
, "HPL_ENA" },
1049 { "HPR_ENA_DLY", NULL
, "HPR_ENA" },
1050 { "LINEOUTL_ENA", NULL
, "Left Line Output PGA" },
1051 { "LINEOUTR_ENA", NULL
, "Right Line Output PGA" },
1052 { "LINEOUTL_ENA_DLY", NULL
, "LINEOUTL_ENA" },
1053 { "LINEOUTR_ENA_DLY", NULL
, "LINEOUTR_ENA" },
1055 { "HPL_DCS", NULL
, "DCS Master" },
1056 { "HPR_DCS", NULL
, "DCS Master" },
1057 { "LINEOUTL_DCS", NULL
, "DCS Master" },
1058 { "LINEOUTR_DCS", NULL
, "DCS Master" },
1060 { "HPL_DCS", NULL
, "HPL_ENA_DLY" },
1061 { "HPR_DCS", NULL
, "HPR_ENA_DLY" },
1062 { "LINEOUTL_DCS", NULL
, "LINEOUTL_ENA_DLY" },
1063 { "LINEOUTR_DCS", NULL
, "LINEOUTR_ENA_DLY" },
1065 { "HPL_ENA_OUTP", NULL
, "HPL_DCS" },
1066 { "HPR_ENA_OUTP", NULL
, "HPR_DCS" },
1067 { "LINEOUTL_ENA_OUTP", NULL
, "LINEOUTL_DCS" },
1068 { "LINEOUTR_ENA_OUTP", NULL
, "LINEOUTR_DCS" },
1070 { "HPL_RMV_SHORT", NULL
, "HPL_ENA_OUTP" },
1071 { "HPR_RMV_SHORT", NULL
, "HPR_ENA_OUTP" },
1072 { "LINEOUTL_RMV_SHORT", NULL
, "LINEOUTL_ENA_OUTP" },
1073 { "LINEOUTR_RMV_SHORT", NULL
, "LINEOUTR_ENA_OUTP" },
1075 { "HPOUTL", NULL
, "HPL_RMV_SHORT" },
1076 { "HPOUTR", NULL
, "HPR_RMV_SHORT" },
1077 { "LINEOUTL", NULL
, "LINEOUTL_RMV_SHORT" },
1078 { "LINEOUTR", NULL
, "LINEOUTR_RMV_SHORT" },
1080 { "LOP", NULL
, "Left Speaker PGA" },
1081 { "LON", NULL
, "Left Speaker PGA" },
1083 { "ROP", NULL
, "Right Speaker PGA" },
1084 { "RON", NULL
, "Right Speaker PGA" },
1086 { "Left Headphone Output PGA", NULL
, "Charge Pump" },
1087 { "Right Headphone Output PGA", NULL
, "Charge Pump" },
1088 { "Left Line Output PGA", NULL
, "Charge Pump" },
1089 { "Right Line Output PGA", NULL
, "Charge Pump" },
1092 static int wm8903_set_bias_level(struct snd_soc_codec
*codec
,
1093 enum snd_soc_bias_level level
)
1096 case SND_SOC_BIAS_ON
:
1099 case SND_SOC_BIAS_PREPARE
:
1100 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1101 WM8903_VMID_RES_MASK
,
1102 WM8903_VMID_RES_50K
);
1105 case SND_SOC_BIAS_STANDBY
:
1106 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1107 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1108 WM8903_POBCTRL
| WM8903_ISEL_MASK
|
1109 WM8903_STARTUP_BIAS_ENA
|
1112 (2 << WM8903_ISEL_SHIFT
) |
1113 WM8903_STARTUP_BIAS_ENA
);
1115 snd_soc_update_bits(codec
,
1116 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0
,
1117 WM8903_SPK_DISCHARGE
,
1118 WM8903_SPK_DISCHARGE
);
1122 snd_soc_update_bits(codec
, WM8903_POWER_MANAGEMENT_5
,
1123 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
,
1124 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
);
1126 snd_soc_update_bits(codec
,
1127 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0
,
1128 WM8903_SPK_DISCHARGE
, 0);
1130 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1131 WM8903_VMID_TIE_ENA
|
1133 WM8903_VMID_IO_ENA
|
1134 WM8903_VMID_SOFT_MASK
|
1135 WM8903_VMID_RES_MASK
|
1136 WM8903_VMID_BUF_ENA
,
1137 WM8903_VMID_TIE_ENA
|
1139 WM8903_VMID_IO_ENA
|
1140 (2 << WM8903_VMID_SOFT_SHIFT
) |
1141 WM8903_VMID_RES_250K
|
1142 WM8903_VMID_BUF_ENA
);
1146 snd_soc_update_bits(codec
, WM8903_POWER_MANAGEMENT_5
,
1147 WM8903_SPKL_ENA
| WM8903_SPKR_ENA
,
1150 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1151 WM8903_VMID_SOFT_MASK
, 0);
1153 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1154 WM8903_VMID_RES_MASK
,
1155 WM8903_VMID_RES_50K
);
1157 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1158 WM8903_BIAS_ENA
| WM8903_POBCTRL
,
1161 /* By default no bypass paths are enabled so
1162 * enable Class W support.
1164 dev_dbg(codec
->dev
, "Enabling Class W\n");
1165 snd_soc_update_bits(codec
, WM8903_CLASS_W_0
,
1166 WM8903_CP_DYN_FREQ
|
1168 WM8903_CP_DYN_FREQ
|
1172 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1173 WM8903_VMID_RES_MASK
,
1174 WM8903_VMID_RES_250K
);
1177 case SND_SOC_BIAS_OFF
:
1178 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1179 WM8903_BIAS_ENA
, 0);
1181 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1182 WM8903_VMID_SOFT_MASK
,
1183 2 << WM8903_VMID_SOFT_SHIFT
);
1185 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1186 WM8903_VMID_BUF_ENA
, 0);
1190 snd_soc_update_bits(codec
, WM8903_VMID_CONTROL_0
,
1191 WM8903_VMID_TIE_ENA
| WM8903_BUFIO_ENA
|
1192 WM8903_VMID_IO_ENA
| WM8903_VMID_RES_MASK
|
1193 WM8903_VMID_SOFT_MASK
|
1194 WM8903_VMID_BUF_ENA
, 0);
1196 snd_soc_update_bits(codec
, WM8903_BIAS_CONTROL_0
,
1197 WM8903_STARTUP_BIAS_ENA
, 0);
1201 codec
->dapm
.bias_level
= level
;
1206 static int wm8903_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
1207 int clk_id
, unsigned int freq
, int dir
)
1209 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1210 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1212 wm8903
->sysclk
= freq
;
1217 static int wm8903_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
1220 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1221 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1223 aif1
&= ~(WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
| WM8903_AIF_FMT_MASK
|
1224 WM8903_AIF_LRCLK_INV
| WM8903_AIF_BCLK_INV
);
1226 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1227 case SND_SOC_DAIFMT_CBS_CFS
:
1229 case SND_SOC_DAIFMT_CBS_CFM
:
1230 aif1
|= WM8903_LRCLK_DIR
;
1232 case SND_SOC_DAIFMT_CBM_CFM
:
1233 aif1
|= WM8903_LRCLK_DIR
| WM8903_BCLK_DIR
;
1235 case SND_SOC_DAIFMT_CBM_CFS
:
1236 aif1
|= WM8903_BCLK_DIR
;
1242 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1243 case SND_SOC_DAIFMT_DSP_A
:
1246 case SND_SOC_DAIFMT_DSP_B
:
1247 aif1
|= 0x3 | WM8903_AIF_LRCLK_INV
;
1249 case SND_SOC_DAIFMT_I2S
:
1252 case SND_SOC_DAIFMT_RIGHT_J
:
1255 case SND_SOC_DAIFMT_LEFT_J
:
1261 /* Clock inversion */
1262 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1263 case SND_SOC_DAIFMT_DSP_A
:
1264 case SND_SOC_DAIFMT_DSP_B
:
1265 /* frame inversion not valid for DSP modes */
1266 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1267 case SND_SOC_DAIFMT_NB_NF
:
1269 case SND_SOC_DAIFMT_IB_NF
:
1270 aif1
|= WM8903_AIF_BCLK_INV
;
1276 case SND_SOC_DAIFMT_I2S
:
1277 case SND_SOC_DAIFMT_RIGHT_J
:
1278 case SND_SOC_DAIFMT_LEFT_J
:
1279 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1280 case SND_SOC_DAIFMT_NB_NF
:
1282 case SND_SOC_DAIFMT_IB_IF
:
1283 aif1
|= WM8903_AIF_BCLK_INV
| WM8903_AIF_LRCLK_INV
;
1285 case SND_SOC_DAIFMT_IB_NF
:
1286 aif1
|= WM8903_AIF_BCLK_INV
;
1288 case SND_SOC_DAIFMT_NB_IF
:
1289 aif1
|= WM8903_AIF_LRCLK_INV
;
1299 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1304 static int wm8903_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1306 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1309 reg
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1312 reg
|= WM8903_DAC_MUTE
;
1314 reg
&= ~WM8903_DAC_MUTE
;
1316 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, reg
);
1321 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1322 * for optimal performance so we list the lower rates first and match
1323 * on the last match we find. */
1329 } clk_sys_ratios
[] = {
1330 { 64, 0x0, 0x0, 1 },
1331 { 68, 0x0, 0x1, 1 },
1332 { 125, 0x0, 0x2, 1 },
1333 { 128, 0x1, 0x0, 1 },
1334 { 136, 0x1, 0x1, 1 },
1335 { 192, 0x2, 0x0, 1 },
1336 { 204, 0x2, 0x1, 1 },
1338 { 64, 0x0, 0x0, 2 },
1339 { 68, 0x0, 0x1, 2 },
1340 { 125, 0x0, 0x2, 2 },
1341 { 128, 0x1, 0x0, 2 },
1342 { 136, 0x1, 0x1, 2 },
1343 { 192, 0x2, 0x0, 2 },
1344 { 204, 0x2, 0x1, 2 },
1346 { 250, 0x2, 0x2, 1 },
1347 { 256, 0x3, 0x0, 1 },
1348 { 272, 0x3, 0x1, 1 },
1349 { 384, 0x4, 0x0, 1 },
1350 { 408, 0x4, 0x1, 1 },
1351 { 375, 0x4, 0x2, 1 },
1352 { 512, 0x5, 0x0, 1 },
1353 { 544, 0x5, 0x1, 1 },
1354 { 500, 0x5, 0x2, 1 },
1355 { 768, 0x6, 0x0, 1 },
1356 { 816, 0x6, 0x1, 1 },
1357 { 750, 0x6, 0x2, 1 },
1358 { 1024, 0x7, 0x0, 1 },
1359 { 1088, 0x7, 0x1, 1 },
1360 { 1000, 0x7, 0x2, 1 },
1361 { 1408, 0x8, 0x0, 1 },
1362 { 1496, 0x8, 0x1, 1 },
1363 { 1536, 0x9, 0x0, 1 },
1364 { 1632, 0x9, 0x1, 1 },
1365 { 1500, 0x9, 0x2, 1 },
1367 { 250, 0x2, 0x2, 2 },
1368 { 256, 0x3, 0x0, 2 },
1369 { 272, 0x3, 0x1, 2 },
1370 { 384, 0x4, 0x0, 2 },
1371 { 408, 0x4, 0x1, 2 },
1372 { 375, 0x4, 0x2, 2 },
1373 { 512, 0x5, 0x0, 2 },
1374 { 544, 0x5, 0x1, 2 },
1375 { 500, 0x5, 0x2, 2 },
1376 { 768, 0x6, 0x0, 2 },
1377 { 816, 0x6, 0x1, 2 },
1378 { 750, 0x6, 0x2, 2 },
1379 { 1024, 0x7, 0x0, 2 },
1380 { 1088, 0x7, 0x1, 2 },
1381 { 1000, 0x7, 0x2, 2 },
1382 { 1408, 0x8, 0x0, 2 },
1383 { 1496, 0x8, 0x1, 2 },
1384 { 1536, 0x9, 0x0, 2 },
1385 { 1632, 0x9, 0x1, 2 },
1386 { 1500, 0x9, 0x2, 2 },
1389 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1413 /* Sample rates for DSP */
1417 } sample_rates
[] = {
1432 static int wm8903_hw_params(struct snd_pcm_substream
*substream
,
1433 struct snd_pcm_hw_params
*params
,
1434 struct snd_soc_dai
*dai
)
1436 struct snd_soc_codec
*codec
= dai
->codec
;
1437 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1438 int fs
= params_rate(params
);
1448 u16 aif1
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_1
);
1449 u16 aif2
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_2
);
1450 u16 aif3
= snd_soc_read(codec
, WM8903_AUDIO_INTERFACE_3
);
1451 u16 clock0
= snd_soc_read(codec
, WM8903_CLOCK_RATES_0
);
1452 u16 clock1
= snd_soc_read(codec
, WM8903_CLOCK_RATES_1
);
1453 u16 dac_digital1
= snd_soc_read(codec
, WM8903_DAC_DIGITAL_1
);
1455 /* Enable sloping stopband filter for low sample rates */
1457 dac_digital1
|= WM8903_DAC_SB_FILT
;
1459 dac_digital1
&= ~WM8903_DAC_SB_FILT
;
1461 /* Configure sample rate logic for DSP - choose nearest rate */
1463 best_val
= abs(sample_rates
[dsp_config
].rate
- fs
);
1464 for (i
= 1; i
< ARRAY_SIZE(sample_rates
); i
++) {
1465 cur_val
= abs(sample_rates
[i
].rate
- fs
);
1466 if (cur_val
<= best_val
) {
1472 dev_dbg(codec
->dev
, "DSP fs = %dHz\n", sample_rates
[dsp_config
].rate
);
1473 clock1
&= ~WM8903_SAMPLE_RATE_MASK
;
1474 clock1
|= sample_rates
[dsp_config
].value
;
1476 aif1
&= ~WM8903_AIF_WL_MASK
;
1478 switch (params_format(params
)) {
1479 case SNDRV_PCM_FORMAT_S16_LE
:
1482 case SNDRV_PCM_FORMAT_S20_3LE
:
1486 case SNDRV_PCM_FORMAT_S24_LE
:
1490 case SNDRV_PCM_FORMAT_S32_LE
:
1498 dev_dbg(codec
->dev
, "MCLK = %dHz, target sample rate = %dHz\n",
1499 wm8903
->sysclk
, fs
);
1501 /* We may not have an MCLK which allows us to generate exactly
1502 * the clock we want, particularly with USB derived inputs, so
1506 best_val
= abs((wm8903
->sysclk
/
1507 (clk_sys_ratios
[0].mclk_div
*
1508 clk_sys_ratios
[0].div
)) - fs
);
1509 for (i
= 1; i
< ARRAY_SIZE(clk_sys_ratios
); i
++) {
1510 cur_val
= abs((wm8903
->sysclk
/
1511 (clk_sys_ratios
[i
].mclk_div
*
1512 clk_sys_ratios
[i
].div
)) - fs
);
1514 if (cur_val
<= best_val
) {
1520 if (clk_sys_ratios
[clk_config
].mclk_div
== 2) {
1521 clock0
|= WM8903_MCLKDIV2
;
1522 clk_sys
= wm8903
->sysclk
/ 2;
1524 clock0
&= ~WM8903_MCLKDIV2
;
1525 clk_sys
= wm8903
->sysclk
;
1528 clock1
&= ~(WM8903_CLK_SYS_RATE_MASK
|
1529 WM8903_CLK_SYS_MODE_MASK
);
1530 clock1
|= clk_sys_ratios
[clk_config
].rate
<< WM8903_CLK_SYS_RATE_SHIFT
;
1531 clock1
|= clk_sys_ratios
[clk_config
].mode
<< WM8903_CLK_SYS_MODE_SHIFT
;
1533 dev_dbg(codec
->dev
, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1534 clk_sys_ratios
[clk_config
].rate
,
1535 clk_sys_ratios
[clk_config
].mode
,
1536 clk_sys_ratios
[clk_config
].div
);
1538 dev_dbg(codec
->dev
, "Actual CLK_SYS = %dHz\n", clk_sys
);
1540 /* We may not get quite the right frequency if using
1541 * approximate clocks so look for the closest match that is
1542 * higher than the target (we need to ensure that there enough
1543 * BCLKs to clock out the samples).
1546 best_val
= ((clk_sys
* 10) / bclk_divs
[0].ratio
) - bclk
;
1548 while (i
< ARRAY_SIZE(bclk_divs
)) {
1549 cur_val
= ((clk_sys
* 10) / bclk_divs
[i
].ratio
) - bclk
;
1550 if (cur_val
< 0) /* BCLK table is sorted */
1557 aif2
&= ~WM8903_BCLK_DIV_MASK
;
1558 aif3
&= ~WM8903_LRCLK_RATE_MASK
;
1560 dev_dbg(codec
->dev
, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1561 bclk_divs
[bclk_div
].ratio
/ 10, bclk
,
1562 (clk_sys
* 10) / bclk_divs
[bclk_div
].ratio
);
1564 aif2
|= bclk_divs
[bclk_div
].div
;
1567 wm8903
->fs
= params_rate(params
);
1568 wm8903_set_deemph(codec
);
1570 snd_soc_write(codec
, WM8903_CLOCK_RATES_0
, clock0
);
1571 snd_soc_write(codec
, WM8903_CLOCK_RATES_1
, clock1
);
1572 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_1
, aif1
);
1573 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_2
, aif2
);
1574 snd_soc_write(codec
, WM8903_AUDIO_INTERFACE_3
, aif3
);
1575 snd_soc_write(codec
, WM8903_DAC_DIGITAL_1
, dac_digital1
);
1581 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1583 * @codec: WM8903 codec
1584 * @jack: jack to report detection events on
1585 * @det: value to report for presence detection
1586 * @shrt: value to report for short detection
1588 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1589 * being used to bring out signals to the processor then only platform
1590 * data configuration is needed for WM8903 and processor GPIOs should
1591 * be configured using snd_soc_jack_add_gpios() instead.
1593 * The current threasholds for detection should be configured using
1594 * micdet_cfg in the platform data. Using this function will force on
1595 * the microphone bias for the device.
1597 int wm8903_mic_detect(struct snd_soc_codec
*codec
, struct snd_soc_jack
*jack
,
1600 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1601 int irq_mask
= WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
;
1603 dev_dbg(codec
->dev
, "Enabling microphone detection: %x %x\n",
1606 /* Store the configuration */
1607 wm8903
->mic_jack
= jack
;
1608 wm8903
->mic_det
= det
;
1609 wm8903
->mic_short
= shrt
;
1611 /* Enable interrupts we've got a report configured for */
1613 irq_mask
&= ~WM8903_MICDET_EINT
;
1615 irq_mask
&= ~WM8903_MICSHRT_EINT
;
1617 snd_soc_update_bits(codec
, WM8903_INTERRUPT_STATUS_1_MASK
,
1618 WM8903_MICDET_EINT
| WM8903_MICSHRT_EINT
,
1622 /* Enable mic detection, this may not have been set through
1623 * platform data (eg, if the defaults are OK). */
1624 snd_soc_update_bits(codec
, WM8903_WRITE_SEQUENCER_0
,
1625 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
1626 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1627 WM8903_MICDET_ENA
, WM8903_MICDET_ENA
);
1629 snd_soc_update_bits(codec
, WM8903_MIC_BIAS_CONTROL_0
,
1630 WM8903_MICDET_ENA
, 0);
1635 EXPORT_SYMBOL_GPL(wm8903_mic_detect
);
1637 static irqreturn_t
wm8903_irq(int irq
, void *data
)
1639 struct wm8903_priv
*wm8903
= data
;
1640 int mic_report
, ret
;
1641 unsigned int int_val
, mask
, int_pol
;
1643 ret
= regmap_read(wm8903
->regmap
, WM8903_INTERRUPT_STATUS_1_MASK
,
1646 dev_err(wm8903
->dev
, "Failed to read IRQ mask: %d\n", ret
);
1650 ret
= regmap_read(wm8903
->regmap
, WM8903_INTERRUPT_STATUS_1
, &int_val
);
1652 dev_err(wm8903
->dev
, "Failed to read IRQ status: %d\n", ret
);
1658 if (int_val
& WM8903_WSEQ_BUSY_EINT
) {
1659 dev_warn(wm8903
->dev
, "Write sequencer done\n");
1663 * The rest is microphone jack detection. We need to manually
1664 * invert the polarity of the interrupt after each event - to
1665 * simplify the code keep track of the last state we reported
1666 * and just invert the relevant bits in both the report and
1667 * the polarity register.
1669 mic_report
= wm8903
->mic_last_report
;
1670 ret
= regmap_read(wm8903
->regmap
, WM8903_INTERRUPT_POLARITY_1
,
1673 dev_err(wm8903
->dev
, "Failed to read interrupt polarity: %d\n",
1678 #ifndef CONFIG_SND_SOC_WM8903_MODULE
1679 if (int_val
& (WM8903_MICSHRT_EINT
| WM8903_MICDET_EINT
))
1680 trace_snd_soc_jack_irq(dev_name(wm8903
->dev
));
1683 if (int_val
& WM8903_MICSHRT_EINT
) {
1684 dev_dbg(wm8903
->dev
, "Microphone short (pol=%x)\n", int_pol
);
1686 mic_report
^= wm8903
->mic_short
;
1687 int_pol
^= WM8903_MICSHRT_INV
;
1690 if (int_val
& WM8903_MICDET_EINT
) {
1691 dev_dbg(wm8903
->dev
, "Microphone detect (pol=%x)\n", int_pol
);
1693 mic_report
^= wm8903
->mic_det
;
1694 int_pol
^= WM8903_MICDET_INV
;
1696 msleep(wm8903
->mic_delay
);
1699 regmap_update_bits(wm8903
->regmap
, WM8903_INTERRUPT_POLARITY_1
,
1700 WM8903_MICSHRT_INV
| WM8903_MICDET_INV
, int_pol
);
1702 snd_soc_jack_report(wm8903
->mic_jack
, mic_report
,
1703 wm8903
->mic_short
| wm8903
->mic_det
);
1705 wm8903
->mic_last_report
= mic_report
;
1710 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1711 SNDRV_PCM_RATE_11025 | \
1712 SNDRV_PCM_RATE_16000 | \
1713 SNDRV_PCM_RATE_22050 | \
1714 SNDRV_PCM_RATE_32000 | \
1715 SNDRV_PCM_RATE_44100 | \
1716 SNDRV_PCM_RATE_48000 | \
1717 SNDRV_PCM_RATE_88200 | \
1718 SNDRV_PCM_RATE_96000)
1720 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1721 SNDRV_PCM_RATE_11025 | \
1722 SNDRV_PCM_RATE_16000 | \
1723 SNDRV_PCM_RATE_22050 | \
1724 SNDRV_PCM_RATE_32000 | \
1725 SNDRV_PCM_RATE_44100 | \
1726 SNDRV_PCM_RATE_48000)
1728 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1729 SNDRV_PCM_FMTBIT_S20_3LE |\
1730 SNDRV_PCM_FMTBIT_S24_LE)
1732 static const struct snd_soc_dai_ops wm8903_dai_ops
= {
1733 .hw_params
= wm8903_hw_params
,
1734 .digital_mute
= wm8903_digital_mute
,
1735 .set_fmt
= wm8903_set_dai_fmt
,
1736 .set_sysclk
= wm8903_set_dai_sysclk
,
1739 static struct snd_soc_dai_driver wm8903_dai
= {
1740 .name
= "wm8903-hifi",
1742 .stream_name
= "Playback",
1745 .rates
= WM8903_PLAYBACK_RATES
,
1746 .formats
= WM8903_FORMATS
,
1749 .stream_name
= "Capture",
1752 .rates
= WM8903_CAPTURE_RATES
,
1753 .formats
= WM8903_FORMATS
,
1755 .ops
= &wm8903_dai_ops
,
1756 .symmetric_rates
= 1,
1759 static int wm8903_suspend(struct snd_soc_codec
*codec
)
1761 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1766 static int wm8903_resume(struct snd_soc_codec
*codec
)
1768 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1770 regcache_sync(wm8903
->regmap
);
1772 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1777 #ifdef CONFIG_GPIOLIB
1778 static inline struct wm8903_priv
*gpio_to_wm8903(struct gpio_chip
*chip
)
1780 return container_of(chip
, struct wm8903_priv
, gpio_chip
);
1783 static int wm8903_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
1785 if (offset
>= WM8903_NUM_GPIO
)
1791 static int wm8903_gpio_direction_in(struct gpio_chip
*chip
, unsigned offset
)
1793 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1794 unsigned int mask
, val
;
1797 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
;
1798 val
= (WM8903_GPn_FN_GPIO_INPUT
<< WM8903_GP1_FN_SHIFT
) |
1801 ret
= regmap_update_bits(wm8903
->regmap
,
1802 WM8903_GPIO_CONTROL_1
+ offset
, mask
, val
);
1809 static int wm8903_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1811 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1814 regmap_read(wm8903
->regmap
, WM8903_GPIO_CONTROL_1
+ offset
, ®
);
1816 return (reg
& WM8903_GP1_LVL_MASK
) >> WM8903_GP1_LVL_SHIFT
;
1819 static int wm8903_gpio_direction_out(struct gpio_chip
*chip
,
1820 unsigned offset
, int value
)
1822 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1823 unsigned int mask
, val
;
1826 mask
= WM8903_GP1_FN_MASK
| WM8903_GP1_DIR_MASK
| WM8903_GP1_LVL_MASK
;
1827 val
= (WM8903_GPn_FN_GPIO_OUTPUT
<< WM8903_GP1_FN_SHIFT
) |
1828 (value
<< WM8903_GP2_LVL_SHIFT
);
1830 ret
= regmap_update_bits(wm8903
->regmap
,
1831 WM8903_GPIO_CONTROL_1
+ offset
, mask
, val
);
1838 static void wm8903_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1840 struct wm8903_priv
*wm8903
= gpio_to_wm8903(chip
);
1842 regmap_update_bits(wm8903
->regmap
, WM8903_GPIO_CONTROL_1
+ offset
,
1843 WM8903_GP1_LVL_MASK
,
1844 !!value
<< WM8903_GP1_LVL_SHIFT
);
1847 static struct gpio_chip wm8903_template_chip
= {
1849 .owner
= THIS_MODULE
,
1850 .request
= wm8903_gpio_request
,
1851 .direction_input
= wm8903_gpio_direction_in
,
1852 .get
= wm8903_gpio_get
,
1853 .direction_output
= wm8903_gpio_direction_out
,
1854 .set
= wm8903_gpio_set
,
1858 static void wm8903_init_gpio(struct wm8903_priv
*wm8903
)
1860 struct wm8903_platform_data
*pdata
= wm8903
->pdata
;
1863 wm8903
->gpio_chip
= wm8903_template_chip
;
1864 wm8903
->gpio_chip
.ngpio
= WM8903_NUM_GPIO
;
1865 wm8903
->gpio_chip
.dev
= wm8903
->dev
;
1867 if (pdata
->gpio_base
)
1868 wm8903
->gpio_chip
.base
= pdata
->gpio_base
;
1870 wm8903
->gpio_chip
.base
= -1;
1872 ret
= gpiochip_add(&wm8903
->gpio_chip
);
1874 dev_err(wm8903
->dev
, "Failed to add GPIOs: %d\n", ret
);
1877 static void wm8903_free_gpio(struct wm8903_priv
*wm8903
)
1881 ret
= gpiochip_remove(&wm8903
->gpio_chip
);
1883 dev_err(wm8903
->dev
, "Failed to remove GPIOs: %d\n", ret
);
1886 static void wm8903_init_gpio(struct wm8903_priv
*wm8903
)
1890 static void wm8903_free_gpio(struct wm8903_priv
*wm8903
)
1895 static int wm8903_probe(struct snd_soc_codec
*codec
)
1897 struct wm8903_priv
*wm8903
= snd_soc_codec_get_drvdata(codec
);
1900 wm8903
->codec
= codec
;
1901 codec
->control_data
= wm8903
->regmap
;
1903 ret
= snd_soc_codec_set_cache_io(codec
, 8, 16, SND_SOC_REGMAP
);
1905 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
1909 /* power on device */
1910 wm8903_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
1915 /* power down chip */
1916 static int wm8903_remove(struct snd_soc_codec
*codec
)
1918 wm8903_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
1923 static struct snd_soc_codec_driver soc_codec_dev_wm8903
= {
1924 .probe
= wm8903_probe
,
1925 .remove
= wm8903_remove
,
1926 .suspend
= wm8903_suspend
,
1927 .resume
= wm8903_resume
,
1928 .set_bias_level
= wm8903_set_bias_level
,
1929 .seq_notifier
= wm8903_seq_notifier
,
1930 .controls
= wm8903_snd_controls
,
1931 .num_controls
= ARRAY_SIZE(wm8903_snd_controls
),
1932 .dapm_widgets
= wm8903_dapm_widgets
,
1933 .num_dapm_widgets
= ARRAY_SIZE(wm8903_dapm_widgets
),
1934 .dapm_routes
= wm8903_intercon
,
1935 .num_dapm_routes
= ARRAY_SIZE(wm8903_intercon
),
1938 static const struct regmap_config wm8903_regmap
= {
1942 .max_register
= WM8903_MAX_REGISTER
,
1943 .volatile_reg
= wm8903_volatile_register
,
1944 .readable_reg
= wm8903_readable_register
,
1946 .cache_type
= REGCACHE_RBTREE
,
1947 .reg_defaults
= wm8903_reg_defaults
,
1948 .num_reg_defaults
= ARRAY_SIZE(wm8903_reg_defaults
),
1951 static int wm8903_set_pdata_irq_trigger(struct i2c_client
*i2c
,
1952 struct wm8903_platform_data
*pdata
)
1954 struct irq_data
*irq_data
= irq_get_irq_data(i2c
->irq
);
1956 dev_err(&i2c
->dev
, "Invalid IRQ: %d\n",
1961 switch (irqd_get_trigger_type(irq_data
)) {
1965 * We assume the controller imposes no restrictions,
1966 * so we are able to select active-high
1969 case IRQ_TYPE_LEVEL_HIGH
:
1970 pdata
->irq_active_low
= false;
1972 case IRQ_TYPE_LEVEL_LOW
:
1973 pdata
->irq_active_low
= true;
1980 static int wm8903_set_pdata_from_of(struct i2c_client
*i2c
,
1981 struct wm8903_platform_data
*pdata
)
1983 const struct device_node
*np
= i2c
->dev
.of_node
;
1987 if (of_property_read_u32(np
, "micdet-cfg", &val32
) >= 0)
1988 pdata
->micdet_cfg
= val32
;
1990 if (of_property_read_u32(np
, "micdet-delay", &val32
) >= 0)
1991 pdata
->micdet_delay
= val32
;
1993 if (of_property_read_u32_array(np
, "gpio-cfg", pdata
->gpio_cfg
,
1994 ARRAY_SIZE(pdata
->gpio_cfg
)) >= 0) {
1996 * In device tree: 0 means "write 0",
1997 * 0xffffffff means "don't touch".
1999 * In platform data: 0 means "don't touch",
2000 * 0x8000 means "write 0".
2002 * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000.
2004 * Convert from DT to pdata representation here,
2005 * so no other code needs to change.
2007 for (i
= 0; i
< ARRAY_SIZE(pdata
->gpio_cfg
); i
++) {
2008 if (pdata
->gpio_cfg
[i
] == 0) {
2009 pdata
->gpio_cfg
[i
] = WM8903_GPIO_CONFIG_ZERO
;
2010 } else if (pdata
->gpio_cfg
[i
] == 0xffffffff) {
2011 pdata
->gpio_cfg
[i
] = 0;
2012 } else if (pdata
->gpio_cfg
[i
] > 0x7fff) {
2013 dev_err(&i2c
->dev
, "Invalid gpio-cfg[%d] %x\n",
2014 i
, pdata
->gpio_cfg
[i
]);
2023 static __devinit
int wm8903_i2c_probe(struct i2c_client
*i2c
,
2024 const struct i2c_device_id
*id
)
2026 struct wm8903_platform_data
*pdata
= dev_get_platdata(&i2c
->dev
);
2027 struct wm8903_priv
*wm8903
;
2029 bool mic_gpio
= false;
2030 unsigned int val
, irq_pol
;
2033 wm8903
= devm_kzalloc(&i2c
->dev
, sizeof(struct wm8903_priv
),
2037 wm8903
->dev
= &i2c
->dev
;
2039 wm8903
->regmap
= devm_regmap_init_i2c(i2c
, &wm8903_regmap
);
2040 if (IS_ERR(wm8903
->regmap
)) {
2041 ret
= PTR_ERR(wm8903
->regmap
);
2042 dev_err(&i2c
->dev
, "Failed to allocate register map: %d\n",
2047 i2c_set_clientdata(i2c
, wm8903
);
2049 /* If no platform data was supplied, create storage for defaults */
2051 wm8903
->pdata
= pdata
;
2053 wm8903
->pdata
= devm_kzalloc(&i2c
->dev
,
2054 sizeof(struct wm8903_platform_data
),
2056 if (wm8903
->pdata
== NULL
) {
2057 dev_err(&i2c
->dev
, "Failed to allocate pdata\n");
2062 ret
= wm8903_set_pdata_irq_trigger(i2c
, wm8903
->pdata
);
2067 if (i2c
->dev
.of_node
) {
2068 ret
= wm8903_set_pdata_from_of(i2c
, wm8903
->pdata
);
2074 pdata
= wm8903
->pdata
;
2076 ret
= regmap_read(wm8903
->regmap
, WM8903_SW_RESET_AND_ID
, &val
);
2078 dev_err(&i2c
->dev
, "Failed to read chip ID: %d\n", ret
);
2081 if (val
!= 0x8903) {
2082 dev_err(&i2c
->dev
, "Device with ID %x is not a WM8903\n", val
);
2087 ret
= regmap_read(wm8903
->regmap
, WM8903_REVISION_NUMBER
, &val
);
2089 dev_err(&i2c
->dev
, "Failed to read chip revision: %d\n", ret
);
2092 dev_info(&i2c
->dev
, "WM8903 revision %c\n",
2093 (val
& WM8903_CHIP_REV_MASK
) + 'A');
2095 /* Reset the device */
2096 regmap_write(wm8903
->regmap
, WM8903_SW_RESET_AND_ID
, 0x8903);
2098 wm8903_init_gpio(wm8903
);
2100 /* Set up GPIO pin state, detect if any are MIC detect outputs */
2101 for (i
= 0; i
< ARRAY_SIZE(pdata
->gpio_cfg
); i
++) {
2102 if ((!pdata
->gpio_cfg
[i
]) ||
2103 (pdata
->gpio_cfg
[i
] > WM8903_GPIO_CONFIG_ZERO
))
2106 regmap_write(wm8903
->regmap
, WM8903_GPIO_CONTROL_1
+ i
,
2107 pdata
->gpio_cfg
[i
] & 0x7fff);
2109 val
= (pdata
->gpio_cfg
[i
] & WM8903_GP1_FN_MASK
)
2110 >> WM8903_GP1_FN_SHIFT
;
2113 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT
:
2114 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT
:
2122 /* Set up microphone detection */
2123 regmap_write(wm8903
->regmap
, WM8903_MIC_BIAS_CONTROL_0
,
2126 /* Microphone detection needs the WSEQ clock */
2127 if (pdata
->micdet_cfg
)
2128 regmap_update_bits(wm8903
->regmap
, WM8903_WRITE_SEQUENCER_0
,
2129 WM8903_WSEQ_ENA
, WM8903_WSEQ_ENA
);
2131 /* If microphone detection is enabled by pdata but
2132 * detected via IRQ then interrupts can be lost before
2133 * the machine driver has set up microphone detection
2134 * IRQs as the IRQs are clear on read. The detection
2135 * will be enabled when the machine driver configures.
2137 WARN_ON(!mic_gpio
&& (pdata
->micdet_cfg
& WM8903_MICDET_ENA
));
2139 wm8903
->mic_delay
= pdata
->micdet_delay
;
2142 if (pdata
->irq_active_low
) {
2143 trigger
= IRQF_TRIGGER_LOW
;
2144 irq_pol
= WM8903_IRQ_POL
;
2146 trigger
= IRQF_TRIGGER_HIGH
;
2150 regmap_update_bits(wm8903
->regmap
, WM8903_INTERRUPT_CONTROL
,
2151 WM8903_IRQ_POL
, irq_pol
);
2153 ret
= request_threaded_irq(i2c
->irq
, NULL
, wm8903_irq
,
2154 trigger
| IRQF_ONESHOT
,
2157 dev_err(wm8903
->dev
, "Failed to request IRQ: %d\n",
2162 /* Enable write sequencer interrupts */
2163 regmap_update_bits(wm8903
->regmap
,
2164 WM8903_INTERRUPT_STATUS_1_MASK
,
2165 WM8903_IM_WSEQ_BUSY_EINT
, 0);
2168 /* Latch volume update bits */
2169 regmap_update_bits(wm8903
->regmap
, WM8903_ADC_DIGITAL_VOLUME_LEFT
,
2170 WM8903_ADCVU
, WM8903_ADCVU
);
2171 regmap_update_bits(wm8903
->regmap
, WM8903_ADC_DIGITAL_VOLUME_RIGHT
,
2172 WM8903_ADCVU
, WM8903_ADCVU
);
2174 regmap_update_bits(wm8903
->regmap
, WM8903_DAC_DIGITAL_VOLUME_LEFT
,
2175 WM8903_DACVU
, WM8903_DACVU
);
2176 regmap_update_bits(wm8903
->regmap
, WM8903_DAC_DIGITAL_VOLUME_RIGHT
,
2177 WM8903_DACVU
, WM8903_DACVU
);
2179 regmap_update_bits(wm8903
->regmap
, WM8903_ANALOGUE_OUT1_LEFT
,
2180 WM8903_HPOUTVU
, WM8903_HPOUTVU
);
2181 regmap_update_bits(wm8903
->regmap
, WM8903_ANALOGUE_OUT1_RIGHT
,
2182 WM8903_HPOUTVU
, WM8903_HPOUTVU
);
2184 regmap_update_bits(wm8903
->regmap
, WM8903_ANALOGUE_OUT2_LEFT
,
2185 WM8903_LINEOUTVU
, WM8903_LINEOUTVU
);
2186 regmap_update_bits(wm8903
->regmap
, WM8903_ANALOGUE_OUT2_RIGHT
,
2187 WM8903_LINEOUTVU
, WM8903_LINEOUTVU
);
2189 regmap_update_bits(wm8903
->regmap
, WM8903_ANALOGUE_OUT3_LEFT
,
2190 WM8903_SPKVU
, WM8903_SPKVU
);
2191 regmap_update_bits(wm8903
->regmap
, WM8903_ANALOGUE_OUT3_RIGHT
,
2192 WM8903_SPKVU
, WM8903_SPKVU
);
2194 /* Enable DAC soft mute by default */
2195 regmap_update_bits(wm8903
->regmap
, WM8903_DAC_DIGITAL_1
,
2196 WM8903_DAC_MUTEMODE
| WM8903_DAC_MUTE
,
2197 WM8903_DAC_MUTEMODE
| WM8903_DAC_MUTE
);
2199 ret
= snd_soc_register_codec(&i2c
->dev
,
2200 &soc_codec_dev_wm8903
, &wm8903_dai
, 1);
2209 static __devexit
int wm8903_i2c_remove(struct i2c_client
*client
)
2211 struct wm8903_priv
*wm8903
= i2c_get_clientdata(client
);
2214 free_irq(client
->irq
, wm8903
);
2215 wm8903_free_gpio(wm8903
);
2216 snd_soc_unregister_codec(&client
->dev
);
2221 static const struct of_device_id wm8903_of_match
[] = {
2222 { .compatible
= "wlf,wm8903", },
2225 MODULE_DEVICE_TABLE(of
, wm8903_of_match
);
2227 static const struct i2c_device_id wm8903_i2c_id
[] = {
2231 MODULE_DEVICE_TABLE(i2c
, wm8903_i2c_id
);
2233 static struct i2c_driver wm8903_i2c_driver
= {
2236 .owner
= THIS_MODULE
,
2237 .of_match_table
= wm8903_of_match
,
2239 .probe
= wm8903_i2c_probe
,
2240 .remove
= __devexit_p(wm8903_i2c_remove
),
2241 .id_table
= wm8903_i2c_id
,
2244 static int __init
wm8903_modinit(void)
2247 ret
= i2c_add_driver(&wm8903_i2c_driver
);
2249 printk(KERN_ERR
"Failed to register wm8903 I2C driver: %d\n",
2254 module_init(wm8903_modinit
);
2256 static void __exit
wm8903_exit(void)
2258 i2c_del_driver(&wm8903_i2c_driver
);
2260 module_exit(wm8903_exit
);
2262 MODULE_DESCRIPTION("ASoC WM8903 driver");
2263 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2264 MODULE_LICENSE("GPL");