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Revert "microblaze_mmu_v2: Update signal returning address"
[linux/fpc-iii.git] / sound / soc / codecs / wm8961.c
blob01edbcc754d2cb7ef10124963a701583cf75f762
1 /*
2 * wm8961.c -- WM8961 ALSA SoC Audio driver
3 *
4 * Copyright 2009-10 Wolfson Microelectronics, plc
5 *
6 * Author: Mark Brown
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Currently unimplemented features:
13 * - ALC
14 */
15
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/pm.h>
21 #include <linux/i2c.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29
30 #include "wm8961.h"
31
32 #define WM8961_MAX_REGISTER 0xFC
33
34 static u16 wm8961_reg_defaults[] = {
35 0x009F, /* R0 - Left Input volume */
36 0x009F, /* R1 - Right Input volume */
37 0x0000, /* R2 - LOUT1 volume */
38 0x0000, /* R3 - ROUT1 volume */
39 0x0020, /* R4 - Clocking1 */
40 0x0008, /* R5 - ADC & DAC Control 1 */
41 0x0000, /* R6 - ADC & DAC Control 2 */
42 0x000A, /* R7 - Audio Interface 0 */
43 0x01F4, /* R8 - Clocking2 */
44 0x0000, /* R9 - Audio Interface 1 */
45 0x00FF, /* R10 - Left DAC volume */
46 0x00FF, /* R11 - Right DAC volume */
47 0x0000, /* R12 */
48 0x0000, /* R13 */
49 0x0040, /* R14 - Audio Interface 2 */
50 0x0000, /* R15 - Software Reset */
51 0x0000, /* R16 */
52 0x007B, /* R17 - ALC1 */
53 0x0000, /* R18 - ALC2 */
54 0x0032, /* R19 - ALC3 */
55 0x0000, /* R20 - Noise Gate */
56 0x00C0, /* R21 - Left ADC volume */
57 0x00C0, /* R22 - Right ADC volume */
58 0x0120, /* R23 - Additional control(1) */
59 0x0000, /* R24 - Additional control(2) */
60 0x0000, /* R25 - Pwr Mgmt (1) */
61 0x0000, /* R26 - Pwr Mgmt (2) */
62 0x0000, /* R27 - Additional Control (3) */
63 0x0000, /* R28 - Anti-pop */
64 0x0000, /* R29 */
65 0x005F, /* R30 - Clocking 3 */
66 0x0000, /* R31 */
67 0x0000, /* R32 - ADCL signal path */
68 0x0000, /* R33 - ADCR signal path */
69 0x0000, /* R34 */
70 0x0000, /* R35 */
71 0x0000, /* R36 */
72 0x0000, /* R37 */
73 0x0000, /* R38 */
74 0x0000, /* R39 */
75 0x0000, /* R40 - LOUT2 volume */
76 0x0000, /* R41 - ROUT2 volume */
77 0x0000, /* R42 */
78 0x0000, /* R43 */
79 0x0000, /* R44 */
80 0x0000, /* R45 */
81 0x0000, /* R46 */
82 0x0000, /* R47 - Pwr Mgmt (3) */
83 0x0023, /* R48 - Additional Control (4) */
84 0x0000, /* R49 - Class D Control 1 */
85 0x0000, /* R50 */
86 0x0003, /* R51 - Class D Control 2 */
87 0x0000, /* R52 */
88 0x0000, /* R53 */
89 0x0000, /* R54 */
90 0x0000, /* R55 */
91 0x0106, /* R56 - Clocking 4 */
92 0x0000, /* R57 - DSP Sidetone 0 */
93 0x0000, /* R58 - DSP Sidetone 1 */
94 0x0000, /* R59 */
95 0x0000, /* R60 - DC Servo 0 */
96 0x0000, /* R61 - DC Servo 1 */
97 0x0000, /* R62 */
98 0x015E, /* R63 - DC Servo 3 */
99 0x0010, /* R64 */
100 0x0010, /* R65 - DC Servo 5 */
101 0x0000, /* R66 */
102 0x0001, /* R67 */
103 0x0003, /* R68 - Analogue PGA Bias */
104 0x0000, /* R69 - Analogue HP 0 */
105 0x0060, /* R70 */
106 0x01FB, /* R71 - Analogue HP 2 */
107 0x0000, /* R72 - Charge Pump 1 */
108 0x0065, /* R73 */
109 0x005F, /* R74 */
110 0x0059, /* R75 */
111 0x006B, /* R76 */
112 0x0038, /* R77 */
113 0x000C, /* R78 */
114 0x000A, /* R79 */
115 0x006B, /* R80 */
116 0x0000, /* R81 */
117 0x0000, /* R82 - Charge Pump B */
118 0x0087, /* R83 */
119 0x0000, /* R84 */
120 0x005C, /* R85 */
121 0x0000, /* R86 */
122 0x0000, /* R87 - Write Sequencer 1 */
123 0x0000, /* R88 - Write Sequencer 2 */
124 0x0000, /* R89 - Write Sequencer 3 */
125 0x0000, /* R90 - Write Sequencer 4 */
126 0x0000, /* R91 - Write Sequencer 5 */
127 0x0000, /* R92 - Write Sequencer 6 */
128 0x0000, /* R93 - Write Sequencer 7 */
129 0x0000, /* R94 */
130 0x0000, /* R95 */
131 0x0000, /* R96 */
132 0x0000, /* R97 */
133 0x0000, /* R98 */
134 0x0000, /* R99 */
135 0x0000, /* R100 */
136 0x0000, /* R101 */
137 0x0000, /* R102 */
138 0x0000, /* R103 */
139 0x0000, /* R104 */
140 0x0000, /* R105 */
141 0x0000, /* R106 */
142 0x0000, /* R107 */
143 0x0000, /* R108 */
144 0x0000, /* R109 */
145 0x0000, /* R110 */
146 0x0000, /* R111 */
147 0x0000, /* R112 */
148 0x0000, /* R113 */
149 0x0000, /* R114 */
150 0x0000, /* R115 */
151 0x0000, /* R116 */
152 0x0000, /* R117 */
153 0x0000, /* R118 */
154 0x0000, /* R119 */
155 0x0000, /* R120 */
156 0x0000, /* R121 */
157 0x0000, /* R122 */
158 0x0000, /* R123 */
159 0x0000, /* R124 */
160 0x0000, /* R125 */
161 0x0000, /* R126 */
162 0x0000, /* R127 */
163 0x0000, /* R128 */
164 0x0000, /* R129 */
165 0x0000, /* R130 */
166 0x0000, /* R131 */
167 0x0000, /* R132 */
168 0x0000, /* R133 */
169 0x0000, /* R134 */
170 0x0000, /* R135 */
171 0x0000, /* R136 */
172 0x0000, /* R137 */
173 0x0000, /* R138 */
174 0x0000, /* R139 */
175 0x0000, /* R140 */
176 0x0000, /* R141 */
177 0x0000, /* R142 */
178 0x0000, /* R143 */
179 0x0000, /* R144 */
180 0x0000, /* R145 */
181 0x0000, /* R146 */
182 0x0000, /* R147 */
183 0x0000, /* R148 */
184 0x0000, /* R149 */
185 0x0000, /* R150 */
186 0x0000, /* R151 */
187 0x0000, /* R152 */
188 0x0000, /* R153 */
189 0x0000, /* R154 */
190 0x0000, /* R155 */
191 0x0000, /* R156 */
192 0x0000, /* R157 */
193 0x0000, /* R158 */
194 0x0000, /* R159 */
195 0x0000, /* R160 */
196 0x0000, /* R161 */
197 0x0000, /* R162 */
198 0x0000, /* R163 */
199 0x0000, /* R164 */
200 0x0000, /* R165 */
201 0x0000, /* R166 */
202 0x0000, /* R167 */
203 0x0000, /* R168 */
204 0x0000, /* R169 */
205 0x0000, /* R170 */
206 0x0000, /* R171 */
207 0x0000, /* R172 */
208 0x0000, /* R173 */
209 0x0000, /* R174 */
210 0x0000, /* R175 */
211 0x0000, /* R176 */
212 0x0000, /* R177 */
213 0x0000, /* R178 */
214 0x0000, /* R179 */
215 0x0000, /* R180 */
216 0x0000, /* R181 */
217 0x0000, /* R182 */
218 0x0000, /* R183 */
219 0x0000, /* R184 */
220 0x0000, /* R185 */
221 0x0000, /* R186 */
222 0x0000, /* R187 */
223 0x0000, /* R188 */
224 0x0000, /* R189 */
225 0x0000, /* R190 */
226 0x0000, /* R191 */
227 0x0000, /* R192 */
228 0x0000, /* R193 */
229 0x0000, /* R194 */
230 0x0000, /* R195 */
231 0x0030, /* R196 */
232 0x0006, /* R197 */
233 0x0000, /* R198 */
234 0x0060, /* R199 */
235 0x0000, /* R200 */
236 0x003F, /* R201 */
237 0x0000, /* R202 */
238 0x0000, /* R203 */
239 0x0000, /* R204 */
240 0x0001, /* R205 */
241 0x0000, /* R206 */
242 0x0181, /* R207 */
243 0x0005, /* R208 */
244 0x0008, /* R209 */
245 0x0008, /* R210 */
246 0x0000, /* R211 */
247 0x013B, /* R212 */
248 0x0000, /* R213 */
249 0x0000, /* R214 */
250 0x0000, /* R215 */
251 0x0000, /* R216 */
252 0x0070, /* R217 */
253 0x0000, /* R218 */
254 0x0000, /* R219 */
255 0x0000, /* R220 */
256 0x0000, /* R221 */
257 0x0000, /* R222 */
258 0x0003, /* R223 */
259 0x0000, /* R224 */
260 0x0000, /* R225 */
261 0x0001, /* R226 */
262 0x0008, /* R227 */
263 0x0000, /* R228 */
264 0x0000, /* R229 */
265 0x0000, /* R230 */
266 0x0000, /* R231 */
267 0x0004, /* R232 */
268 0x0000, /* R233 */
269 0x0000, /* R234 */
270 0x0000, /* R235 */
271 0x0000, /* R236 */
272 0x0000, /* R237 */
273 0x0080, /* R238 */
274 0x0000, /* R239 */
275 0x0000, /* R240 */
276 0x0000, /* R241 */
277 0x0000, /* R242 */
278 0x0000, /* R243 */
279 0x0000, /* R244 */
280 0x0052, /* R245 */
281 0x0110, /* R246 */
282 0x0040, /* R247 */
283 0x0000, /* R248 */
284 0x0030, /* R249 */
285 0x0000, /* R250 */
286 0x0000, /* R251 */
287 0x0001, /* R252 - General test 1 */
288 };
289
290 struct wm8961_priv {
291 enum snd_soc_control_type control_type;
292 int sysclk;
293 };
294
295 static int wm8961_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
296 {
297 switch (reg) {
298 case WM8961_SOFTWARE_RESET:
299 case WM8961_WRITE_SEQUENCER_7:
300 case WM8961_DC_SERVO_1:
301 return 1;
302
303 default:
304 return 0;
305 }
306 }
307
308 static int wm8961_reset(struct snd_soc_codec *codec)
309 {
310 return snd_soc_write(codec, WM8961_SOFTWARE_RESET, 0);
311 }
312
313 /*
314 * The headphone output supports special anti-pop sequences giving
315 * silent power up and power down.
316 */
317 static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
318 struct snd_kcontrol *kcontrol, int event)
319 {
320 struct snd_soc_codec *codec = w->codec;
321 u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0);
322 u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1);
323 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
324 u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
325 int timeout = 500;
326
327 if (event & SND_SOC_DAPM_POST_PMU) {
328 /* Make sure the output is shorted */
329 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
330 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
331
332 /* Enable the charge pump */
333 cp_reg |= WM8961_CP_ENA;
334 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg);
335 mdelay(5);
336
337 /* Enable the PGA */
338 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
339 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
340
341 /* Enable the amplifier */
342 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
343 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
344
345 /* Second stage enable */
346 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
347 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
348
349 /* Enable the DC servo & trigger startup */
350 dcs_reg |=
351 WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
352 WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
353 dev_dbg(codec->dev, "Enabling DC servo\n");
354
355 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
356 do {
357 msleep(1);
358 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
359 } while (--timeout &&
360 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
361 WM8961_DCS_TRIG_STARTUP_HPL));
362 if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
363 WM8961_DCS_TRIG_STARTUP_HPL))
364 dev_err(codec->dev, "DC servo timed out\n");
365 else
366 dev_dbg(codec->dev, "DC servo startup complete\n");
367
368 /* Enable the output stage */
369 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
370 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
371
372 /* Remove the short on the output stage */
373 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
374 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
375 }
376
377 if (event & SND_SOC_DAPM_PRE_PMD) {
378 /* Short the output */
379 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
380 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
381
382 /* Disable the output stage */
383 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
384 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
385
386 /* Disable DC offset cancellation */
387 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
388 WM8961_DCS_ENA_CHAN_HPL);
389 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
390
391 /* Finish up */
392 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
393 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
394 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
395
396 /* Disable the PGA */
397 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
398 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
399
400 /* Disable the charge pump */
401 dev_dbg(codec->dev, "Disabling charge pump\n");
402 snd_soc_write(codec, WM8961_CHARGE_PUMP_1,
403 cp_reg & ~WM8961_CP_ENA);
404 }
405
406 return 0;
407 }
408
409 static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
410 struct snd_kcontrol *kcontrol, int event)
411 {
412 struct snd_soc_codec *codec = w->codec;
413 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
414 u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1);
415
416 if (event & SND_SOC_DAPM_POST_PMU) {
417 /* Enable the PGA */
418 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
419 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
420
421 /* Enable the amplifier */
422 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
423 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
424 }
425
426 if (event & SND_SOC_DAPM_PRE_PMD) {
427 /* Disable the amplifier */
428 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
429 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
430
431 /* Disable the PGA */
432 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
433 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
434 }
435
436 return 0;
437 }
438
439 static const char *adc_hpf_text[] = {
440 "Hi-fi", "Voice 1", "Voice 2", "Voice 3",
441 };
442
443 static const struct soc_enum adc_hpf =
444 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_2, 7, 4, adc_hpf_text);
445
446 static const char *dac_deemph_text[] = {
447 "None", "32kHz", "44.1kHz", "48kHz",
448 };
449
450 static const struct soc_enum dac_deemph =
451 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_1, 1, 4, dac_deemph_text);
452
453 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
454 static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
455 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
456 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
457 static unsigned int boost_tlv[] = {
458 TLV_DB_RANGE_HEAD(4),
459 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
460 1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
461 2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
462 3, 3, TLV_DB_SCALE_ITEM(29, 0, 0),
463 };
464 static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
465
466 static const struct snd_kcontrol_new wm8961_snd_controls[] = {
467 SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
468 0, 127, 0, out_tlv),
469 SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
470 6, 3, 7, 0, hp_sec_tlv),
471 SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
472 7, 1, 0),
473
474 SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
475 0, 127, 0, out_tlv),
476 SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
477 7, 1, 0),
478 SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
479
480 SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
481 SOC_ENUM("DAC Deemphasis", dac_deemph),
482 SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
483
484 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
485 WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
486
487 SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
488 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
489
490 SOC_DOUBLE_R_TLV("Capture Volume",
491 WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
492 1, 119, 0, adc_tlv),
493 SOC_DOUBLE_R_TLV("Capture Boost Volume",
494 WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
495 4, 3, 0, boost_tlv),
496 SOC_DOUBLE_R_TLV("Capture PGA Volume",
497 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
498 0, 62, 0, pga_tlv),
499 SOC_DOUBLE_R("Capture PGA ZC Switch",
500 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
501 6, 1, 1),
502 SOC_DOUBLE_R("Capture PGA Switch",
503 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
504 7, 1, 1),
505 };
506
507 static const char *sidetone_text[] = {
508 "None", "Left", "Right"
509 };
510
511 static const struct soc_enum dacl_sidetone =
512 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_0, 2, 3, sidetone_text);
513
514 static const struct soc_enum dacr_sidetone =
515 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_1, 2, 3, sidetone_text);
516
517 static const struct snd_kcontrol_new dacl_mux =
518 SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
519
520 static const struct snd_kcontrol_new dacr_mux =
521 SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
522
523 static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
524 SND_SOC_DAPM_INPUT("LINPUT"),
525 SND_SOC_DAPM_INPUT("RINPUT"),
526
527 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
528
529 SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
530 SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
531
532 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
533 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
534
535 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8961_PWR_MGMT_1, 1, 0, NULL, 0),
536
537 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
538 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
539
540 SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
541 SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
542
543 /* Handle as a mono path for DCS */
544 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
545 4, 0, NULL, 0, wm8961_hp_event,
546 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
547 SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
548 4, 0, NULL, 0, wm8961_spk_event,
549 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
550
551 SND_SOC_DAPM_OUTPUT("HP_L"),
552 SND_SOC_DAPM_OUTPUT("HP_R"),
553 SND_SOC_DAPM_OUTPUT("SPK_LN"),
554 SND_SOC_DAPM_OUTPUT("SPK_LP"),
555 SND_SOC_DAPM_OUTPUT("SPK_RN"),
556 SND_SOC_DAPM_OUTPUT("SPK_RP"),
557 };
558
559
560 static const struct snd_soc_dapm_route audio_paths[] = {
561 { "DACL", NULL, "CLK_DSP" },
562 { "DACL", NULL, "DACL Sidetone" },
563 { "DACR", NULL, "CLK_DSP" },
564 { "DACR", NULL, "DACR Sidetone" },
565
566 { "DACL Sidetone", "Left", "ADCL" },
567 { "DACL Sidetone", "Right", "ADCR" },
568
569 { "DACR Sidetone", "Left", "ADCL" },
570 { "DACR Sidetone", "Right", "ADCR" },
571
572 { "HP_L", NULL, "Headphone Output" },
573 { "HP_R", NULL, "Headphone Output" },
574 { "Headphone Output", NULL, "DACL" },
575 { "Headphone Output", NULL, "DACR" },
576
577 { "SPK_LN", NULL, "Speaker Output" },
578 { "SPK_LP", NULL, "Speaker Output" },
579 { "SPK_RN", NULL, "Speaker Output" },
580 { "SPK_RP", NULL, "Speaker Output" },
581
582 { "Speaker Output", NULL, "DACL" },
583 { "Speaker Output", NULL, "DACR" },
584
585 { "ADCL", NULL, "Left Input" },
586 { "ADCL", NULL, "CLK_DSP" },
587 { "ADCR", NULL, "Right Input" },
588 { "ADCR", NULL, "CLK_DSP" },
589
590 { "Left Input", NULL, "LINPUT" },
591 { "Right Input", NULL, "RINPUT" },
592
593 };
594
595 /* Values for CLK_SYS_RATE */
596 static struct {
597 int ratio;
598 u16 val;
599 } wm8961_clk_sys_ratio[] = {
600 { 64, 0 },
601 { 128, 1 },
602 { 192, 2 },
603 { 256, 3 },
604 { 384, 4 },
605 { 512, 5 },
606 { 768, 6 },
607 { 1024, 7 },
608 { 1408, 8 },
609 { 1536, 9 },
610 };
611
612 /* Values for SAMPLE_RATE */
613 static struct {
614 int rate;
615 u16 val;
616 } wm8961_srate[] = {
617 { 48000, 0 },
618 { 44100, 0 },
619 { 32000, 1 },
620 { 22050, 2 },
621 { 24000, 2 },
622 { 16000, 3 },
623 { 11250, 4 },
624 { 12000, 4 },
625 { 8000, 5 },
626 };
627
628 static int wm8961_hw_params(struct snd_pcm_substream *substream,
629 struct snd_pcm_hw_params *params,
630 struct snd_soc_dai *dai)
631 {
632 struct snd_soc_codec *codec = dai->codec;
633 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
634 int i, best, target, fs;
635 u16 reg;
636
637 fs = params_rate(params);
638
639 if (!wm8961->sysclk) {
640 dev_err(codec->dev, "MCLK has not been specified\n");
641 return -EINVAL;
642 }
643
644 /* Find the closest sample rate for the filters */
645 best = 0;
646 for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
647 if (abs(wm8961_srate[i].rate - fs) <
648 abs(wm8961_srate[best].rate - fs))
649 best = i;
650 }
651 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3);
652 reg &= ~WM8961_SAMPLE_RATE_MASK;
653 reg |= wm8961_srate[best].val;
654 snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg);
655 dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n",
656 wm8961_srate[best].rate, fs);
657
658 /* Select a CLK_SYS/fs ratio equal to or higher than required */
659 target = wm8961->sysclk / fs;
660
661 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
662 dev_err(codec->dev,
663 "SYSCLK must be at least 64*fs for DAC\n");
664 return -EINVAL;
665 }
666 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
667 dev_err(codec->dev,
668 "SYSCLK must be at least 256*fs for ADC\n");
669 return -EINVAL;
670 }
671
672 for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
673 if (wm8961_clk_sys_ratio[i].ratio >= target)
674 break;
675 }
676 if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
677 dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n");
678 return -EINVAL;
679 }
680 dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
681 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
682 wm8961->sysclk / fs);
683
684 reg = snd_soc_read(codec, WM8961_CLOCKING_4);
685 reg &= ~WM8961_CLK_SYS_RATE_MASK;
686 reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
687 snd_soc_write(codec, WM8961_CLOCKING_4, reg);
688
689 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
690 reg &= ~WM8961_WL_MASK;
691 switch (params_format(params)) {
692 case SNDRV_PCM_FORMAT_S16_LE:
693 break;
694 case SNDRV_PCM_FORMAT_S20_3LE:
695 reg |= 1 << WM8961_WL_SHIFT;
696 break;
697 case SNDRV_PCM_FORMAT_S24_LE:
698 reg |= 2 << WM8961_WL_SHIFT;
699 break;
700 case SNDRV_PCM_FORMAT_S32_LE:
701 reg |= 3 << WM8961_WL_SHIFT;
702 break;
703 default:
704 return -EINVAL;
705 }
706 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg);
707
708 /* Sloping stop-band filter is recommended for <= 24kHz */
709 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
710 if (fs <= 24000)
711 reg |= WM8961_DACSLOPE;
712 else
713 reg &= ~WM8961_DACSLOPE;
714 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
715
716 return 0;
717 }
718
719 static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
720 unsigned int freq,
721 int dir)
722 {
723 struct snd_soc_codec *codec = dai->codec;
724 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
725 u16 reg = snd_soc_read(codec, WM8961_CLOCKING1);
726
727 if (freq > 33000000) {
728 dev_err(codec->dev, "MCLK must be <33MHz\n");
729 return -EINVAL;
730 }
731
732 if (freq > 16500000) {
733 dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
734 reg |= WM8961_MCLKDIV;
735 freq /= 2;
736 } else {
737 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
738 reg &= ~WM8961_MCLKDIV;
739 }
740
741 snd_soc_write(codec, WM8961_CLOCKING1, reg);
742
743 wm8961->sysclk = freq;
744
745 return 0;
746 }
747
748 static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
749 {
750 struct snd_soc_codec *codec = dai->codec;
751 u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
752
753 aif &= ~(WM8961_BCLKINV | WM8961_LRP |
754 WM8961_MS | WM8961_FORMAT_MASK);
755
756 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
757 case SND_SOC_DAIFMT_CBM_CFM:
758 aif |= WM8961_MS;
759 break;
760 case SND_SOC_DAIFMT_CBS_CFS:
761 break;
762 default:
763 return -EINVAL;
764 }
765
766 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
767 case SND_SOC_DAIFMT_RIGHT_J:
768 break;
769
770 case SND_SOC_DAIFMT_LEFT_J:
771 aif |= 1;
772 break;
773
774 case SND_SOC_DAIFMT_I2S:
775 aif |= 2;
776 break;
777
778 case SND_SOC_DAIFMT_DSP_B:
779 aif |= WM8961_LRP;
780 case SND_SOC_DAIFMT_DSP_A:
781 aif |= 3;
782 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
783 case SND_SOC_DAIFMT_NB_NF:
784 case SND_SOC_DAIFMT_IB_NF:
785 break;
786 default:
787 return -EINVAL;
788 }
789 break;
790
791 default:
792 return -EINVAL;
793 }
794
795 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
796 case SND_SOC_DAIFMT_NB_NF:
797 break;
798 case SND_SOC_DAIFMT_NB_IF:
799 aif |= WM8961_LRP;
800 break;
801 case SND_SOC_DAIFMT_IB_NF:
802 aif |= WM8961_BCLKINV;
803 break;
804 case SND_SOC_DAIFMT_IB_IF:
805 aif |= WM8961_BCLKINV | WM8961_LRP;
806 break;
807 default:
808 return -EINVAL;
809 }
810
811 return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif);
812 }
813
814 static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
815 {
816 struct snd_soc_codec *codec = dai->codec;
817 u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2);
818
819 if (tristate)
820 reg |= WM8961_TRIS;
821 else
822 reg &= ~WM8961_TRIS;
823
824 return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg);
825 }
826
827 static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
828 {
829 struct snd_soc_codec *codec = dai->codec;
830 u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1);
831
832 if (mute)
833 reg |= WM8961_DACMU;
834 else
835 reg &= ~WM8961_DACMU;
836
837 msleep(17);
838
839 return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg);
840 }
841
842 static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
843 {
844 struct snd_soc_codec *codec = dai->codec;
845 u16 reg;
846
847 switch (div_id) {
848 case WM8961_BCLK:
849 reg = snd_soc_read(codec, WM8961_CLOCKING2);
850 reg &= ~WM8961_BCLKDIV_MASK;
851 reg |= div;
852 snd_soc_write(codec, WM8961_CLOCKING2, reg);
853 break;
854
855 case WM8961_LRCLK:
856 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2);
857 reg &= ~WM8961_LRCLK_RATE_MASK;
858 reg |= div;
859 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg);
860 break;
861
862 default:
863 return -EINVAL;
864 }
865
866 return 0;
867 }
868
869 static int wm8961_set_bias_level(struct snd_soc_codec *codec,
870 enum snd_soc_bias_level level)
871 {
872 u16 reg;
873
874 /* This is all slightly unusual since we have no bypass paths
875 * and the output amplifier structure means we can just slam
876 * the biases straight up rather than having to ramp them
877 * slowly.
878 */
879 switch (level) {
880 case SND_SOC_BIAS_ON:
881 break;
882
883 case SND_SOC_BIAS_PREPARE:
884 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
885 /* Enable bias generation */
886 reg = snd_soc_read(codec, WM8961_ANTI_POP);
887 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
888 snd_soc_write(codec, WM8961_ANTI_POP, reg);
889
890 /* VMID=2*50k, VREF */
891 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
892 reg &= ~WM8961_VMIDSEL_MASK;
893 reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
894 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
895 }
896 break;
897
898 case SND_SOC_BIAS_STANDBY:
899 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
900 /* VREF off */
901 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
902 reg &= ~WM8961_VREF;
903 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
904
905 /* Bias generation off */
906 reg = snd_soc_read(codec, WM8961_ANTI_POP);
907 reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
908 snd_soc_write(codec, WM8961_ANTI_POP, reg);
909
910 /* VMID off */
911 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
912 reg &= ~WM8961_VMIDSEL_MASK;
913 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
914 }
915 break;
916
917 case SND_SOC_BIAS_OFF:
918 break;
919 }
920
921 codec->dapm.bias_level = level;
922
923 return 0;
924 }
925
926
927 #define WM8961_RATES SNDRV_PCM_RATE_8000_48000
928
929 #define WM8961_FORMATS \
930 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
931 SNDRV_PCM_FMTBIT_S24_LE)
932
933 static const struct snd_soc_dai_ops wm8961_dai_ops = {
934 .hw_params = wm8961_hw_params,
935 .set_sysclk = wm8961_set_sysclk,
936 .set_fmt = wm8961_set_fmt,
937 .digital_mute = wm8961_digital_mute,
938 .set_tristate = wm8961_set_tristate,
939 .set_clkdiv = wm8961_set_clkdiv,
940 };
941
942 static struct snd_soc_dai_driver wm8961_dai = {
943 .name = "wm8961-hifi",
944 .playback = {
945 .stream_name = "HiFi Playback",
946 .channels_min = 1,
947 .channels_max = 2,
948 .rates = WM8961_RATES,
949 .formats = WM8961_FORMATS,},
950 .capture = {
951 .stream_name = "HiFi Capture",
952 .channels_min = 1,
953 .channels_max = 2,
954 .rates = WM8961_RATES,
955 .formats = WM8961_FORMATS,},
956 .ops = &wm8961_dai_ops,
957 };
958
959 static int wm8961_probe(struct snd_soc_codec *codec)
960 {
961 struct snd_soc_dapm_context *dapm = &codec->dapm;
962 int ret = 0;
963 u16 reg;
964
965 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
966 if (ret != 0) {
967 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
968 return ret;
969 }
970
971 reg = snd_soc_read(codec, WM8961_SOFTWARE_RESET);
972 if (reg != 0x1801) {
973 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg);
974 return -EINVAL;
975 }
976
977 /* This isn't volatile - readback doesn't correspond to write */
978 codec->cache_bypass = 1;
979 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
980 codec->cache_bypass = 0;
981 dev_info(codec->dev, "WM8961 family %d revision %c\n",
982 (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
983 ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
984 + 'A');
985
986 ret = wm8961_reset(codec);
987 if (ret < 0) {
988 dev_err(codec->dev, "Failed to issue reset\n");
989 return ret;
990 }
991
992 /* Enable class W */
993 reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);
994 reg |= WM8961_CP_DYN_PWR_MASK;
995 snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);
996
997 /* Latch volume update bits (right channel only, we always
998 * write both out) and default ZC on. */
999 reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);
1000 snd_soc_write(codec, WM8961_ROUT1_VOLUME,
1001 reg | WM8961_LO1ZC | WM8961_OUT1VU);
1002 snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
1003 reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);
1004 snd_soc_write(codec, WM8961_ROUT2_VOLUME,
1005 reg | WM8961_SPKRZC | WM8961_SPKVU);
1006 snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
1007
1008 reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);
1009 snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
1010 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
1011 snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
1012
1013 /* Use soft mute by default */
1014 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
1015 reg |= WM8961_DACSMM;
1016 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
1017
1018 /* Use automatic clocking mode by default; for now this is all
1019 * we support.
1020 */
1021 reg = snd_soc_read(codec, WM8961_CLOCKING_3);
1022 reg &= ~WM8961_MANUAL_MODE;
1023 snd_soc_write(codec, WM8961_CLOCKING_3, reg);
1024
1025 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1026
1027 snd_soc_add_codec_controls(codec, wm8961_snd_controls,
1028 ARRAY_SIZE(wm8961_snd_controls));
1029 snd_soc_dapm_new_controls(dapm, wm8961_dapm_widgets,
1030 ARRAY_SIZE(wm8961_dapm_widgets));
1031 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
1032
1033 return 0;
1034 }
1035
1036 static int wm8961_remove(struct snd_soc_codec *codec)
1037 {
1038 wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
1039 return 0;
1040 }
1041
1042 #ifdef CONFIG_PM
1043 static int wm8961_suspend(struct snd_soc_codec *codec)
1044 {
1045 wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
1046
1047 return 0;
1048 }
1049
1050 static int wm8961_resume(struct snd_soc_codec *codec)
1051 {
1052 snd_soc_cache_sync(codec);
1053
1054 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1055
1056 return 0;
1057 }
1058 #else
1059 #define wm8961_suspend NULL
1060 #define wm8961_resume NULL
1061 #endif
1062
1063 static struct snd_soc_codec_driver soc_codec_dev_wm8961 = {
1064 .probe = wm8961_probe,
1065 .remove = wm8961_remove,
1066 .suspend = wm8961_suspend,
1067 .resume = wm8961_resume,
1068 .set_bias_level = wm8961_set_bias_level,
1069 .reg_cache_size = ARRAY_SIZE(wm8961_reg_defaults),
1070 .reg_word_size = sizeof(u16),
1071 .reg_cache_default = wm8961_reg_defaults,
1072 .volatile_register = wm8961_volatile_register,
1073 };
1074
1075 static __devinit int wm8961_i2c_probe(struct i2c_client *i2c,
1076 const struct i2c_device_id *id)
1077 {
1078 struct wm8961_priv *wm8961;
1079 int ret;
1080
1081 wm8961 = devm_kzalloc(&i2c->dev, sizeof(struct wm8961_priv),
1082 GFP_KERNEL);
1083 if (wm8961 == NULL)
1084 return -ENOMEM;
1085
1086 i2c_set_clientdata(i2c, wm8961);
1087
1088 ret = snd_soc_register_codec(&i2c->dev,
1089 &soc_codec_dev_wm8961, &wm8961_dai, 1);
1090
1091 return ret;
1092 }
1093
1094 static __devexit int wm8961_i2c_remove(struct i2c_client *client)
1095 {
1096 snd_soc_unregister_codec(&client->dev);
1097
1098 return 0;
1099 }
1100
1101 static const struct i2c_device_id wm8961_i2c_id[] = {
1102 { "wm8961", 0 },
1103 { }
1104 };
1105 MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
1106
1107 static struct i2c_driver wm8961_i2c_driver = {
1108 .driver = {
1109 .name = "wm8961",
1110 .owner = THIS_MODULE,
1111 },
1112 .probe = wm8961_i2c_probe,
1113 .remove = __devexit_p(wm8961_i2c_remove),
1114 .id_table = wm8961_i2c_id,
1115 };
1116
1117 static int __init wm8961_modinit(void)
1118 {
1119 int ret = 0;
1120 ret = i2c_add_driver(&wm8961_i2c_driver);
1121 if (ret != 0) {
1122 printk(KERN_ERR "Failed to register wm8961 I2C driver: %d\n",
1123 ret);
1124 }
1125 return ret;
1126 }
1127 module_init(wm8961_modinit);
1128
1129 static void __exit wm8961_exit(void)
1130 {
1131 i2c_del_driver(&wm8961_i2c_driver);
1132 }
1133 module_exit(wm8961_exit);
1134
1135 MODULE_DESCRIPTION("ASoC WM8961 driver");
1136 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1137 MODULE_LICENSE("GPL");
Linux with added FPC-III support