Revert "microblaze_mmu_v2: Update signal returning address"
[linux/fpc-iii.git] / sound / soc / tegra / tegra_pcm.c
blob8d6900c1ee47e8d1a263584bf470e5c2eec56af4
1 /*
2 * tegra_pcm.c - Tegra PCM driver
4 * Author: Stephen Warren <swarren@nvidia.com>
5 * Copyright (C) 2010,2012 - NVIDIA, Inc.
7 * Based on code copyright/by:
9 * Copyright (c) 2009-2010, NVIDIA Corporation.
10 * Scott Peterson <speterson@nvidia.com>
11 * Vijay Mali <vmali@nvidia.com>
13 * Copyright (C) 2010 Google, Inc.
14 * Iliyan Malchev <malchev@google.com>
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * version 2 as published by the Free Software Foundation.
20 * This program is distributed in the hope that it will be useful, but
21 * WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
28 * 02110-1301 USA
32 #include <linux/dma-mapping.h>
33 #include <linux/module.h>
34 #include <linux/slab.h>
35 #include <sound/core.h>
36 #include <sound/pcm.h>
37 #include <sound/pcm_params.h>
38 #include <sound/soc.h>
39 #include <sound/dmaengine_pcm.h>
41 #include "tegra_pcm.h"
43 static const struct snd_pcm_hardware tegra_pcm_hardware = {
44 .info = SNDRV_PCM_INFO_MMAP |
45 SNDRV_PCM_INFO_MMAP_VALID |
46 SNDRV_PCM_INFO_PAUSE |
47 SNDRV_PCM_INFO_RESUME |
48 SNDRV_PCM_INFO_INTERLEAVED,
49 .formats = SNDRV_PCM_FMTBIT_S16_LE,
50 .channels_min = 2,
51 .channels_max = 2,
52 .period_bytes_min = 1024,
53 .period_bytes_max = PAGE_SIZE,
54 .periods_min = 2,
55 .periods_max = 8,
56 .buffer_bytes_max = PAGE_SIZE * 8,
57 .fifo_size = 4,
60 #if defined(CONFIG_TEGRA_SYSTEM_DMA)
61 static void tegra_pcm_queue_dma(struct tegra_runtime_data *prtd)
63 struct snd_pcm_substream *substream = prtd->substream;
64 struct snd_dma_buffer *buf = &substream->dma_buffer;
65 struct tegra_dma_req *dma_req;
66 unsigned long addr;
68 dma_req = &prtd->dma_req[prtd->dma_req_idx];
69 prtd->dma_req_idx = 1 - prtd->dma_req_idx;
71 addr = buf->addr + prtd->dma_pos;
72 prtd->dma_pos += dma_req->size;
73 if (prtd->dma_pos >= prtd->dma_pos_end)
74 prtd->dma_pos = 0;
76 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
77 dma_req->source_addr = addr;
78 else
79 dma_req->dest_addr = addr;
81 tegra_dma_enqueue_req(prtd->dma_chan, dma_req);
84 static void dma_complete_callback(struct tegra_dma_req *req)
86 struct tegra_runtime_data *prtd = (struct tegra_runtime_data *)req->dev;
87 struct snd_pcm_substream *substream = prtd->substream;
88 struct snd_pcm_runtime *runtime = substream->runtime;
90 spin_lock(&prtd->lock);
92 if (!prtd->running) {
93 spin_unlock(&prtd->lock);
94 return;
97 if (++prtd->period_index >= runtime->periods)
98 prtd->period_index = 0;
100 tegra_pcm_queue_dma(prtd);
102 spin_unlock(&prtd->lock);
104 snd_pcm_period_elapsed(substream);
107 static void setup_dma_tx_request(struct tegra_dma_req *req,
108 struct tegra_pcm_dma_params * dmap)
110 req->complete = dma_complete_callback;
111 req->to_memory = false;
112 req->dest_addr = dmap->addr;
113 req->dest_wrap = dmap->wrap;
114 req->source_bus_width = 32;
115 req->source_wrap = 0;
116 req->dest_bus_width = dmap->width;
117 req->req_sel = dmap->req_sel;
120 static void setup_dma_rx_request(struct tegra_dma_req *req,
121 struct tegra_pcm_dma_params * dmap)
123 req->complete = dma_complete_callback;
124 req->to_memory = true;
125 req->source_addr = dmap->addr;
126 req->dest_wrap = 0;
127 req->source_bus_width = dmap->width;
128 req->source_wrap = dmap->wrap;
129 req->dest_bus_width = 32;
130 req->req_sel = dmap->req_sel;
133 static int tegra_pcm_open(struct snd_pcm_substream *substream)
135 struct snd_pcm_runtime *runtime = substream->runtime;
136 struct tegra_runtime_data *prtd;
137 struct snd_soc_pcm_runtime *rtd = substream->private_data;
138 struct tegra_pcm_dma_params * dmap;
139 int ret = 0;
141 prtd = kzalloc(sizeof(struct tegra_runtime_data), GFP_KERNEL);
142 if (prtd == NULL)
143 return -ENOMEM;
145 runtime->private_data = prtd;
146 prtd->substream = substream;
148 spin_lock_init(&prtd->lock);
150 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
151 dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
152 setup_dma_tx_request(&prtd->dma_req[0], dmap);
153 setup_dma_tx_request(&prtd->dma_req[1], dmap);
154 } else {
155 dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
156 setup_dma_rx_request(&prtd->dma_req[0], dmap);
157 setup_dma_rx_request(&prtd->dma_req[1], dmap);
160 prtd->dma_req[0].dev = prtd;
161 prtd->dma_req[1].dev = prtd;
163 prtd->dma_chan = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
164 if (prtd->dma_chan == NULL) {
165 ret = -ENOMEM;
166 goto err;
169 /* Set HW params now that initialization is complete */
170 snd_soc_set_runtime_hwparams(substream, &tegra_pcm_hardware);
172 /* Ensure that buffer size is a multiple of period size */
173 ret = snd_pcm_hw_constraint_integer(runtime,
174 SNDRV_PCM_HW_PARAM_PERIODS);
175 if (ret < 0)
176 goto err;
178 return 0;
180 err:
181 if (prtd->dma_chan) {
182 tegra_dma_free_channel(prtd->dma_chan);
185 kfree(prtd);
187 return ret;
190 static int tegra_pcm_close(struct snd_pcm_substream *substream)
192 struct snd_pcm_runtime *runtime = substream->runtime;
193 struct tegra_runtime_data *prtd = runtime->private_data;
195 tegra_dma_free_channel(prtd->dma_chan);
197 kfree(prtd);
199 return 0;
202 static int tegra_pcm_hw_params(struct snd_pcm_substream *substream,
203 struct snd_pcm_hw_params *params)
205 struct snd_pcm_runtime *runtime = substream->runtime;
206 struct tegra_runtime_data *prtd = runtime->private_data;
208 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
210 prtd->dma_req[0].size = params_period_bytes(params);
211 prtd->dma_req[1].size = prtd->dma_req[0].size;
213 return 0;
216 static int tegra_pcm_hw_free(struct snd_pcm_substream *substream)
218 snd_pcm_set_runtime_buffer(substream, NULL);
220 return 0;
223 static int tegra_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
225 struct snd_pcm_runtime *runtime = substream->runtime;
226 struct tegra_runtime_data *prtd = runtime->private_data;
227 unsigned long flags;
229 switch (cmd) {
230 case SNDRV_PCM_TRIGGER_START:
231 prtd->dma_pos = 0;
232 prtd->dma_pos_end = frames_to_bytes(runtime, runtime->periods * runtime->period_size);
233 prtd->period_index = 0;
234 prtd->dma_req_idx = 0;
235 /* Fall-through */
236 case SNDRV_PCM_TRIGGER_RESUME:
237 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
238 spin_lock_irqsave(&prtd->lock, flags);
239 prtd->running = 1;
240 spin_unlock_irqrestore(&prtd->lock, flags);
241 tegra_pcm_queue_dma(prtd);
242 tegra_pcm_queue_dma(prtd);
243 break;
244 case SNDRV_PCM_TRIGGER_STOP:
245 case SNDRV_PCM_TRIGGER_SUSPEND:
246 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
247 spin_lock_irqsave(&prtd->lock, flags);
248 prtd->running = 0;
249 spin_unlock_irqrestore(&prtd->lock, flags);
250 tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req[0]);
251 tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req[1]);
252 break;
253 default:
254 return -EINVAL;
257 return 0;
260 static snd_pcm_uframes_t tegra_pcm_pointer(struct snd_pcm_substream *substream)
262 struct snd_pcm_runtime *runtime = substream->runtime;
263 struct tegra_runtime_data *prtd = runtime->private_data;
265 return prtd->period_index * runtime->period_size;
269 static int tegra_pcm_mmap(struct snd_pcm_substream *substream,
270 struct vm_area_struct *vma)
272 struct snd_pcm_runtime *runtime = substream->runtime;
274 return dma_mmap_writecombine(substream->pcm->card->dev, vma,
275 runtime->dma_area,
276 runtime->dma_addr,
277 runtime->dma_bytes);
280 static struct snd_pcm_ops tegra_pcm_ops = {
281 .open = tegra_pcm_open,
282 .close = tegra_pcm_close,
283 .ioctl = snd_pcm_lib_ioctl,
284 .hw_params = tegra_pcm_hw_params,
285 .hw_free = tegra_pcm_hw_free,
286 .trigger = tegra_pcm_trigger,
287 .pointer = tegra_pcm_pointer,
288 .mmap = tegra_pcm_mmap,
290 #else
291 static int tegra_pcm_open(struct snd_pcm_substream *substream)
293 struct snd_soc_pcm_runtime *rtd = substream->private_data;
294 struct device *dev = rtd->platform->dev;
295 int ret;
297 /* Set HW params now that initialization is complete */
298 snd_soc_set_runtime_hwparams(substream, &tegra_pcm_hardware);
300 ret = snd_dmaengine_pcm_open(substream, NULL, NULL);
301 if (ret) {
302 dev_err(dev, "dmaengine pcm open failed with err %d\n", ret);
303 return ret;
306 return 0;
309 static int tegra_pcm_close(struct snd_pcm_substream *substream)
311 snd_dmaengine_pcm_close(substream);
312 return 0;
315 static int tegra_pcm_hw_params(struct snd_pcm_substream *substream,
316 struct snd_pcm_hw_params *params)
318 struct snd_soc_pcm_runtime *rtd = substream->private_data;
319 struct device *dev = rtd->platform->dev;
320 struct dma_chan *chan = snd_dmaengine_pcm_get_chan(substream);
321 struct tegra_pcm_dma_params *dmap;
322 struct dma_slave_config slave_config;
323 int ret;
325 dmap = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
327 ret = snd_hwparams_to_dma_slave_config(substream, params,
328 &slave_config);
329 if (ret) {
330 dev_err(dev, "hw params config failed with err %d\n", ret);
331 return ret;
334 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
335 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
336 slave_config.dst_addr = dmap->addr;
337 slave_config.dst_maxburst = 4;
338 } else {
339 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
340 slave_config.src_addr = dmap->addr;
341 slave_config.src_maxburst = 4;
343 slave_config.slave_id = dmap->req_sel;
345 ret = dmaengine_slave_config(chan, &slave_config);
346 if (ret < 0) {
347 dev_err(dev, "dma slave config failed with err %d\n", ret);
348 return ret;
351 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
352 return 0;
355 static int tegra_pcm_hw_free(struct snd_pcm_substream *substream)
357 snd_pcm_set_runtime_buffer(substream, NULL);
358 return 0;
361 static int tegra_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
363 switch (cmd) {
364 case SNDRV_PCM_TRIGGER_START:
365 case SNDRV_PCM_TRIGGER_RESUME:
366 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
367 return snd_dmaengine_pcm_trigger(substream,
368 SNDRV_PCM_TRIGGER_START);
370 case SNDRV_PCM_TRIGGER_STOP:
371 case SNDRV_PCM_TRIGGER_SUSPEND:
372 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
373 return snd_dmaengine_pcm_trigger(substream,
374 SNDRV_PCM_TRIGGER_STOP);
375 default:
376 return -EINVAL;
378 return 0;
381 static int tegra_pcm_mmap(struct snd_pcm_substream *substream,
382 struct vm_area_struct *vma)
384 struct snd_pcm_runtime *runtime = substream->runtime;
386 return dma_mmap_writecombine(substream->pcm->card->dev, vma,
387 runtime->dma_area,
388 runtime->dma_addr,
389 runtime->dma_bytes);
392 static struct snd_pcm_ops tegra_pcm_ops = {
393 .open = tegra_pcm_open,
394 .close = tegra_pcm_close,
395 .ioctl = snd_pcm_lib_ioctl,
396 .hw_params = tegra_pcm_hw_params,
397 .hw_free = tegra_pcm_hw_free,
398 .trigger = tegra_pcm_trigger,
399 .pointer = snd_dmaengine_pcm_pointer,
400 .mmap = tegra_pcm_mmap,
402 #endif
404 static int tegra_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
406 struct snd_pcm_substream *substream = pcm->streams[stream].substream;
407 struct snd_dma_buffer *buf = &substream->dma_buffer;
408 size_t size = tegra_pcm_hardware.buffer_bytes_max;
410 buf->area = dma_alloc_writecombine(pcm->card->dev, size,
411 &buf->addr, GFP_KERNEL);
412 if (!buf->area)
413 return -ENOMEM;
415 buf->dev.type = SNDRV_DMA_TYPE_DEV;
416 buf->dev.dev = pcm->card->dev;
417 buf->private_data = NULL;
418 buf->bytes = size;
420 return 0;
423 static void tegra_pcm_deallocate_dma_buffer(struct snd_pcm *pcm, int stream)
425 struct snd_pcm_substream *substream;
426 struct snd_dma_buffer *buf;
428 substream = pcm->streams[stream].substream;
429 if (!substream)
430 return;
432 buf = &substream->dma_buffer;
433 if (!buf->area)
434 return;
436 dma_free_writecombine(pcm->card->dev, buf->bytes,
437 buf->area, buf->addr);
438 buf->area = NULL;
441 static u64 tegra_dma_mask = DMA_BIT_MASK(32);
443 static int tegra_pcm_new(struct snd_soc_pcm_runtime *rtd)
445 struct snd_card *card = rtd->card->snd_card;
446 struct snd_pcm *pcm = rtd->pcm;
447 int ret = 0;
449 if (!card->dev->dma_mask)
450 card->dev->dma_mask = &tegra_dma_mask;
451 if (!card->dev->coherent_dma_mask)
452 card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
454 if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
455 ret = tegra_pcm_preallocate_dma_buffer(pcm,
456 SNDRV_PCM_STREAM_PLAYBACK);
457 if (ret)
458 goto err;
461 if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
462 ret = tegra_pcm_preallocate_dma_buffer(pcm,
463 SNDRV_PCM_STREAM_CAPTURE);
464 if (ret)
465 goto err_free_play;
468 return 0;
470 err_free_play:
471 tegra_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK);
472 err:
473 return ret;
476 static void tegra_pcm_free(struct snd_pcm *pcm)
478 tegra_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_CAPTURE);
479 tegra_pcm_deallocate_dma_buffer(pcm, SNDRV_PCM_STREAM_PLAYBACK);
482 static struct snd_soc_platform_driver tegra_pcm_platform = {
483 .ops = &tegra_pcm_ops,
484 .pcm_new = tegra_pcm_new,
485 .pcm_free = tegra_pcm_free,
488 int __devinit tegra_pcm_platform_register(struct device *dev)
490 return snd_soc_register_platform(dev, &tegra_pcm_platform);
492 EXPORT_SYMBOL_GPL(tegra_pcm_platform_register);
494 void __devexit tegra_pcm_platform_unregister(struct device *dev)
496 snd_soc_unregister_platform(dev);
498 EXPORT_SYMBOL_GPL(tegra_pcm_platform_unregister);
500 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
501 MODULE_DESCRIPTION("Tegra PCM ASoC driver");
502 MODULE_LICENSE("GPL");