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ceph: define 'end/complete' in readdir reply as bit flags
[linux/fpc-iii.git] / sound / pci / ctxfi / cthw20k1.c
blob9667cbfb0ca2b38eae7e76f45f742195631b271e
1 /**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File cthw20k1.c
9 *
10 * @Brief
11 * This file contains the implementation of hardware access methord for 20k1.
12 *
13 * @Author Liu Chun
14 * @Date Jun 24 2008
15 *
16 */
17
18 #include <linux/types.h>
19 #include <linux/slab.h>
20 #include <linux/pci.h>
21 #include <linux/io.h>
22 #include <linux/string.h>
23 #include <linux/spinlock.h>
24 #include <linux/kernel.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include "cthw20k1.h"
28 #include "ct20k1reg.h"
29
30 #if BITS_PER_LONG == 32
31 #define CT_XFI_DMA_MASK DMA_BIT_MASK(32) /* 32 bit PTE */
32 #else
33 #define CT_XFI_DMA_MASK DMA_BIT_MASK(64) /* 64 bit PTE */
34 #endif
35
36 struct hw20k1 {
37 struct hw hw;
38 spinlock_t reg_20k1_lock;
39 spinlock_t reg_pci_lock;
40 };
41
42 static u32 hw_read_20kx(struct hw *hw, u32 reg);
43 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
44 static u32 hw_read_pci(struct hw *hw, u32 reg);
45 static void hw_write_pci(struct hw *hw, u32 reg, u32 data);
46
47 /*
48 * Type definition block.
49 * The layout of control structures can be directly applied on 20k2 chip.
50 */
51
52 /*
53 * SRC control block definitions.
54 */
55
56 /* SRC resource control block */
57 #define SRCCTL_STATE 0x00000007
58 #define SRCCTL_BM 0x00000008
59 #define SRCCTL_RSR 0x00000030
60 #define SRCCTL_SF 0x000001C0
61 #define SRCCTL_WR 0x00000200
62 #define SRCCTL_PM 0x00000400
63 #define SRCCTL_ROM 0x00001800
64 #define SRCCTL_VO 0x00002000
65 #define SRCCTL_ST 0x00004000
66 #define SRCCTL_IE 0x00008000
67 #define SRCCTL_ILSZ 0x000F0000
68 #define SRCCTL_BP 0x00100000
69
70 #define SRCCCR_CISZ 0x000007FF
71 #define SRCCCR_CWA 0x001FF800
72 #define SRCCCR_D 0x00200000
73 #define SRCCCR_RS 0x01C00000
74 #define SRCCCR_NAL 0x3E000000
75 #define SRCCCR_RA 0xC0000000
76
77 #define SRCCA_CA 0x03FFFFFF
78 #define SRCCA_RS 0x1C000000
79 #define SRCCA_NAL 0xE0000000
80
81 #define SRCSA_SA 0x03FFFFFF
82
83 #define SRCLA_LA 0x03FFFFFF
84
85 /* Mixer Parameter Ring ram Low and Hight register.
86 * Fixed-point value in 8.24 format for parameter channel */
87 #define MPRLH_PITCH 0xFFFFFFFF
88
89 /* SRC resource register dirty flags */
90 union src_dirty {
91 struct {
92 u16 ctl:1;
93 u16 ccr:1;
94 u16 sa:1;
95 u16 la:1;
96 u16 ca:1;
97 u16 mpr:1;
98 u16 czbfs:1; /* Clear Z-Buffers */
99 u16 rsv:9;
100 } bf;
101 u16 data;
102 };
103
104 struct src_rsc_ctrl_blk {
105 unsigned int ctl;
106 unsigned int ccr;
107 unsigned int ca;
108 unsigned int sa;
109 unsigned int la;
110 unsigned int mpr;
111 union src_dirty dirty;
112 };
113
114 /* SRC manager control block */
115 union src_mgr_dirty {
116 struct {
117 u16 enb0:1;
118 u16 enb1:1;
119 u16 enb2:1;
120 u16 enb3:1;
121 u16 enb4:1;
122 u16 enb5:1;
123 u16 enb6:1;
124 u16 enb7:1;
125 u16 enbsa:1;
126 u16 rsv:7;
127 } bf;
128 u16 data;
129 };
130
131 struct src_mgr_ctrl_blk {
132 unsigned int enbsa;
133 unsigned int enb[8];
134 union src_mgr_dirty dirty;
135 };
136
137 /* SRCIMP manager control block */
138 #define SRCAIM_ARC 0x00000FFF
139 #define SRCAIM_NXT 0x00FF0000
140 #define SRCAIM_SRC 0xFF000000
141
142 struct srcimap {
143 unsigned int srcaim;
144 unsigned int idx;
145 };
146
147 /* SRCIMP manager register dirty flags */
148 union srcimp_mgr_dirty {
149 struct {
150 u16 srcimap:1;
151 u16 rsv:15;
152 } bf;
153 u16 data;
154 };
155
156 struct srcimp_mgr_ctrl_blk {
157 struct srcimap srcimap;
158 union srcimp_mgr_dirty dirty;
159 };
160
161 /*
162 * Function implementation block.
163 */
164
165 static int src_get_rsc_ctrl_blk(void **rblk)
166 {
167 struct src_rsc_ctrl_blk *blk;
168
169 *rblk = NULL;
170 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
171 if (!blk)
172 return -ENOMEM;
173
174 *rblk = blk;
175
176 return 0;
177 }
178
179 static int src_put_rsc_ctrl_blk(void *blk)
180 {
181 kfree((struct src_rsc_ctrl_blk *)blk);
182
183 return 0;
184 }
185
186 static int src_set_state(void *blk, unsigned int state)
187 {
188 struct src_rsc_ctrl_blk *ctl = blk;
189
190 set_field(&ctl->ctl, SRCCTL_STATE, state);
191 ctl->dirty.bf.ctl = 1;
192 return 0;
193 }
194
195 static int src_set_bm(void *blk, unsigned int bm)
196 {
197 struct src_rsc_ctrl_blk *ctl = blk;
198
199 set_field(&ctl->ctl, SRCCTL_BM, bm);
200 ctl->dirty.bf.ctl = 1;
201 return 0;
202 }
203
204 static int src_set_rsr(void *blk, unsigned int rsr)
205 {
206 struct src_rsc_ctrl_blk *ctl = blk;
207
208 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
209 ctl->dirty.bf.ctl = 1;
210 return 0;
211 }
212
213 static int src_set_sf(void *blk, unsigned int sf)
214 {
215 struct src_rsc_ctrl_blk *ctl = blk;
216
217 set_field(&ctl->ctl, SRCCTL_SF, sf);
218 ctl->dirty.bf.ctl = 1;
219 return 0;
220 }
221
222 static int src_set_wr(void *blk, unsigned int wr)
223 {
224 struct src_rsc_ctrl_blk *ctl = blk;
225
226 set_field(&ctl->ctl, SRCCTL_WR, wr);
227 ctl->dirty.bf.ctl = 1;
228 return 0;
229 }
230
231 static int src_set_pm(void *blk, unsigned int pm)
232 {
233 struct src_rsc_ctrl_blk *ctl = blk;
234
235 set_field(&ctl->ctl, SRCCTL_PM, pm);
236 ctl->dirty.bf.ctl = 1;
237 return 0;
238 }
239
240 static int src_set_rom(void *blk, unsigned int rom)
241 {
242 struct src_rsc_ctrl_blk *ctl = blk;
243
244 set_field(&ctl->ctl, SRCCTL_ROM, rom);
245 ctl->dirty.bf.ctl = 1;
246 return 0;
247 }
248
249 static int src_set_vo(void *blk, unsigned int vo)
250 {
251 struct src_rsc_ctrl_blk *ctl = blk;
252
253 set_field(&ctl->ctl, SRCCTL_VO, vo);
254 ctl->dirty.bf.ctl = 1;
255 return 0;
256 }
257
258 static int src_set_st(void *blk, unsigned int st)
259 {
260 struct src_rsc_ctrl_blk *ctl = blk;
261
262 set_field(&ctl->ctl, SRCCTL_ST, st);
263 ctl->dirty.bf.ctl = 1;
264 return 0;
265 }
266
267 static int src_set_ie(void *blk, unsigned int ie)
268 {
269 struct src_rsc_ctrl_blk *ctl = blk;
270
271 set_field(&ctl->ctl, SRCCTL_IE, ie);
272 ctl->dirty.bf.ctl = 1;
273 return 0;
274 }
275
276 static int src_set_ilsz(void *blk, unsigned int ilsz)
277 {
278 struct src_rsc_ctrl_blk *ctl = blk;
279
280 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
281 ctl->dirty.bf.ctl = 1;
282 return 0;
283 }
284
285 static int src_set_bp(void *blk, unsigned int bp)
286 {
287 struct src_rsc_ctrl_blk *ctl = blk;
288
289 set_field(&ctl->ctl, SRCCTL_BP, bp);
290 ctl->dirty.bf.ctl = 1;
291 return 0;
292 }
293
294 static int src_set_cisz(void *blk, unsigned int cisz)
295 {
296 struct src_rsc_ctrl_blk *ctl = blk;
297
298 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
299 ctl->dirty.bf.ccr = 1;
300 return 0;
301 }
302
303 static int src_set_ca(void *blk, unsigned int ca)
304 {
305 struct src_rsc_ctrl_blk *ctl = blk;
306
307 set_field(&ctl->ca, SRCCA_CA, ca);
308 ctl->dirty.bf.ca = 1;
309 return 0;
310 }
311
312 static int src_set_sa(void *blk, unsigned int sa)
313 {
314 struct src_rsc_ctrl_blk *ctl = blk;
315
316 set_field(&ctl->sa, SRCSA_SA, sa);
317 ctl->dirty.bf.sa = 1;
318 return 0;
319 }
320
321 static int src_set_la(void *blk, unsigned int la)
322 {
323 struct src_rsc_ctrl_blk *ctl = blk;
324
325 set_field(&ctl->la, SRCLA_LA, la);
326 ctl->dirty.bf.la = 1;
327 return 0;
328 }
329
330 static int src_set_pitch(void *blk, unsigned int pitch)
331 {
332 struct src_rsc_ctrl_blk *ctl = blk;
333
334 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
335 ctl->dirty.bf.mpr = 1;
336 return 0;
337 }
338
339 static int src_set_clear_zbufs(void *blk, unsigned int clear)
340 {
341 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
342 return 0;
343 }
344
345 static int src_set_dirty(void *blk, unsigned int flags)
346 {
347 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
348 return 0;
349 }
350
351 static int src_set_dirty_all(void *blk)
352 {
353 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
354 return 0;
355 }
356
357 #define AR_SLOT_SIZE 4096
358 #define AR_SLOT_BLOCK_SIZE 16
359 #define AR_PTS_PITCH 6
360 #define AR_PARAM_SRC_OFFSET 0x60
361
362 static unsigned int src_param_pitch_mixer(unsigned int src_idx)
363 {
364 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
365 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
366
367 }
368
369 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
370 {
371 struct src_rsc_ctrl_blk *ctl = blk;
372 int i;
373
374 if (ctl->dirty.bf.czbfs) {
375 /* Clear Z-Buffer registers */
376 for (i = 0; i < 8; i++)
377 hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0);
378
379 for (i = 0; i < 4; i++)
380 hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0);
381
382 for (i = 0; i < 8; i++)
383 hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0);
384
385 ctl->dirty.bf.czbfs = 0;
386 }
387 if (ctl->dirty.bf.mpr) {
388 /* Take the parameter mixer resource in the same group as that
389 * the idx src is in for simplicity. Unlike src, all conjugate
390 * parameter mixer resources must be programmed for
391 * corresponding conjugate src resources. */
392 unsigned int pm_idx = src_param_pitch_mixer(idx);
393 hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr);
394 hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3);
395 hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0);
396 ctl->dirty.bf.mpr = 0;
397 }
398 if (ctl->dirty.bf.sa) {
399 hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa);
400 ctl->dirty.bf.sa = 0;
401 }
402 if (ctl->dirty.bf.la) {
403 hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la);
404 ctl->dirty.bf.la = 0;
405 }
406 if (ctl->dirty.bf.ca) {
407 hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca);
408 ctl->dirty.bf.ca = 0;
409 }
410
411 /* Write srccf register */
412 hw_write_20kx(hw, SRCCF+idx*0x100, 0x0);
413
414 if (ctl->dirty.bf.ccr) {
415 hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr);
416 ctl->dirty.bf.ccr = 0;
417 }
418 if (ctl->dirty.bf.ctl) {
419 hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl);
420 ctl->dirty.bf.ctl = 0;
421 }
422
423 return 0;
424 }
425
426 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
427 {
428 struct src_rsc_ctrl_blk *ctl = blk;
429
430 ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100);
431 ctl->dirty.bf.ca = 0;
432
433 return get_field(ctl->ca, SRCCA_CA);
434 }
435
436 static unsigned int src_get_dirty(void *blk)
437 {
438 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
439 }
440
441 static unsigned int src_dirty_conj_mask(void)
442 {
443 return 0x20;
444 }
445
446 static int src_mgr_enbs_src(void *blk, unsigned int idx)
447 {
448 ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0);
449 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
450 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
451 return 0;
452 }
453
454 static int src_mgr_enb_src(void *blk, unsigned int idx)
455 {
456 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
457 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
458 return 0;
459 }
460
461 static int src_mgr_dsb_src(void *blk, unsigned int idx)
462 {
463 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
464 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
465 return 0;
466 }
467
468 static int src_mgr_commit_write(struct hw *hw, void *blk)
469 {
470 struct src_mgr_ctrl_blk *ctl = blk;
471 int i;
472 unsigned int ret;
473
474 if (ctl->dirty.bf.enbsa) {
475 do {
476 ret = hw_read_20kx(hw, SRCENBSTAT);
477 } while (ret & 0x1);
478 hw_write_20kx(hw, SRCENBS, ctl->enbsa);
479 ctl->dirty.bf.enbsa = 0;
480 }
481 for (i = 0; i < 8; i++) {
482 if ((ctl->dirty.data & (0x1 << i))) {
483 hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]);
484 ctl->dirty.data &= ~(0x1 << i);
485 }
486 }
487
488 return 0;
489 }
490
491 static int src_mgr_get_ctrl_blk(void **rblk)
492 {
493 struct src_mgr_ctrl_blk *blk;
494
495 *rblk = NULL;
496 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
497 if (!blk)
498 return -ENOMEM;
499
500 *rblk = blk;
501
502 return 0;
503 }
504
505 static int src_mgr_put_ctrl_blk(void *blk)
506 {
507 kfree((struct src_mgr_ctrl_blk *)blk);
508
509 return 0;
510 }
511
512 static int srcimp_mgr_get_ctrl_blk(void **rblk)
513 {
514 struct srcimp_mgr_ctrl_blk *blk;
515
516 *rblk = NULL;
517 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
518 if (!blk)
519 return -ENOMEM;
520
521 *rblk = blk;
522
523 return 0;
524 }
525
526 static int srcimp_mgr_put_ctrl_blk(void *blk)
527 {
528 kfree((struct srcimp_mgr_ctrl_blk *)blk);
529
530 return 0;
531 }
532
533 static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
534 {
535 struct srcimp_mgr_ctrl_blk *ctl = blk;
536
537 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
538 ctl->dirty.bf.srcimap = 1;
539 return 0;
540 }
541
542 static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
543 {
544 struct srcimp_mgr_ctrl_blk *ctl = blk;
545
546 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
547 ctl->dirty.bf.srcimap = 1;
548 return 0;
549 }
550
551 static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
552 {
553 struct srcimp_mgr_ctrl_blk *ctl = blk;
554
555 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
556 ctl->dirty.bf.srcimap = 1;
557 return 0;
558 }
559
560 static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
561 {
562 struct srcimp_mgr_ctrl_blk *ctl = blk;
563
564 ctl->srcimap.idx = addr;
565 ctl->dirty.bf.srcimap = 1;
566 return 0;
567 }
568
569 static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
570 {
571 struct srcimp_mgr_ctrl_blk *ctl = blk;
572
573 if (ctl->dirty.bf.srcimap) {
574 hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100,
575 ctl->srcimap.srcaim);
576 ctl->dirty.bf.srcimap = 0;
577 }
578
579 return 0;
580 }
581
582 /*
583 * AMIXER control block definitions.
584 */
585
586 #define AMOPLO_M 0x00000003
587 #define AMOPLO_X 0x0003FFF0
588 #define AMOPLO_Y 0xFFFC0000
589
590 #define AMOPHI_SADR 0x000000FF
591 #define AMOPHI_SE 0x80000000
592
593 /* AMIXER resource register dirty flags */
594 union amixer_dirty {
595 struct {
596 u16 amoplo:1;
597 u16 amophi:1;
598 u16 rsv:14;
599 } bf;
600 u16 data;
601 };
602
603 /* AMIXER resource control block */
604 struct amixer_rsc_ctrl_blk {
605 unsigned int amoplo;
606 unsigned int amophi;
607 union amixer_dirty dirty;
608 };
609
610 static int amixer_set_mode(void *blk, unsigned int mode)
611 {
612 struct amixer_rsc_ctrl_blk *ctl = blk;
613
614 set_field(&ctl->amoplo, AMOPLO_M, mode);
615 ctl->dirty.bf.amoplo = 1;
616 return 0;
617 }
618
619 static int amixer_set_iv(void *blk, unsigned int iv)
620 {
621 /* 20k1 amixer does not have this field */
622 return 0;
623 }
624
625 static int amixer_set_x(void *blk, unsigned int x)
626 {
627 struct amixer_rsc_ctrl_blk *ctl = blk;
628
629 set_field(&ctl->amoplo, AMOPLO_X, x);
630 ctl->dirty.bf.amoplo = 1;
631 return 0;
632 }
633
634 static int amixer_set_y(void *blk, unsigned int y)
635 {
636 struct amixer_rsc_ctrl_blk *ctl = blk;
637
638 set_field(&ctl->amoplo, AMOPLO_Y, y);
639 ctl->dirty.bf.amoplo = 1;
640 return 0;
641 }
642
643 static int amixer_set_sadr(void *blk, unsigned int sadr)
644 {
645 struct amixer_rsc_ctrl_blk *ctl = blk;
646
647 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
648 ctl->dirty.bf.amophi = 1;
649 return 0;
650 }
651
652 static int amixer_set_se(void *blk, unsigned int se)
653 {
654 struct amixer_rsc_ctrl_blk *ctl = blk;
655
656 set_field(&ctl->amophi, AMOPHI_SE, se);
657 ctl->dirty.bf.amophi = 1;
658 return 0;
659 }
660
661 static int amixer_set_dirty(void *blk, unsigned int flags)
662 {
663 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
664 return 0;
665 }
666
667 static int amixer_set_dirty_all(void *blk)
668 {
669 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
670 return 0;
671 }
672
673 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
674 {
675 struct amixer_rsc_ctrl_blk *ctl = blk;
676
677 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
678 hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo);
679 ctl->dirty.bf.amoplo = 0;
680 hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi);
681 ctl->dirty.bf.amophi = 0;
682 }
683
684 return 0;
685 }
686
687 static int amixer_get_y(void *blk)
688 {
689 struct amixer_rsc_ctrl_blk *ctl = blk;
690
691 return get_field(ctl->amoplo, AMOPLO_Y);
692 }
693
694 static unsigned int amixer_get_dirty(void *blk)
695 {
696 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
697 }
698
699 static int amixer_rsc_get_ctrl_blk(void **rblk)
700 {
701 struct amixer_rsc_ctrl_blk *blk;
702
703 *rblk = NULL;
704 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
705 if (!blk)
706 return -ENOMEM;
707
708 *rblk = blk;
709
710 return 0;
711 }
712
713 static int amixer_rsc_put_ctrl_blk(void *blk)
714 {
715 kfree((struct amixer_rsc_ctrl_blk *)blk);
716
717 return 0;
718 }
719
720 static int amixer_mgr_get_ctrl_blk(void **rblk)
721 {
722 /*amixer_mgr_ctrl_blk_t *blk;*/
723
724 *rblk = NULL;
725 /*blk = kzalloc(sizeof(*blk), GFP_KERNEL);
726 if (!blk)
727 return -ENOMEM;
728
729 *rblk = blk;*/
730
731 return 0;
732 }
733
734 static int amixer_mgr_put_ctrl_blk(void *blk)
735 {
736 /*kfree((amixer_mgr_ctrl_blk_t *)blk);*/
737
738 return 0;
739 }
740
741 /*
742 * DAIO control block definitions.
743 */
744
745 /* Receiver Sample Rate Tracker Control register */
746 #define SRTCTL_SRCR 0x000000FF
747 #define SRTCTL_SRCL 0x0000FF00
748 #define SRTCTL_RSR 0x00030000
749 #define SRTCTL_DRAT 0x000C0000
750 #define SRTCTL_RLE 0x10000000
751 #define SRTCTL_RLP 0x20000000
752 #define SRTCTL_EC 0x40000000
753 #define SRTCTL_ET 0x80000000
754
755 /* DAIO Receiver register dirty flags */
756 union dai_dirty {
757 struct {
758 u16 srtctl:1;
759 u16 rsv:15;
760 } bf;
761 u16 data;
762 };
763
764 /* DAIO Receiver control block */
765 struct dai_ctrl_blk {
766 unsigned int srtctl;
767 union dai_dirty dirty;
768 };
769
770 /* S/PDIF Transmitter register dirty flags */
771 union dao_dirty {
772 struct {
773 u16 spos:1;
774 u16 rsv:15;
775 } bf;
776 u16 data;
777 };
778
779 /* S/PDIF Transmitter control block */
780 struct dao_ctrl_blk {
781 unsigned int spos; /* S/PDIF Output Channel Status Register */
782 union dao_dirty dirty;
783 };
784
785 /* Audio Input Mapper RAM */
786 #define AIM_ARC 0x00000FFF
787 #define AIM_NXT 0x007F0000
788
789 struct daoimap {
790 unsigned int aim;
791 unsigned int idx;
792 };
793
794 /* I2S Transmitter/Receiver Control register */
795 #define I2SCTL_EA 0x00000004
796 #define I2SCTL_EI 0x00000010
797
798 /* S/PDIF Transmitter Control register */
799 #define SPOCTL_OE 0x00000001
800 #define SPOCTL_OS 0x0000000E
801 #define SPOCTL_RIV 0x00000010
802 #define SPOCTL_LIV 0x00000020
803 #define SPOCTL_SR 0x000000C0
804
805 /* S/PDIF Receiver Control register */
806 #define SPICTL_EN 0x00000001
807 #define SPICTL_I24 0x00000002
808 #define SPICTL_IB 0x00000004
809 #define SPICTL_SM 0x00000008
810 #define SPICTL_VM 0x00000010
811
812 /* DAIO manager register dirty flags */
813 union daio_mgr_dirty {
814 struct {
815 u32 i2soctl:4;
816 u32 i2sictl:4;
817 u32 spoctl:4;
818 u32 spictl:4;
819 u32 daoimap:1;
820 u32 rsv:15;
821 } bf;
822 u32 data;
823 };
824
825 /* DAIO manager control block */
826 struct daio_mgr_ctrl_blk {
827 unsigned int i2sctl;
828 unsigned int spoctl;
829 unsigned int spictl;
830 struct daoimap daoimap;
831 union daio_mgr_dirty dirty;
832 };
833
834 static int dai_srt_set_srcr(void *blk, unsigned int src)
835 {
836 struct dai_ctrl_blk *ctl = blk;
837
838 set_field(&ctl->srtctl, SRTCTL_SRCR, src);
839 ctl->dirty.bf.srtctl = 1;
840 return 0;
841 }
842
843 static int dai_srt_set_srcl(void *blk, unsigned int src)
844 {
845 struct dai_ctrl_blk *ctl = blk;
846
847 set_field(&ctl->srtctl, SRTCTL_SRCL, src);
848 ctl->dirty.bf.srtctl = 1;
849 return 0;
850 }
851
852 static int dai_srt_set_rsr(void *blk, unsigned int rsr)
853 {
854 struct dai_ctrl_blk *ctl = blk;
855
856 set_field(&ctl->srtctl, SRTCTL_RSR, rsr);
857 ctl->dirty.bf.srtctl = 1;
858 return 0;
859 }
860
861 static int dai_srt_set_drat(void *blk, unsigned int drat)
862 {
863 struct dai_ctrl_blk *ctl = blk;
864
865 set_field(&ctl->srtctl, SRTCTL_DRAT, drat);
866 ctl->dirty.bf.srtctl = 1;
867 return 0;
868 }
869
870 static int dai_srt_set_ec(void *blk, unsigned int ec)
871 {
872 struct dai_ctrl_blk *ctl = blk;
873
874 set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0);
875 ctl->dirty.bf.srtctl = 1;
876 return 0;
877 }
878
879 static int dai_srt_set_et(void *blk, unsigned int et)
880 {
881 struct dai_ctrl_blk *ctl = blk;
882
883 set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0);
884 ctl->dirty.bf.srtctl = 1;
885 return 0;
886 }
887
888 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
889 {
890 struct dai_ctrl_blk *ctl = blk;
891
892 if (ctl->dirty.bf.srtctl) {
893 if (idx < 4) {
894 /* S/PDIF SRTs */
895 hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl);
896 } else {
897 /* I2S SRT */
898 hw_write_20kx(hw, SRTICTL, ctl->srtctl);
899 }
900 ctl->dirty.bf.srtctl = 0;
901 }
902
903 return 0;
904 }
905
906 static int dai_get_ctrl_blk(void **rblk)
907 {
908 struct dai_ctrl_blk *blk;
909
910 *rblk = NULL;
911 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
912 if (!blk)
913 return -ENOMEM;
914
915 *rblk = blk;
916
917 return 0;
918 }
919
920 static int dai_put_ctrl_blk(void *blk)
921 {
922 kfree((struct dai_ctrl_blk *)blk);
923
924 return 0;
925 }
926
927 static int dao_set_spos(void *blk, unsigned int spos)
928 {
929 ((struct dao_ctrl_blk *)blk)->spos = spos;
930 ((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1;
931 return 0;
932 }
933
934 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
935 {
936 struct dao_ctrl_blk *ctl = blk;
937
938 if (ctl->dirty.bf.spos) {
939 if (idx < 4) {
940 /* S/PDIF SPOSx */
941 hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos);
942 }
943 ctl->dirty.bf.spos = 0;
944 }
945
946 return 0;
947 }
948
949 static int dao_get_spos(void *blk, unsigned int *spos)
950 {
951 *spos = ((struct dao_ctrl_blk *)blk)->spos;
952 return 0;
953 }
954
955 static int dao_get_ctrl_blk(void **rblk)
956 {
957 struct dao_ctrl_blk *blk;
958
959 *rblk = NULL;
960 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
961 if (!blk)
962 return -ENOMEM;
963
964 *rblk = blk;
965
966 return 0;
967 }
968
969 static int dao_put_ctrl_blk(void *blk)
970 {
971 kfree((struct dao_ctrl_blk *)blk);
972
973 return 0;
974 }
975
976 static int daio_mgr_enb_dai(void *blk, unsigned int idx)
977 {
978 struct daio_mgr_ctrl_blk *ctl = blk;
979
980 if (idx < 4) {
981 /* S/PDIF input */
982 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 1);
983 ctl->dirty.bf.spictl |= (0x1 << idx);
984 } else {
985 /* I2S input */
986 idx %= 4;
987 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 1);
988 ctl->dirty.bf.i2sictl |= (0x1 << idx);
989 }
990 return 0;
991 }
992
993 static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
994 {
995 struct daio_mgr_ctrl_blk *ctl = blk;
996
997 if (idx < 4) {
998 /* S/PDIF input */
999 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0);
1000 ctl->dirty.bf.spictl |= (0x1 << idx);
1001 } else {
1002 /* I2S input */
1003 idx %= 4;
1004 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0);
1005 ctl->dirty.bf.i2sictl |= (0x1 << idx);
1006 }
1007 return 0;
1008 }
1009
1010 static int daio_mgr_enb_dao(void *blk, unsigned int idx)
1011 {
1012 struct daio_mgr_ctrl_blk *ctl = blk;
1013
1014 if (idx < 4) {
1015 /* S/PDIF output */
1016 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 1);
1017 ctl->dirty.bf.spoctl |= (0x1 << idx);
1018 } else {
1019 /* I2S output */
1020 idx %= 4;
1021 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 1);
1022 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1023 }
1024 return 0;
1025 }
1026
1027 static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
1028 {
1029 struct daio_mgr_ctrl_blk *ctl = blk;
1030
1031 if (idx < 4) {
1032 /* S/PDIF output */
1033 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0);
1034 ctl->dirty.bf.spoctl |= (0x1 << idx);
1035 } else {
1036 /* I2S output */
1037 idx %= 4;
1038 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0);
1039 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1040 }
1041 return 0;
1042 }
1043
1044 static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
1045 {
1046 struct daio_mgr_ctrl_blk *ctl = blk;
1047
1048 if (idx < 4) {
1049 /* S/PDIF output */
1050 switch ((conf & 0x7)) {
1051 case 0:
1052 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 3);
1053 break; /* CDIF */
1054 case 1:
1055 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0);
1056 break;
1057 case 2:
1058 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 1);
1059 break;
1060 case 4:
1061 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 2);
1062 break;
1063 default:
1064 break;
1065 }
1066 set_field(&ctl->spoctl, SPOCTL_LIV << (idx*8),
1067 (conf >> 4) & 0x1); /* Non-audio */
1068 set_field(&ctl->spoctl, SPOCTL_RIV << (idx*8),
1069 (conf >> 4) & 0x1); /* Non-audio */
1070 set_field(&ctl->spoctl, SPOCTL_OS << (idx*8),
1071 ((conf >> 3) & 0x1) ? 2 : 2); /* Raw */
1072
1073 ctl->dirty.bf.spoctl |= (0x1 << idx);
1074 } else {
1075 /* I2S output */
1076 /*idx %= 4; */
1077 }
1078 return 0;
1079 }
1080
1081 static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1082 {
1083 struct daio_mgr_ctrl_blk *ctl = blk;
1084
1085 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1086 ctl->dirty.bf.daoimap = 1;
1087 return 0;
1088 }
1089
1090 static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1091 {
1092 struct daio_mgr_ctrl_blk *ctl = blk;
1093
1094 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1095 ctl->dirty.bf.daoimap = 1;
1096 return 0;
1097 }
1098
1099 static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1100 {
1101 struct daio_mgr_ctrl_blk *ctl = blk;
1102
1103 ctl->daoimap.idx = addr;
1104 ctl->dirty.bf.daoimap = 1;
1105 return 0;
1106 }
1107
1108 static int daio_mgr_commit_write(struct hw *hw, void *blk)
1109 {
1110 struct daio_mgr_ctrl_blk *ctl = blk;
1111 int i;
1112
1113 if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) {
1114 for (i = 0; i < 4; i++) {
1115 if ((ctl->dirty.bf.i2sictl & (0x1 << i)))
1116 ctl->dirty.bf.i2sictl &= ~(0x1 << i);
1117
1118 if ((ctl->dirty.bf.i2soctl & (0x1 << i)))
1119 ctl->dirty.bf.i2soctl &= ~(0x1 << i);
1120 }
1121 hw_write_20kx(hw, I2SCTL, ctl->i2sctl);
1122 mdelay(1);
1123 }
1124 if (ctl->dirty.bf.spoctl) {
1125 for (i = 0; i < 4; i++) {
1126 if ((ctl->dirty.bf.spoctl & (0x1 << i)))
1127 ctl->dirty.bf.spoctl &= ~(0x1 << i);
1128 }
1129 hw_write_20kx(hw, SPOCTL, ctl->spoctl);
1130 mdelay(1);
1131 }
1132 if (ctl->dirty.bf.spictl) {
1133 for (i = 0; i < 4; i++) {
1134 if ((ctl->dirty.bf.spictl & (0x1 << i)))
1135 ctl->dirty.bf.spictl &= ~(0x1 << i);
1136 }
1137 hw_write_20kx(hw, SPICTL, ctl->spictl);
1138 mdelay(1);
1139 }
1140 if (ctl->dirty.bf.daoimap) {
1141 hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4,
1142 ctl->daoimap.aim);
1143 ctl->dirty.bf.daoimap = 0;
1144 }
1145
1146 return 0;
1147 }
1148
1149 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1150 {
1151 struct daio_mgr_ctrl_blk *blk;
1152
1153 *rblk = NULL;
1154 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1155 if (!blk)
1156 return -ENOMEM;
1157
1158 blk->i2sctl = hw_read_20kx(hw, I2SCTL);
1159 blk->spoctl = hw_read_20kx(hw, SPOCTL);
1160 blk->spictl = hw_read_20kx(hw, SPICTL);
1161
1162 *rblk = blk;
1163
1164 return 0;
1165 }
1166
1167 static int daio_mgr_put_ctrl_blk(void *blk)
1168 {
1169 kfree((struct daio_mgr_ctrl_blk *)blk);
1170
1171 return 0;
1172 }
1173
1174 /* Timer interrupt */
1175 static int set_timer_irq(struct hw *hw, int enable)
1176 {
1177 hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
1178 return 0;
1179 }
1180
1181 static int set_timer_tick(struct hw *hw, unsigned int ticks)
1182 {
1183 if (ticks)
1184 ticks |= TIMR_IE | TIMR_IP;
1185 hw_write_20kx(hw, TIMR, ticks);
1186 return 0;
1187 }
1188
1189 static unsigned int get_wc(struct hw *hw)
1190 {
1191 return hw_read_20kx(hw, WC);
1192 }
1193
1194 /* Card hardware initialization block */
1195 struct dac_conf {
1196 unsigned int msr; /* master sample rate in rsrs */
1197 };
1198
1199 struct adc_conf {
1200 unsigned int msr; /* master sample rate in rsrs */
1201 unsigned char input; /* the input source of ADC */
1202 unsigned char mic20db; /* boost mic by 20db if input is microphone */
1203 };
1204
1205 struct daio_conf {
1206 unsigned int msr; /* master sample rate in rsrs */
1207 };
1208
1209 struct trn_conf {
1210 unsigned long vm_pgt_phys;
1211 };
1212
1213 static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1214 {
1215 u32 i2sorg;
1216 u32 spdorg;
1217
1218 /* Read I2S CTL. Keep original value. */
1219 /*i2sorg = hw_read_20kx(hw, I2SCTL);*/
1220 i2sorg = 0x94040404; /* enable all audio out and I2S-D input */
1221 /* Program I2S with proper master sample rate and enable
1222 * the correct I2S channel. */
1223 i2sorg &= 0xfffffffc;
1224
1225 /* Enable S/PDIF-out-A in fixed 24-bit data
1226 * format and default to 48kHz. */
1227 /* Disable all before doing any changes. */
1228 hw_write_20kx(hw, SPOCTL, 0x0);
1229 spdorg = 0x05;
1230
1231 switch (info->msr) {
1232 case 1:
1233 i2sorg |= 1;
1234 spdorg |= (0x0 << 6);
1235 break;
1236 case 2:
1237 i2sorg |= 2;
1238 spdorg |= (0x1 << 6);
1239 break;
1240 case 4:
1241 i2sorg |= 3;
1242 spdorg |= (0x2 << 6);
1243 break;
1244 default:
1245 i2sorg |= 1;
1246 break;
1247 }
1248
1249 hw_write_20kx(hw, I2SCTL, i2sorg);
1250 hw_write_20kx(hw, SPOCTL, spdorg);
1251
1252 /* Enable S/PDIF-in-A in fixed 24-bit data format. */
1253 /* Disable all before doing any changes. */
1254 hw_write_20kx(hw, SPICTL, 0x0);
1255 mdelay(1);
1256 spdorg = 0x0a0a0a0a;
1257 hw_write_20kx(hw, SPICTL, spdorg);
1258 mdelay(1);
1259
1260 return 0;
1261 }
1262
1263 /* TRANSPORT operations */
1264 static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1265 {
1266 u32 trnctl;
1267 u32 ptp_phys_low, ptp_phys_high;
1268
1269 /* Set up device page table */
1270 if ((~0UL) == info->vm_pgt_phys) {
1271 dev_err(hw->card->dev,
1272 "Wrong device page table page address!\n");
1273 return -1;
1274 }
1275
1276 trnctl = 0x13; /* 32-bit, 4k-size page */
1277 ptp_phys_low = (u32)info->vm_pgt_phys;
1278 ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1279 if (sizeof(void *) == 8) /* 64bit address */
1280 trnctl |= (1 << 2);
1281 #if 0 /* Only 4k h/w pages for simplicitiy */
1282 #if PAGE_SIZE == 8192
1283 trnctl |= (1<<5);
1284 #endif
1285 #endif
1286 hw_write_20kx(hw, PTPALX, ptp_phys_low);
1287 hw_write_20kx(hw, PTPAHX, ptp_phys_high);
1288 hw_write_20kx(hw, TRNCTL, trnctl);
1289 hw_write_20kx(hw, TRNIS, 0x200c01); /* really needed? */
1290
1291 return 0;
1292 }
1293
1294 /* Card initialization */
1295 #define GCTL_EAC 0x00000001
1296 #define GCTL_EAI 0x00000002
1297 #define GCTL_BEP 0x00000004
1298 #define GCTL_BES 0x00000008
1299 #define GCTL_DSP 0x00000010
1300 #define GCTL_DBP 0x00000020
1301 #define GCTL_ABP 0x00000040
1302 #define GCTL_TBP 0x00000080
1303 #define GCTL_SBP 0x00000100
1304 #define GCTL_FBP 0x00000200
1305 #define GCTL_XA 0x00000400
1306 #define GCTL_ET 0x00000800
1307 #define GCTL_PR 0x00001000
1308 #define GCTL_MRL 0x00002000
1309 #define GCTL_SDE 0x00004000
1310 #define GCTL_SDI 0x00008000
1311 #define GCTL_SM 0x00010000
1312 #define GCTL_SR 0x00020000
1313 #define GCTL_SD 0x00040000
1314 #define GCTL_SE 0x00080000
1315 #define GCTL_AID 0x00100000
1316
1317 static int hw_pll_init(struct hw *hw, unsigned int rsr)
1318 {
1319 unsigned int pllctl;
1320 int i;
1321
1322 pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731;
1323 for (i = 0; i < 3; i++) {
1324 if (hw_read_20kx(hw, PLLCTL) == pllctl)
1325 break;
1326
1327 hw_write_20kx(hw, PLLCTL, pllctl);
1328 mdelay(40);
1329 }
1330 if (i >= 3) {
1331 dev_alert(hw->card->dev, "PLL initialization failed!!!\n");
1332 return -EBUSY;
1333 }
1334
1335 return 0;
1336 }
1337
1338 static int hw_auto_init(struct hw *hw)
1339 {
1340 unsigned int gctl;
1341 int i;
1342
1343 gctl = hw_read_20kx(hw, GCTL);
1344 set_field(&gctl, GCTL_EAI, 0);
1345 hw_write_20kx(hw, GCTL, gctl);
1346 set_field(&gctl, GCTL_EAI, 1);
1347 hw_write_20kx(hw, GCTL, gctl);
1348 mdelay(10);
1349 for (i = 0; i < 400000; i++) {
1350 gctl = hw_read_20kx(hw, GCTL);
1351 if (get_field(gctl, GCTL_AID))
1352 break;
1353 }
1354 if (!get_field(gctl, GCTL_AID)) {
1355 dev_alert(hw->card->dev, "Card Auto-init failed!!!\n");
1356 return -EBUSY;
1357 }
1358
1359 return 0;
1360 }
1361
1362 static int i2c_unlock(struct hw *hw)
1363 {
1364 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1365 return 0;
1366
1367 hw_write_pci(hw, 0xcc, 0x8c);
1368 hw_write_pci(hw, 0xcc, 0x0e);
1369 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1370 return 0;
1371
1372 hw_write_pci(hw, 0xcc, 0xee);
1373 hw_write_pci(hw, 0xcc, 0xaa);
1374 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1375 return 0;
1376
1377 return -1;
1378 }
1379
1380 static void i2c_lock(struct hw *hw)
1381 {
1382 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1383 hw_write_pci(hw, 0xcc, 0x00);
1384 }
1385
1386 static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data)
1387 {
1388 unsigned int ret;
1389
1390 do {
1391 ret = hw_read_pci(hw, 0xEC);
1392 } while (!(ret & 0x800000));
1393 hw_write_pci(hw, 0xE0, device);
1394 hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff));
1395 }
1396
1397 /* DAC operations */
1398
1399 static int hw_reset_dac(struct hw *hw)
1400 {
1401 u32 i;
1402 u16 gpioorg;
1403 unsigned int ret;
1404
1405 if (i2c_unlock(hw))
1406 return -1;
1407
1408 do {
1409 ret = hw_read_pci(hw, 0xEC);
1410 } while (!(ret & 0x800000));
1411 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1412
1413 /* To be effective, need to reset the DAC twice. */
1414 for (i = 0; i < 2; i++) {
1415 /* set gpio */
1416 mdelay(100);
1417 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1418 gpioorg &= 0xfffd;
1419 hw_write_20kx(hw, GPIO, gpioorg);
1420 mdelay(1);
1421 hw_write_20kx(hw, GPIO, gpioorg | 0x2);
1422 }
1423
1424 i2c_write(hw, 0x00180080, 0x01, 0x80);
1425 i2c_write(hw, 0x00180080, 0x02, 0x10);
1426
1427 i2c_lock(hw);
1428
1429 return 0;
1430 }
1431
1432 static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1433 {
1434 u32 data;
1435 u16 gpioorg;
1436 unsigned int ret;
1437
1438 if (hw->model == CTSB055X) {
1439 /* SB055x, unmute outputs */
1440 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1441 gpioorg &= 0xffbf; /* set GPIO6 to low */
1442 gpioorg |= 2; /* set GPIO1 to high */
1443 hw_write_20kx(hw, GPIO, gpioorg);
1444 return 0;
1445 }
1446
1447 /* mute outputs */
1448 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1449 gpioorg &= 0xffbf;
1450 hw_write_20kx(hw, GPIO, gpioorg);
1451
1452 hw_reset_dac(hw);
1453
1454 if (i2c_unlock(hw))
1455 return -1;
1456
1457 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1458 do {
1459 ret = hw_read_pci(hw, 0xEC);
1460 } while (!(ret & 0x800000));
1461
1462 switch (info->msr) {
1463 case 1:
1464 data = 0x24;
1465 break;
1466 case 2:
1467 data = 0x25;
1468 break;
1469 case 4:
1470 data = 0x26;
1471 break;
1472 default:
1473 data = 0x24;
1474 break;
1475 }
1476
1477 i2c_write(hw, 0x00180080, 0x06, data);
1478 i2c_write(hw, 0x00180080, 0x09, data);
1479 i2c_write(hw, 0x00180080, 0x0c, data);
1480 i2c_write(hw, 0x00180080, 0x0f, data);
1481
1482 i2c_lock(hw);
1483
1484 /* unmute outputs */
1485 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1486 gpioorg = gpioorg | 0x40;
1487 hw_write_20kx(hw, GPIO, gpioorg);
1488
1489 return 0;
1490 }
1491
1492 /* ADC operations */
1493
1494 static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type)
1495 {
1496 return 0;
1497 }
1498
1499 static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type)
1500 {
1501 u32 data;
1502
1503 data = hw_read_20kx(hw, GPIO);
1504 switch (type) {
1505 case ADC_MICIN:
1506 data = ((data & (0x1<<7)) && (data & (0x1<<8)));
1507 break;
1508 case ADC_LINEIN:
1509 data = (!(data & (0x1<<7)) && (data & (0x1<<8)));
1510 break;
1511 case ADC_NONE: /* Digital I/O */
1512 data = (!(data & (0x1<<8)));
1513 break;
1514 default:
1515 data = 0;
1516 }
1517 return data;
1518 }
1519
1520 static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type)
1521 {
1522 u32 data;
1523
1524 data = hw_read_20kx(hw, GPIO);
1525 switch (type) {
1526 case ADC_MICIN:
1527 data = (data & (0x1 << 7)) ? 1 : 0;
1528 break;
1529 case ADC_LINEIN:
1530 data = (data & (0x1 << 7)) ? 0 : 1;
1531 break;
1532 default:
1533 data = 0;
1534 }
1535 return data;
1536 }
1537
1538 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1539 {
1540 switch (hw->model) {
1541 case CTSB055X:
1542 return is_adc_input_selected_SB055x(hw, type);
1543 case CTSB073X:
1544 return is_adc_input_selected_hendrix(hw, type);
1545 case CTUAA:
1546 return is_adc_input_selected_hendrix(hw, type);
1547 default:
1548 return is_adc_input_selected_SBx(hw, type);
1549 }
1550 }
1551
1552 static int
1553 adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost)
1554 {
1555 u32 data;
1556
1557 /*
1558 * check and set the following GPIO bits accordingly
1559 * ADC_Gain = GPIO2
1560 * DRM_off = GPIO3
1561 * Mic_Pwr_on = GPIO7
1562 * Digital_IO_Sel = GPIO8
1563 * Mic_Sw = GPIO9
1564 * Aux/MicLine_Sw = GPIO12
1565 */
1566 data = hw_read_20kx(hw, GPIO);
1567 data &= 0xec73;
1568 switch (type) {
1569 case ADC_MICIN:
1570 data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ;
1571 data |= boost ? (0x1<<2) : 0;
1572 break;
1573 case ADC_LINEIN:
1574 data |= (0x1<<8);
1575 break;
1576 case ADC_AUX:
1577 data |= (0x1<<8) | (0x1<<12);
1578 break;
1579 case ADC_NONE:
1580 data |= (0x1<<12); /* set to digital */
1581 break;
1582 default:
1583 return -1;
1584 }
1585
1586 hw_write_20kx(hw, GPIO, data);
1587
1588 return 0;
1589 }
1590
1591
1592 static int
1593 adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost)
1594 {
1595 u32 data;
1596 u32 i2c_data;
1597 unsigned int ret;
1598
1599 if (i2c_unlock(hw))
1600 return -1;
1601
1602 do {
1603 ret = hw_read_pci(hw, 0xEC);
1604 } while (!(ret & 0x800000)); /* i2c ready poll */
1605 /* set i2c access mode as Direct Control */
1606 hw_write_pci(hw, 0xEC, 0x05);
1607
1608 data = hw_read_20kx(hw, GPIO);
1609 switch (type) {
1610 case ADC_MICIN:
1611 data |= ((0x1 << 7) | (0x1 << 8));
1612 i2c_data = 0x1; /* Mic-in */
1613 break;
1614 case ADC_LINEIN:
1615 data &= ~(0x1 << 7);
1616 data |= (0x1 << 8);
1617 i2c_data = 0x2; /* Line-in */
1618 break;
1619 case ADC_NONE:
1620 data &= ~(0x1 << 8);
1621 i2c_data = 0x0; /* set to Digital */
1622 break;
1623 default:
1624 i2c_lock(hw);
1625 return -1;
1626 }
1627 hw_write_20kx(hw, GPIO, data);
1628 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1629 if (boost) {
1630 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1631 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1632 } else {
1633 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1634 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1635 }
1636
1637 i2c_lock(hw);
1638
1639 return 0;
1640 }
1641
1642 static int
1643 adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost)
1644 {
1645 u32 data;
1646 u32 i2c_data;
1647 unsigned int ret;
1648
1649 if (i2c_unlock(hw))
1650 return -1;
1651
1652 do {
1653 ret = hw_read_pci(hw, 0xEC);
1654 } while (!(ret & 0x800000)); /* i2c ready poll */
1655 /* set i2c access mode as Direct Control */
1656 hw_write_pci(hw, 0xEC, 0x05);
1657
1658 data = hw_read_20kx(hw, GPIO);
1659 switch (type) {
1660 case ADC_MICIN:
1661 data |= (0x1 << 7);
1662 i2c_data = 0x1; /* Mic-in */
1663 break;
1664 case ADC_LINEIN:
1665 data &= ~(0x1 << 7);
1666 i2c_data = 0x2; /* Line-in */
1667 break;
1668 default:
1669 i2c_lock(hw);
1670 return -1;
1671 }
1672 hw_write_20kx(hw, GPIO, data);
1673 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1674 if (boost) {
1675 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1676 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1677 } else {
1678 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1679 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1680 }
1681
1682 i2c_lock(hw);
1683
1684 return 0;
1685 }
1686
1687 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1688 {
1689 int state = type == ADC_MICIN;
1690
1691 switch (hw->model) {
1692 case CTSB055X:
1693 return adc_input_select_SB055x(hw, type, state);
1694 case CTSB073X:
1695 return adc_input_select_hendrix(hw, type, state);
1696 case CTUAA:
1697 return adc_input_select_hendrix(hw, type, state);
1698 default:
1699 return adc_input_select_SBx(hw, type, state);
1700 }
1701 }
1702
1703 static int adc_init_SB055x(struct hw *hw, int input, int mic20db)
1704 {
1705 return adc_input_select_SB055x(hw, input, mic20db);
1706 }
1707
1708 static int adc_init_SBx(struct hw *hw, int input, int mic20db)
1709 {
1710 u16 gpioorg;
1711 u16 input_source;
1712 u32 adcdata;
1713 unsigned int ret;
1714
1715 input_source = 0x100; /* default to analog */
1716 switch (input) {
1717 case ADC_MICIN:
1718 adcdata = 0x1;
1719 input_source = 0x180; /* set GPIO7 to select Mic */
1720 break;
1721 case ADC_LINEIN:
1722 adcdata = 0x2;
1723 break;
1724 case ADC_VIDEO:
1725 adcdata = 0x4;
1726 break;
1727 case ADC_AUX:
1728 adcdata = 0x8;
1729 break;
1730 case ADC_NONE:
1731 adcdata = 0x0;
1732 input_source = 0x0; /* set to Digital */
1733 break;
1734 default:
1735 adcdata = 0x0;
1736 break;
1737 }
1738
1739 if (i2c_unlock(hw))
1740 return -1;
1741
1742 do {
1743 ret = hw_read_pci(hw, 0xEC);
1744 } while (!(ret & 0x800000)); /* i2c ready poll */
1745 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1746
1747 i2c_write(hw, 0x001a0080, 0x0e, 0x08);
1748 i2c_write(hw, 0x001a0080, 0x18, 0x0a);
1749 i2c_write(hw, 0x001a0080, 0x28, 0x86);
1750 i2c_write(hw, 0x001a0080, 0x2a, adcdata);
1751
1752 if (mic20db) {
1753 i2c_write(hw, 0x001a0080, 0x1c, 0xf7);
1754 i2c_write(hw, 0x001a0080, 0x1e, 0xf7);
1755 } else {
1756 i2c_write(hw, 0x001a0080, 0x1c, 0xcf);
1757 i2c_write(hw, 0x001a0080, 0x1e, 0xcf);
1758 }
1759
1760 if (!(hw_read_20kx(hw, ID0) & 0x100))
1761 i2c_write(hw, 0x001a0080, 0x16, 0x26);
1762
1763 i2c_lock(hw);
1764
1765 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1766 gpioorg &= 0xfe7f;
1767 gpioorg |= input_source;
1768 hw_write_20kx(hw, GPIO, gpioorg);
1769
1770 return 0;
1771 }
1772
1773 static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1774 {
1775 if (hw->model == CTSB055X)
1776 return adc_init_SB055x(hw, info->input, info->mic20db);
1777 else
1778 return adc_init_SBx(hw, info->input, info->mic20db);
1779 }
1780
1781 static struct capabilities hw_capabilities(struct hw *hw)
1782 {
1783 struct capabilities cap;
1784
1785 /* SB073x and Vista compatible cards have no digit IO switch */
1786 cap.digit_io_switch = !(hw->model == CTSB073X || hw->model == CTUAA);
1787 cap.dedicated_mic = 0;
1788 cap.output_switch = 0;
1789 cap.mic_source_switch = 0;
1790
1791 return cap;
1792 }
1793
1794 #define CTLBITS(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
1795
1796 #define UAA_CFG_PWRSTATUS 0x44
1797 #define UAA_CFG_SPACE_FLAG 0xA0
1798 #define UAA_CORE_CHANGE 0x3FFC
1799 static int uaa_to_xfi(struct pci_dev *pci)
1800 {
1801 unsigned int bar0, bar1, bar2, bar3, bar4, bar5;
1802 unsigned int cmd, irq, cl_size, l_timer, pwr;
1803 unsigned int is_uaa;
1804 unsigned int data[4] = {0};
1805 unsigned int io_base;
1806 void __iomem *mem_base;
1807 int i;
1808 const u32 CTLX = CTLBITS('C', 'T', 'L', 'X');
1809 const u32 CTL_ = CTLBITS('C', 'T', 'L', '-');
1810 const u32 CTLF = CTLBITS('C', 'T', 'L', 'F');
1811 const u32 CTLi = CTLBITS('C', 'T', 'L', 'i');
1812 const u32 CTLA = CTLBITS('C', 'T', 'L', 'A');
1813 const u32 CTLZ = CTLBITS('C', 'T', 'L', 'Z');
1814 const u32 CTLL = CTLBITS('C', 'T', 'L', 'L');
1815
1816 /* By default, Hendrix card UAA Bar0 should be using memory... */
1817 io_base = pci_resource_start(pci, 0);
1818 mem_base = ioremap(io_base, pci_resource_len(pci, 0));
1819 if (!mem_base)
1820 return -ENOENT;
1821
1822 /* Read current mode from Mode Change Register */
1823 for (i = 0; i < 4; i++)
1824 data[i] = readl(mem_base + UAA_CORE_CHANGE);
1825
1826 /* Determine current mode... */
1827 if (data[0] == CTLA) {
1828 is_uaa = ((data[1] == CTLZ && data[2] == CTLL
1829 && data[3] == CTLA) || (data[1] == CTLA
1830 && data[2] == CTLZ && data[3] == CTLL));
1831 } else if (data[0] == CTLZ) {
1832 is_uaa = (data[1] == CTLL
1833 && data[2] == CTLA && data[3] == CTLA);
1834 } else if (data[0] == CTLL) {
1835 is_uaa = (data[1] == CTLA
1836 && data[2] == CTLA && data[3] == CTLZ);
1837 } else {
1838 is_uaa = 0;
1839 }
1840
1841 if (!is_uaa) {
1842 /* Not in UAA mode currently. Return directly. */
1843 iounmap(mem_base);
1844 return 0;
1845 }
1846
1847 pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0);
1848 pci_read_config_dword(pci, PCI_BASE_ADDRESS_1, &bar1);
1849 pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2);
1850 pci_read_config_dword(pci, PCI_BASE_ADDRESS_3, &bar3);
1851 pci_read_config_dword(pci, PCI_BASE_ADDRESS_4, &bar4);
1852 pci_read_config_dword(pci, PCI_BASE_ADDRESS_5, &bar5);
1853 pci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq);
1854 pci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size);
1855 pci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer);
1856 pci_read_config_dword(pci, UAA_CFG_PWRSTATUS, &pwr);
1857 pci_read_config_dword(pci, PCI_COMMAND, &cmd);
1858
1859 /* Set up X-Fi core PCI configuration space. */
1860 /* Switch to X-Fi config space with BAR0 exposed. */
1861 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321);
1862 /* Copy UAA's BAR5 into X-Fi BAR0 */
1863 pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5);
1864 /* Switch to X-Fi config space without BAR0 exposed. */
1865 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678);
1866 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, bar1);
1867 pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2);
1868 pci_write_config_dword(pci, PCI_BASE_ADDRESS_3, bar3);
1869 pci_write_config_dword(pci, PCI_BASE_ADDRESS_4, bar4);
1870 pci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq);
1871 pci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size);
1872 pci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer);
1873 pci_write_config_dword(pci, UAA_CFG_PWRSTATUS, pwr);
1874 pci_write_config_dword(pci, PCI_COMMAND, cmd);
1875
1876 /* Switch to X-Fi mode */
1877 writel(CTLX, (mem_base + UAA_CORE_CHANGE));
1878 writel(CTL_, (mem_base + UAA_CORE_CHANGE));
1879 writel(CTLF, (mem_base + UAA_CORE_CHANGE));
1880 writel(CTLi, (mem_base + UAA_CORE_CHANGE));
1881
1882 iounmap(mem_base);
1883
1884 return 0;
1885 }
1886
1887 static irqreturn_t ct_20k1_interrupt(int irq, void *dev_id)
1888 {
1889 struct hw *hw = dev_id;
1890 unsigned int status;
1891
1892 status = hw_read_20kx(hw, GIP);
1893 if (!status)
1894 return IRQ_NONE;
1895
1896 if (hw->irq_callback)
1897 hw->irq_callback(hw->irq_callback_data, status);
1898
1899 hw_write_20kx(hw, GIP, status);
1900 return IRQ_HANDLED;
1901 }
1902
1903 static int hw_card_start(struct hw *hw)
1904 {
1905 int err;
1906 struct pci_dev *pci = hw->pci;
1907
1908 err = pci_enable_device(pci);
1909 if (err < 0)
1910 return err;
1911
1912 /* Set DMA transfer mask */
1913 if (dma_set_mask(&pci->dev, CT_XFI_DMA_MASK) < 0 ||
1914 dma_set_coherent_mask(&pci->dev, CT_XFI_DMA_MASK) < 0) {
1915 dev_err(hw->card->dev,
1916 "architecture does not support PCI busmaster DMA with mask 0x%llx\n",
1917 CT_XFI_DMA_MASK);
1918 err = -ENXIO;
1919 goto error1;
1920 }
1921
1922 if (!hw->io_base) {
1923 err = pci_request_regions(pci, "XFi");
1924 if (err < 0)
1925 goto error1;
1926
1927 if (hw->model == CTUAA)
1928 hw->io_base = pci_resource_start(pci, 5);
1929 else
1930 hw->io_base = pci_resource_start(pci, 0);
1931
1932 }
1933
1934 /* Switch to X-Fi mode from UAA mode if neeeded */
1935 if (hw->model == CTUAA) {
1936 err = uaa_to_xfi(pci);
1937 if (err)
1938 goto error2;
1939
1940 }
1941
1942 if (hw->irq < 0) {
1943 err = request_irq(pci->irq, ct_20k1_interrupt, IRQF_SHARED,
1944 KBUILD_MODNAME, hw);
1945 if (err < 0) {
1946 dev_err(hw->card->dev,
1947 "XFi: Cannot get irq %d\n", pci->irq);
1948 goto error2;
1949 }
1950 hw->irq = pci->irq;
1951 }
1952
1953 pci_set_master(pci);
1954
1955 return 0;
1956
1957 error2:
1958 pci_release_regions(pci);
1959 hw->io_base = 0;
1960 error1:
1961 pci_disable_device(pci);
1962 return err;
1963 }
1964
1965 static int hw_card_stop(struct hw *hw)
1966 {
1967 unsigned int data;
1968
1969 /* disable transport bus master and queueing of request */
1970 hw_write_20kx(hw, TRNCTL, 0x00);
1971
1972 /* disable pll */
1973 data = hw_read_20kx(hw, PLLCTL);
1974 hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12))));
1975
1976 /* TODO: Disable interrupt and so on... */
1977 if (hw->irq >= 0)
1978 synchronize_irq(hw->irq);
1979 return 0;
1980 }
1981
1982 static int hw_card_shutdown(struct hw *hw)
1983 {
1984 if (hw->irq >= 0)
1985 free_irq(hw->irq, hw);
1986
1987 hw->irq = -1;
1988 iounmap(hw->mem_base);
1989 hw->mem_base = NULL;
1990
1991 if (hw->io_base)
1992 pci_release_regions(hw->pci);
1993
1994 hw->io_base = 0;
1995
1996 pci_disable_device(hw->pci);
1997
1998 return 0;
1999 }
2000
2001 static int hw_card_init(struct hw *hw, struct card_conf *info)
2002 {
2003 int err;
2004 unsigned int gctl;
2005 u32 data;
2006 struct dac_conf dac_info = {0};
2007 struct adc_conf adc_info = {0};
2008 struct daio_conf daio_info = {0};
2009 struct trn_conf trn_info = {0};
2010
2011 /* Get PCI io port base address and do Hendrix switch if needed. */
2012 err = hw_card_start(hw);
2013 if (err)
2014 return err;
2015
2016 /* PLL init */
2017 err = hw_pll_init(hw, info->rsr);
2018 if (err < 0)
2019 return err;
2020
2021 /* kick off auto-init */
2022 err = hw_auto_init(hw);
2023 if (err < 0)
2024 return err;
2025
2026 /* Enable audio ring */
2027 gctl = hw_read_20kx(hw, GCTL);
2028 set_field(&gctl, GCTL_EAC, 1);
2029 set_field(&gctl, GCTL_DBP, 1);
2030 set_field(&gctl, GCTL_TBP, 1);
2031 set_field(&gctl, GCTL_FBP, 1);
2032 set_field(&gctl, GCTL_ET, 1);
2033 hw_write_20kx(hw, GCTL, gctl);
2034 mdelay(10);
2035
2036 /* Reset all global pending interrupts */
2037 hw_write_20kx(hw, GIE, 0);
2038 /* Reset all SRC pending interrupts */
2039 hw_write_20kx(hw, SRCIP, 0);
2040 mdelay(30);
2041
2042 /* Detect the card ID and configure GPIO accordingly. */
2043 switch (hw->model) {
2044 case CTSB055X:
2045 hw_write_20kx(hw, GPIOCTL, 0x13fe);
2046 break;
2047 case CTSB073X:
2048 hw_write_20kx(hw, GPIOCTL, 0x00e6);
2049 break;
2050 case CTUAA:
2051 hw_write_20kx(hw, GPIOCTL, 0x00c2);
2052 break;
2053 default:
2054 hw_write_20kx(hw, GPIOCTL, 0x01e6);
2055 break;
2056 }
2057
2058 trn_info.vm_pgt_phys = info->vm_pgt_phys;
2059 err = hw_trn_init(hw, &trn_info);
2060 if (err < 0)
2061 return err;
2062
2063 daio_info.msr = info->msr;
2064 err = hw_daio_init(hw, &daio_info);
2065 if (err < 0)
2066 return err;
2067
2068 dac_info.msr = info->msr;
2069 err = hw_dac_init(hw, &dac_info);
2070 if (err < 0)
2071 return err;
2072
2073 adc_info.msr = info->msr;
2074 adc_info.input = ADC_LINEIN;
2075 adc_info.mic20db = 0;
2076 err = hw_adc_init(hw, &adc_info);
2077 if (err < 0)
2078 return err;
2079
2080 data = hw_read_20kx(hw, SRCMCTL);
2081 data |= 0x1; /* Enables input from the audio ring */
2082 hw_write_20kx(hw, SRCMCTL, data);
2083
2084 return 0;
2085 }
2086
2087 #ifdef CONFIG_PM_SLEEP
2088 static int hw_suspend(struct hw *hw)
2089 {
2090 struct pci_dev *pci = hw->pci;
2091
2092 hw_card_stop(hw);
2093
2094 if (hw->model == CTUAA) {
2095 /* Switch to UAA config space. */
2096 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x0);
2097 }
2098
2099 return 0;
2100 }
2101
2102 static int hw_resume(struct hw *hw, struct card_conf *info)
2103 {
2104 /* Re-initialize card hardware. */
2105 return hw_card_init(hw, info);
2106 }
2107 #endif
2108
2109 static u32 hw_read_20kx(struct hw *hw, u32 reg)
2110 {
2111 u32 value;
2112 unsigned long flags;
2113
2114 spin_lock_irqsave(
2115 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2116 outl(reg, hw->io_base + 0x0);
2117 value = inl(hw->io_base + 0x4);
2118 spin_unlock_irqrestore(
2119 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2120
2121 return value;
2122 }
2123
2124 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2125 {
2126 unsigned long flags;
2127
2128 spin_lock_irqsave(
2129 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2130 outl(reg, hw->io_base + 0x0);
2131 outl(data, hw->io_base + 0x4);
2132 spin_unlock_irqrestore(
2133 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2134
2135 }
2136
2137 static u32 hw_read_pci(struct hw *hw, u32 reg)
2138 {
2139 u32 value;
2140 unsigned long flags;
2141
2142 spin_lock_irqsave(
2143 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2144 outl(reg, hw->io_base + 0x10);
2145 value = inl(hw->io_base + 0x14);
2146 spin_unlock_irqrestore(
2147 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2148
2149 return value;
2150 }
2151
2152 static void hw_write_pci(struct hw *hw, u32 reg, u32 data)
2153 {
2154 unsigned long flags;
2155
2156 spin_lock_irqsave(
2157 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2158 outl(reg, hw->io_base + 0x10);
2159 outl(data, hw->io_base + 0x14);
2160 spin_unlock_irqrestore(
2161 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2162 }
2163
2164 static struct hw ct20k1_preset = {
2165 .irq = -1,
2166
2167 .card_init = hw_card_init,
2168 .card_stop = hw_card_stop,
2169 .pll_init = hw_pll_init,
2170 .is_adc_source_selected = hw_is_adc_input_selected,
2171 .select_adc_source = hw_adc_input_select,
2172 .capabilities = hw_capabilities,
2173 #ifdef CONFIG_PM_SLEEP
2174 .suspend = hw_suspend,
2175 .resume = hw_resume,
2176 #endif
2177
2178 .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
2179 .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
2180 .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
2181 .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
2182 .src_set_state = src_set_state,
2183 .src_set_bm = src_set_bm,
2184 .src_set_rsr = src_set_rsr,
2185 .src_set_sf = src_set_sf,
2186 .src_set_wr = src_set_wr,
2187 .src_set_pm = src_set_pm,
2188 .src_set_rom = src_set_rom,
2189 .src_set_vo = src_set_vo,
2190 .src_set_st = src_set_st,
2191 .src_set_ie = src_set_ie,
2192 .src_set_ilsz = src_set_ilsz,
2193 .src_set_bp = src_set_bp,
2194 .src_set_cisz = src_set_cisz,
2195 .src_set_ca = src_set_ca,
2196 .src_set_sa = src_set_sa,
2197 .src_set_la = src_set_la,
2198 .src_set_pitch = src_set_pitch,
2199 .src_set_dirty = src_set_dirty,
2200 .src_set_clear_zbufs = src_set_clear_zbufs,
2201 .src_set_dirty_all = src_set_dirty_all,
2202 .src_commit_write = src_commit_write,
2203 .src_get_ca = src_get_ca,
2204 .src_get_dirty = src_get_dirty,
2205 .src_dirty_conj_mask = src_dirty_conj_mask,
2206 .src_mgr_enbs_src = src_mgr_enbs_src,
2207 .src_mgr_enb_src = src_mgr_enb_src,
2208 .src_mgr_dsb_src = src_mgr_dsb_src,
2209 .src_mgr_commit_write = src_mgr_commit_write,
2210
2211 .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
2212 .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
2213 .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
2214 .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
2215 .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
2216 .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
2217 .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
2218
2219 .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
2220 .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
2221 .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
2222 .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
2223 .amixer_set_mode = amixer_set_mode,
2224 .amixer_set_iv = amixer_set_iv,
2225 .amixer_set_x = amixer_set_x,
2226 .amixer_set_y = amixer_set_y,
2227 .amixer_set_sadr = amixer_set_sadr,
2228 .amixer_set_se = amixer_set_se,
2229 .amixer_set_dirty = amixer_set_dirty,
2230 .amixer_set_dirty_all = amixer_set_dirty_all,
2231 .amixer_commit_write = amixer_commit_write,
2232 .amixer_get_y = amixer_get_y,
2233 .amixer_get_dirty = amixer_get_dirty,
2234
2235 .dai_get_ctrl_blk = dai_get_ctrl_blk,
2236 .dai_put_ctrl_blk = dai_put_ctrl_blk,
2237 .dai_srt_set_srco = dai_srt_set_srcr,
2238 .dai_srt_set_srcm = dai_srt_set_srcl,
2239 .dai_srt_set_rsr = dai_srt_set_rsr,
2240 .dai_srt_set_drat = dai_srt_set_drat,
2241 .dai_srt_set_ec = dai_srt_set_ec,
2242 .dai_srt_set_et = dai_srt_set_et,
2243 .dai_commit_write = dai_commit_write,
2244
2245 .dao_get_ctrl_blk = dao_get_ctrl_blk,
2246 .dao_put_ctrl_blk = dao_put_ctrl_blk,
2247 .dao_set_spos = dao_set_spos,
2248 .dao_commit_write = dao_commit_write,
2249 .dao_get_spos = dao_get_spos,
2250
2251 .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
2252 .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
2253 .daio_mgr_enb_dai = daio_mgr_enb_dai,
2254 .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
2255 .daio_mgr_enb_dao = daio_mgr_enb_dao,
2256 .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
2257 .daio_mgr_dao_init = daio_mgr_dao_init,
2258 .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
2259 .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
2260 .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
2261 .daio_mgr_commit_write = daio_mgr_commit_write,
2262
2263 .set_timer_irq = set_timer_irq,
2264 .set_timer_tick = set_timer_tick,
2265 .get_wc = get_wc,
2266 };
2267
2268 int create_20k1_hw_obj(struct hw **rhw)
2269 {
2270 struct hw20k1 *hw20k1;
2271
2272 *rhw = NULL;
2273 hw20k1 = kzalloc(sizeof(*hw20k1), GFP_KERNEL);
2274 if (!hw20k1)
2275 return -ENOMEM;
2276
2277 spin_lock_init(&hw20k1->reg_20k1_lock);
2278 spin_lock_init(&hw20k1->reg_pci_lock);
2279
2280 hw20k1->hw = ct20k1_preset;
2281
2282 *rhw = &hw20k1->hw;
2283
2284 return 0;
2285 }
2286
2287 int destroy_20k1_hw_obj(struct hw *hw)
2288 {
2289 if (hw->io_base)
2290 hw_card_shutdown(hw);
2291
2292 kfree(container_of(hw, struct hw20k1, hw));
2293 return 0;
2294 }
Linux with added FPC-III support