| blob | 2dd85273976fcf4aa29e6066ad0975cd4de3582b |
1 /*
2 * linux/arch/arm/mm/proc-xscale.S
3 *
4 * Author: Nicolas Pitre
5 * Created: November 2000
6 * Copyright: (C) 2000, 2001 MontaVista Software Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * MMU functions for the Intel XScale CPUs
13 *
14 * 2001 Aug 21:
15 * some contributions by Brett Gaines <brett.w.gaines@intel.com>
16 * Copyright 2001 by Intel Corp.
17 *
18 * 2001 Sep 08:
19 * Completely revisited, many important fixes
20 * Nicolas Pitre <nico@cam.org>
21 */
23 #include <linux/linkage.h>
24 #include <linux/init.h>
25 #include <asm/assembler.h>
26 #include <asm/elf.h>
27 #include <asm/pgtable.h>
28 #include <asm/pgtable-hwdef.h>
29 #include <asm/page.h>
30 #include <asm/ptrace.h>
31 #include "proc-macros.S"
33 /*
34 * This is the maximum size of an area which will be flushed. If the area
35 * is larger than this, then we flush the whole cache
36 */
37 #define MAX_AREA_SIZE 32768
39 /*
40 * the cache line size of the I and D cache
41 */
42 #define CACHELINESIZE 32
44 /*
45 * the size of the data cache
46 */
47 #define CACHESIZE 32768
49 /*
50 * Virtual address used to allocate the cache when flushed
51 *
52 * This must be an address range which is _never_ used. It should
53 * apparently have a mapping in the corresponding page table for
54 * compatibility with future CPUs that _could_ require it. For instance we
55 * don't care.
56 *
57 * This must be aligned on a 2*CACHESIZE boundary. The code selects one of
58 * the 2 areas in alternance each time the clean_d_cache macro is used.
59 * Without this the XScale core exhibits cache eviction problems and no one
60 * knows why.
61 *
62 * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
63 */
64 #define CLEAN_ADDR 0xfffe0000
66 /*
67 * This macro is used to wait for a CP15 write and is needed
68 * when we have to ensure that the last operation to the co-pro
69 * was completed before continuing with operation.
70 */
71 .macro cpwait, rd
72 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
73 mov \rd, \rd @ wait for completion
74 sub pc, pc, #4 @ flush instruction pipeline
75 .endm
77 .macro cpwait_ret, lr, rd
78 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
79 sub pc, \lr, \rd, LSR #32 @ wait for completion and
80 @ flush instruction pipeline
81 .endm
83 /*
84 * This macro cleans the entire dcache using line allocate.
85 * The main loop has been unrolled to reduce loop overhead.
86 * rd and rs are two scratch registers.
87 */
88 .macro clean_d_cache, rd, rs
89 ldr \rs, =clean_addr
90 ldr \rd, [\rs]
91 eor \rd, \rd, #CACHESIZE
92 str \rd, [\rs]
93 add \rs, \rd, #CACHESIZE
94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
95 add \rd, \rd, #CACHELINESIZE
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
97 add \rd, \rd, #CACHELINESIZE
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
99 add \rd, \rd, #CACHELINESIZE
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
101 add \rd, \rd, #CACHELINESIZE
102 teq \rd, \rs
103 bne 1b
104 .endm
106 .data
107 clean_addr: .word CLEAN_ADDR
109 .text
111 /*
112 * cpu_xscale_proc_init()
113 *
114 * Nothing too exciting at the moment
115 */
116 ENTRY(cpu_xscale_proc_init)
117 @ enable write buffer coalescing. Some bootloader disable it
118 mrc p15, 0, r1, c1, c0, 1
119 bic r1, r1, #1
120 mcr p15, 0, r1, c1, c0, 1
121 mov pc, lr
123 /*
124 * cpu_xscale_proc_fin()
125 */
126 ENTRY(cpu_xscale_proc_fin)
127 str lr, [sp, #-4]!
128 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
129 msr cpsr_c, r0
130 bl xscale_flush_kern_cache_all @ clean caches
131 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
132 bic r0, r0, #0x1800 @ ...IZ...........
133 bic r0, r0, #0x0006 @ .............CA.
134 mcr p15, 0, r0, c1, c0, 0 @ disable caches
135 ldr pc, [sp], #4
137 /*
138 * cpu_xscale_reset(loc)
139 *
140 * Perform a soft reset of the system. Put the CPU into the
141 * same state as it would be if it had been reset, and branch
142 * to what would be the reset vector.
143 *
144 * loc: location to jump to for soft reset
145 *
146 * Beware PXA270 erratum E7.
147 */
148 .align 5
149 ENTRY(cpu_xscale_reset)
150 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
151 msr cpsr_c, r1 @ reset CPSR
152 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
153 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
154 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
155 bic r1, r1, #0x0086 @ ........B....CA.
156 bic r1, r1, #0x3900 @ ..VIZ..S........
157 sub pc, pc, #4 @ flush pipeline
158 @ *** cache line aligned ***
159 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
160 bic r1, r1, #0x0001 @ ...............M
161 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
162 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
163 @ CAUTION: MMU turned off from this point. We count on the pipeline
164 @ already containing those two last instructions to survive.
165 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
166 mov pc, r0
168 /*
169 * cpu_xscale_do_idle()
170 *
171 * Cause the processor to idle
172 *
173 * For now we do nothing but go to idle mode for every case
174 *
175 * XScale supports clock switching, but using idle mode support
176 * allows external hardware to react to system state changes.
177 */
178 .align 5
180 ENTRY(cpu_xscale_do_idle)
181 mov r0, #1
182 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
183 mov pc, lr
185 /* ================================= CACHE ================================ */
187 /*
188 * flush_user_cache_all()
189 *
190 * Invalidate all cache entries in a particular address
191 * space.
192 */
193 ENTRY(xscale_flush_user_cache_all)
194 /* FALLTHROUGH */
196 /*
197 * flush_kern_cache_all()
198 *
199 * Clean and invalidate the entire cache.
200 */
201 ENTRY(xscale_flush_kern_cache_all)
202 mov r2, #VM_EXEC
203 mov ip, #0
204 __flush_whole_cache:
205 clean_d_cache r0, r1
206 tst r2, #VM_EXEC
207 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
208 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
209 mov pc, lr
211 /*
212 * flush_user_cache_range(start, end, vm_flags)
213 *
214 * Invalidate a range of cache entries in the specified
215 * address space.
216 *
217 * - start - start address (may not be aligned)
218 * - end - end address (exclusive, may not be aligned)
219 * - vma - vma_area_struct describing address space
220 */
221 .align 5
222 ENTRY(xscale_flush_user_cache_range)
223 mov ip, #0
224 sub r3, r1, r0 @ calculate total size
225 cmp r3, #MAX_AREA_SIZE
226 bhs __flush_whole_cache
228 1: tst r2, #VM_EXEC
229 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
230 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
231 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
232 add r0, r0, #CACHELINESIZE
233 cmp r0, r1
234 blo 1b
235 tst r2, #VM_EXEC
236 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
237 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
238 mov pc, lr
240 /*
241 * coherent_kern_range(start, end)
242 *
243 * Ensure coherency between the Icache and the Dcache in the
244 * region described by start. If you have non-snooping
245 * Harvard caches, you need to implement this function.
246 *
247 * - start - virtual start address
248 * - end - virtual end address
249 *
250 * Note: single I-cache line invalidation isn't used here since
251 * it also trashes the mini I-cache used by JTAG debuggers.
252 */
253 ENTRY(xscale_coherent_kern_range)
254 bic r0, r0, #CACHELINESIZE - 1
255 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
256 add r0, r0, #CACHELINESIZE
257 cmp r0, r1
258 blo 1b
259 mov r0, #0
260 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
261 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
262 mov pc, lr
264 /*
265 * coherent_user_range(start, end)
266 *
267 * Ensure coherency between the Icache and the Dcache in the
268 * region described by start. If you have non-snooping
269 * Harvard caches, you need to implement this function.
270 *
271 * - start - virtual start address
272 * - end - virtual end address
273 */
274 ENTRY(xscale_coherent_user_range)
275 bic r0, r0, #CACHELINESIZE - 1
276 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
277 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
278 add r0, r0, #CACHELINESIZE
279 cmp r0, r1
280 blo 1b
281 mov r0, #0
282 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
283 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
284 mov pc, lr
286 /*
287 * flush_kern_dcache_page(void *page)
288 *
289 * Ensure no D cache aliasing occurs, either with itself or
290 * the I cache
291 *
292 * - addr - page aligned address
293 */
294 ENTRY(xscale_flush_kern_dcache_page)
295 add r1, r0, #PAGE_SZ
296 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
297 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
298 add r0, r0, #CACHELINESIZE
299 cmp r0, r1
300 blo 1b
301 mov r0, #0
302 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
303 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
304 mov pc, lr
306 /*
307 * dma_inv_range(start, end)
308 *
309 * Invalidate (discard) the specified virtual address range.
310 * May not write back any entries. If 'start' or 'end'
311 * are not cache line aligned, those lines must be written
312 * back.
313 *
314 * - start - virtual start address
315 * - end - virtual end address
316 */
317 ENTRY(xscale_dma_inv_range)
318 tst r0, #CACHELINESIZE - 1
319 bic r0, r0, #CACHELINESIZE - 1
320 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
321 tst r1, #CACHELINESIZE - 1
322 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
323 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
324 add r0, r0, #CACHELINESIZE
325 cmp r0, r1
326 blo 1b
327 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
328 mov pc, lr
330 /*
331 * dma_clean_range(start, end)
332 *
333 * Clean the specified virtual address range.
334 *
335 * - start - virtual start address
336 * - end - virtual end address
337 */
338 ENTRY(xscale_dma_clean_range)
339 bic r0, r0, #CACHELINESIZE - 1
340 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
341 add r0, r0, #CACHELINESIZE
342 cmp r0, r1
343 blo 1b
344 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
345 mov pc, lr
347 /*
348 * dma_flush_range(start, end)
349 *
350 * Clean and invalidate the specified virtual address range.
351 *
352 * - start - virtual start address
353 * - end - virtual end address
354 */
355 ENTRY(xscale_dma_flush_range)
356 bic r0, r0, #CACHELINESIZE - 1
357 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
358 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
359 add r0, r0, #CACHELINESIZE
360 cmp r0, r1
361 blo 1b
362 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
363 mov pc, lr
365 ENTRY(xscale_cache_fns)
366 .long xscale_flush_kern_cache_all
367 .long xscale_flush_user_cache_all
368 .long xscale_flush_user_cache_range
369 .long xscale_coherent_kern_range
370 .long xscale_coherent_user_range
371 .long xscale_flush_kern_dcache_page
372 .long xscale_dma_inv_range
373 .long xscale_dma_clean_range
374 .long xscale_dma_flush_range
376 /*
377 * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
378 * clear the dirty bits, which means that if we invalidate a dirty line,
379 * the dirty data can still be written back to external memory later on.
380 *
381 * The recommended workaround is to always do a clean D-cache line before
382 * doing an invalidate D-cache line, so on the affected processors,
383 * dma_inv_range() is implemented as dma_flush_range().
384 *
385 * See erratum #25 of "Intel 80200 Processor Specification Update",
386 * revision January 22, 2003, available at:
387 * http://www.intel.com/design/iio/specupdt/273415.htm
388 */
389 ENTRY(xscale_80200_A0_A1_cache_fns)
390 .long xscale_flush_kern_cache_all
391 .long xscale_flush_user_cache_all
392 .long xscale_flush_user_cache_range
393 .long xscale_coherent_kern_range
394 .long xscale_coherent_user_range
395 .long xscale_flush_kern_dcache_page
396 .long xscale_dma_flush_range
397 .long xscale_dma_clean_range
398 .long xscale_dma_flush_range
400 ENTRY(cpu_xscale_dcache_clean_area)
401 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
402 add r0, r0, #CACHELINESIZE
403 subs r1, r1, #CACHELINESIZE
404 bhi 1b
405 mov pc, lr
407 /* =============================== PageTable ============================== */
409 #define PTE_CACHE_WRITE_ALLOCATE 0
411 /*
412 * cpu_xscale_switch_mm(pgd)
413 *
414 * Set the translation base pointer to be as described by pgd.
415 *
416 * pgd: new page tables
417 */
418 .align 5
419 ENTRY(cpu_xscale_switch_mm)
420 clean_d_cache r1, r2
421 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
422 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
423 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
424 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
425 cpwait_ret lr, ip
427 /*
428 * cpu_xscale_set_pte_ext(ptep, pte, ext)
429 *
430 * Set a PTE and flush it out
431 *
432 * Errata 40: must set memory to write-through for user read-only pages.
433 */
434 .align 5
435 ENTRY(cpu_xscale_set_pte_ext)
436 str r1, [r0], #-2048 @ linux version
438 bic r2, r1, #0xff0
439 orr r2, r2, #PTE_TYPE_EXT @ extended page
441 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
443 tst r3, #L_PTE_USER @ User?
444 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
446 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
447 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
448 @ combined with user -> user r/w
450 @
451 @ Handle the X bit. We want to set this bit for the minicache
452 @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
453 @ and we have a writeable, cacheable region. If we ignore the
454 @ U and E bits, we can allow user space to use the minicache as
455 @ well.
456 @
457 @ X = (C & ~W & ~B) | (C & W & B & write_allocate)
458 @
459 eor ip, r1, #L_PTE_CACHEABLE
460 tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
461 #if PTE_CACHE_WRITE_ALLOCATE
462 eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
463 tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
464 #endif
465 orreq r2, r2, #PTE_EXT_TEX(1)
467 @
468 @ Erratum 40: The B bit must be cleared for a user read-only
469 @ cacheable page.
470 @
471 @ B = B & ~(U & C & ~W)
472 @
473 and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
474 teq ip, #L_PTE_USER | L_PTE_CACHEABLE
475 biceq r2, r2, #PTE_BUFFERABLE
477 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
478 movne r2, #0 @ no -> fault
480 str r2, [r0] @ hardware version
481 mov ip, #0
482 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
483 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
484 mov pc, lr
487 .ltorg
489 .align
491 __INIT
493 .type __xscale_setup, #function
494 __xscale_setup:
495 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
496 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
497 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
498 mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
499 orr r0, r0, #1 << 13 @ Its undefined whether this
500 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
502 adr r5, xscale_crval
503 ldmia r5, {r5, r6}
504 mrc p15, 0, r0, c1, c0, 0 @ get control register
505 bic r0, r0, r5
506 orr r0, r0, r6
507 mov pc, lr
508 .size __xscale_setup, . - __xscale_setup
510 /*
511 * R
512 * .RVI ZFRS BLDP WCAM
513 * ..11 1.01 .... .101
514 *
515 */
516 .type xscale_crval, #object
517 xscale_crval:
518 crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
520 __INITDATA
522 /*
523 * Purpose : Function pointers used to access above functions - all calls
524 * come through these
525 */
527 .type xscale_processor_functions, #object
528 ENTRY(xscale_processor_functions)
529 .word v5t_early_abort
530 .word pabort_noifar
531 .word cpu_xscale_proc_init
532 .word cpu_xscale_proc_fin
533 .word cpu_xscale_reset
534 .word cpu_xscale_do_idle
535 .word cpu_xscale_dcache_clean_area
536 .word cpu_xscale_switch_mm
537 .word cpu_xscale_set_pte_ext
538 .size xscale_processor_functions, . - xscale_processor_functions
540 .section ".rodata"
542 .type cpu_arch_name, #object
543 cpu_arch_name:
544 .asciz "armv5te"
545 .size cpu_arch_name, . - cpu_arch_name
547 .type cpu_elf_name, #object
548 cpu_elf_name:
549 .asciz "v5"
550 .size cpu_elf_name, . - cpu_elf_name
552 .type cpu_80200_A0_A1_name, #object
553 cpu_80200_A0_A1_name:
554 .asciz "XScale-80200 A0/A1"
555 .size cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name
557 .type cpu_80200_name, #object
558 cpu_80200_name:
559 .asciz "XScale-80200"
560 .size cpu_80200_name, . - cpu_80200_name
562 .type cpu_80219_name, #object
563 cpu_80219_name:
564 .asciz "XScale-80219"
565 .size cpu_80219_name, . - cpu_80219_name
567 .type cpu_8032x_name, #object
568 cpu_8032x_name:
569 .asciz "XScale-IOP8032x Family"
570 .size cpu_8032x_name, . - cpu_8032x_name
572 .type cpu_8033x_name, #object
573 cpu_8033x_name:
574 .asciz "XScale-IOP8033x Family"
575 .size cpu_8033x_name, . - cpu_8033x_name
577 .type cpu_pxa250_name, #object
578 cpu_pxa250_name:
579 .asciz "XScale-PXA250"
580 .size cpu_pxa250_name, . - cpu_pxa250_name
582 .type cpu_pxa210_name, #object
583 cpu_pxa210_name:
584 .asciz "XScale-PXA210"
585 .size cpu_pxa210_name, . - cpu_pxa210_name
587 .type cpu_ixp42x_name, #object
588 cpu_ixp42x_name:
589 .asciz "XScale-IXP42x Family"
590 .size cpu_ixp42x_name, . - cpu_ixp42x_name
592 .type cpu_ixp43x_name, #object
593 cpu_ixp43x_name:
594 .asciz "XScale-IXP43x Family"
595 .size cpu_ixp43x_name, . - cpu_ixp43x_name
597 .type cpu_ixp46x_name, #object
598 cpu_ixp46x_name:
599 .asciz "XScale-IXP46x Family"
600 .size cpu_ixp46x_name, . - cpu_ixp46x_name
602 .type cpu_ixp2400_name, #object
603 cpu_ixp2400_name:
604 .asciz "XScale-IXP2400"
605 .size cpu_ixp2400_name, . - cpu_ixp2400_name
607 .type cpu_ixp2800_name, #object
608 cpu_ixp2800_name:
609 .asciz "XScale-IXP2800"
610 .size cpu_ixp2800_name, . - cpu_ixp2800_name
612 .type cpu_pxa255_name, #object
613 cpu_pxa255_name:
614 .asciz "XScale-PXA255"
615 .size cpu_pxa255_name, . - cpu_pxa255_name
617 .type cpu_pxa270_name, #object
618 cpu_pxa270_name:
619 .asciz "XScale-PXA270"
620 .size cpu_pxa270_name, . - cpu_pxa270_name
622 .align
624 .section ".proc.info.init", #alloc, #execinstr
626 .type __80200_A0_A1_proc_info,#object
627 __80200_A0_A1_proc_info:
628 .long 0x69052000
629 .long 0xfffffffe
630 .long PMD_TYPE_SECT | \
631 PMD_SECT_BUFFERABLE | \
632 PMD_SECT_CACHEABLE | \
633 PMD_SECT_AP_WRITE | \
634 PMD_SECT_AP_READ
635 .long PMD_TYPE_SECT | \
636 PMD_SECT_AP_WRITE | \
637 PMD_SECT_AP_READ
638 b __xscale_setup
639 .long cpu_arch_name
640 .long cpu_elf_name
641 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
642 .long cpu_80200_name
643 .long xscale_processor_functions
644 .long v4wbi_tlb_fns
645 .long xscale_mc_user_fns
646 .long xscale_80200_A0_A1_cache_fns
647 .size __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info
649 .type __80200_proc_info,#object
650 __80200_proc_info:
651 .long 0x69052000
652 .long 0xfffffff0
653 .long PMD_TYPE_SECT | \
654 PMD_SECT_BUFFERABLE | \
655 PMD_SECT_CACHEABLE | \
656 PMD_SECT_AP_WRITE | \
657 PMD_SECT_AP_READ
658 .long PMD_TYPE_SECT | \
659 PMD_SECT_AP_WRITE | \
660 PMD_SECT_AP_READ
661 b __xscale_setup
662 .long cpu_arch_name
663 .long cpu_elf_name
664 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
665 .long cpu_80200_name
666 .long xscale_processor_functions
667 .long v4wbi_tlb_fns
668 .long xscale_mc_user_fns
669 .long xscale_cache_fns
670 .size __80200_proc_info, . - __80200_proc_info
672 .type __80219_proc_info,#object
673 __80219_proc_info:
674 .long 0x69052e20
675 .long 0xffffffe0
676 .long PMD_TYPE_SECT | \
677 PMD_SECT_BUFFERABLE | \
678 PMD_SECT_CACHEABLE | \
679 PMD_SECT_AP_WRITE | \
680 PMD_SECT_AP_READ
681 .long PMD_TYPE_SECT | \
682 PMD_SECT_AP_WRITE | \
683 PMD_SECT_AP_READ
684 b __xscale_setup
685 .long cpu_arch_name
686 .long cpu_elf_name
687 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
688 .long cpu_80219_name
689 .long xscale_processor_functions
690 .long v4wbi_tlb_fns
691 .long xscale_mc_user_fns
692 .long xscale_cache_fns
693 .size __80219_proc_info, . - __80219_proc_info
695 .type __8032x_proc_info,#object
696 __8032x_proc_info:
697 .long 0x69052420
698 .long 0xfffff7e0
699 .long PMD_TYPE_SECT | \
700 PMD_SECT_BUFFERABLE | \
701 PMD_SECT_CACHEABLE | \
702 PMD_SECT_AP_WRITE | \
703 PMD_SECT_AP_READ
704 .long PMD_TYPE_SECT | \
705 PMD_SECT_AP_WRITE | \
706 PMD_SECT_AP_READ
707 b __xscale_setup
708 .long cpu_arch_name
709 .long cpu_elf_name
710 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
711 .long cpu_8032x_name
712 .long xscale_processor_functions
713 .long v4wbi_tlb_fns
714 .long xscale_mc_user_fns
715 .long xscale_cache_fns
716 .size __8032x_proc_info, . - __8032x_proc_info
718 .type __8033x_proc_info,#object
719 __8033x_proc_info:
720 .long 0x69054010
721 .long 0xfffffd30
722 .long PMD_TYPE_SECT | \
723 PMD_SECT_BUFFERABLE | \
724 PMD_SECT_CACHEABLE | \
725 PMD_SECT_AP_WRITE | \
726 PMD_SECT_AP_READ
727 .long PMD_TYPE_SECT | \
728 PMD_SECT_AP_WRITE | \
729 PMD_SECT_AP_READ
730 b __xscale_setup
731 .long cpu_arch_name
732 .long cpu_elf_name
733 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
734 .long cpu_8033x_name
735 .long xscale_processor_functions
736 .long v4wbi_tlb_fns
737 .long xscale_mc_user_fns
738 .long xscale_cache_fns
739 .size __8033x_proc_info, . - __8033x_proc_info
741 .type __pxa250_proc_info,#object
742 __pxa250_proc_info:
743 .long 0x69052100
744 .long 0xfffff7f0
745 .long PMD_TYPE_SECT | \
746 PMD_SECT_BUFFERABLE | \
747 PMD_SECT_CACHEABLE | \
748 PMD_SECT_AP_WRITE | \
749 PMD_SECT_AP_READ
750 .long PMD_TYPE_SECT | \
751 PMD_SECT_AP_WRITE | \
752 PMD_SECT_AP_READ
753 b __xscale_setup
754 .long cpu_arch_name
755 .long cpu_elf_name
756 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
757 .long cpu_pxa250_name
758 .long xscale_processor_functions
759 .long v4wbi_tlb_fns
760 .long xscale_mc_user_fns
761 .long xscale_cache_fns
762 .size __pxa250_proc_info, . - __pxa250_proc_info
764 .type __pxa210_proc_info,#object
765 __pxa210_proc_info:
766 .long 0x69052120
767 .long 0xfffff3f0
768 .long PMD_TYPE_SECT | \
769 PMD_SECT_BUFFERABLE | \
770 PMD_SECT_CACHEABLE | \
771 PMD_SECT_AP_WRITE | \
772 PMD_SECT_AP_READ
773 .long PMD_TYPE_SECT | \
774 PMD_SECT_AP_WRITE | \
775 PMD_SECT_AP_READ
776 b __xscale_setup
777 .long cpu_arch_name
778 .long cpu_elf_name
779 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
780 .long cpu_pxa210_name
781 .long xscale_processor_functions
782 .long v4wbi_tlb_fns
783 .long xscale_mc_user_fns
784 .long xscale_cache_fns
785 .size __pxa210_proc_info, . - __pxa210_proc_info
787 .type __ixp2400_proc_info, #object
788 __ixp2400_proc_info:
789 .long 0x69054190
790 .long 0xfffffff0
791 .long PMD_TYPE_SECT | \
792 PMD_SECT_BUFFERABLE | \
793 PMD_SECT_CACHEABLE | \
794 PMD_SECT_AP_WRITE | \
795 PMD_SECT_AP_READ
796 .long PMD_TYPE_SECT | \
797 PMD_SECT_AP_WRITE | \
798 PMD_SECT_AP_READ
799 b __xscale_setup
800 .long cpu_arch_name
801 .long cpu_elf_name
802 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
803 .long cpu_ixp2400_name
804 .long xscale_processor_functions
805 .long v4wbi_tlb_fns
806 .long xscale_mc_user_fns
807 .long xscale_cache_fns
808 .size __ixp2400_proc_info, . - __ixp2400_proc_info
810 .type __ixp2800_proc_info, #object
811 __ixp2800_proc_info:
812 .long 0x690541a0
813 .long 0xfffffff0
814 .long PMD_TYPE_SECT | \
815 PMD_SECT_BUFFERABLE | \
816 PMD_SECT_CACHEABLE | \
817 PMD_SECT_AP_WRITE | \
818 PMD_SECT_AP_READ
819 .long PMD_TYPE_SECT | \
820 PMD_SECT_AP_WRITE | \
821 PMD_SECT_AP_READ
822 b __xscale_setup
823 .long cpu_arch_name
824 .long cpu_elf_name
825 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
826 .long cpu_ixp2800_name
827 .long xscale_processor_functions
828 .long v4wbi_tlb_fns
829 .long xscale_mc_user_fns
830 .long xscale_cache_fns
831 .size __ixp2800_proc_info, . - __ixp2800_proc_info
833 .type __ixp42x_proc_info, #object
834 __ixp42x_proc_info:
835 .long 0x690541c0
836 .long 0xffffffc0
837 .long PMD_TYPE_SECT | \
838 PMD_SECT_BUFFERABLE | \
839 PMD_SECT_CACHEABLE | \
840 PMD_SECT_AP_WRITE | \
841 PMD_SECT_AP_READ
842 .long PMD_TYPE_SECT | \
843 PMD_SECT_AP_WRITE | \
844 PMD_SECT_AP_READ
845 b __xscale_setup
846 .long cpu_arch_name
847 .long cpu_elf_name
848 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
849 .long cpu_ixp42x_name
850 .long xscale_processor_functions
851 .long v4wbi_tlb_fns
852 .long xscale_mc_user_fns
853 .long xscale_cache_fns
854 .size __ixp42x_proc_info, . - __ixp42x_proc_info
856 .type __ixp43x_proc_info, #object
857 __ixp43x_proc_info:
858 .long 0x69054040
859 .long 0xfffffff0
860 .long PMD_TYPE_SECT | \
861 PMD_SECT_BUFFERABLE | \
862 PMD_SECT_CACHEABLE | \
863 PMD_SECT_AP_WRITE | \
864 PMD_SECT_AP_READ
865 .long PMD_TYPE_SECT | \
866 PMD_SECT_AP_WRITE | \
867 PMD_SECT_AP_READ
868 b __xscale_setup
869 .long cpu_arch_name
870 .long cpu_elf_name
871 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
872 .long cpu_ixp43x_name
873 .long xscale_processor_functions
874 .long v4wbi_tlb_fns
875 .long xscale_mc_user_fns
876 .long xscale_cache_fns
877 .size __ixp43x_proc_info, . - __ixp43x_proc_info
879 .type __ixp46x_proc_info, #object
880 __ixp46x_proc_info:
881 .long 0x69054200
882 .long 0xffffff00
883 .long PMD_TYPE_SECT | \
884 PMD_SECT_BUFFERABLE | \
885 PMD_SECT_CACHEABLE | \
886 PMD_SECT_AP_WRITE | \
887 PMD_SECT_AP_READ
888 .long PMD_TYPE_SECT | \
889 PMD_SECT_AP_WRITE | \
890 PMD_SECT_AP_READ
891 b __xscale_setup
892 .long cpu_arch_name
893 .long cpu_elf_name
894 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
895 .long cpu_ixp46x_name
896 .long xscale_processor_functions
897 .long v4wbi_tlb_fns
898 .long xscale_mc_user_fns
899 .long xscale_cache_fns
900 .size __ixp46x_proc_info, . - __ixp46x_proc_info
902 .type __pxa255_proc_info,#object
903 __pxa255_proc_info:
904 .long 0x69052d00
905 .long 0xfffffff0
906 .long PMD_TYPE_SECT | \
907 PMD_SECT_BUFFERABLE | \
908 PMD_SECT_CACHEABLE | \
909 PMD_SECT_AP_WRITE | \
910 PMD_SECT_AP_READ
911 .long PMD_TYPE_SECT | \
912 PMD_SECT_AP_WRITE | \
913 PMD_SECT_AP_READ
914 b __xscale_setup
915 .long cpu_arch_name
916 .long cpu_elf_name
917 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
918 .long cpu_pxa255_name
919 .long xscale_processor_functions
920 .long v4wbi_tlb_fns
921 .long xscale_mc_user_fns
922 .long xscale_cache_fns
923 .size __pxa255_proc_info, . - __pxa255_proc_info
925 .type __pxa270_proc_info,#object
926 __pxa270_proc_info:
927 .long 0x69054110
928 .long 0xfffffff0
929 .long PMD_TYPE_SECT | \
930 PMD_SECT_BUFFERABLE | \
931 PMD_SECT_CACHEABLE | \
932 PMD_SECT_AP_WRITE | \
933 PMD_SECT_AP_READ
934 .long PMD_TYPE_SECT | \
935 PMD_SECT_AP_WRITE | \
936 PMD_SECT_AP_READ
937 b __xscale_setup
938 .long cpu_arch_name
939 .long cpu_elf_name
940 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
941 .long cpu_pxa270_name
942 .long xscale_processor_functions
943 .long v4wbi_tlb_fns
944 .long xscale_mc_user_fns
945 .long xscale_cache_fns
946 .size __pxa270_proc_info, . - __pxa270_proc_info