arch/powerpc/sysdev/fsl_rio.c

   1 /*
   2  * Freescale MPC85xx/MPC86xx RapidIO support
   3  *
   4  * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
   5  * Zhang Wei <wei.zhang@freescale.com>
   6  *
   7  * Copyright 2005 MontaVista Software, Inc.
   8  * Matt Porter <mporter@kernel.crashing.org>
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/rio.h>
  22 #include <linux/rio_drv.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/delay.h>
  25
  26 #include <asm/io.h>
  27
  28 /* RapidIO definition irq, which read from OF-tree */
  29 #define IRQ_RIO_BELL(m)         (((struct rio_priv *)(m->priv))->bellirq)
  30 #define IRQ_RIO_TX(m)           (((struct rio_priv *)(m->priv))->txirq)
  31 #define IRQ_RIO_RX(m)           (((struct rio_priv *)(m->priv))->rxirq)
  32
  33 #define RIO_ATMU_REGS_OFFSET    0x10c00
  34 #define RIO_P_MSG_REGS_OFFSET   0x11000
  35 #define RIO_S_MSG_REGS_OFFSET   0x13000
  36 #define RIO_ESCSR               0x158
  37 #define RIO_CCSR                0x15c
  38 #define RIO_ISR_AACR            0x10120
  39 #define RIO_ISR_AACR_AA         0x1     /* Accept All ID */
  40 #define RIO_MAINT_WIN_SIZE      0x400000
  41 #define RIO_DBELL_WIN_SIZE      0x1000
  42
  43 #define RIO_MSG_OMR_MUI         0x00000002
  44 #define RIO_MSG_OSR_TE          0x00000080
  45 #define RIO_MSG_OSR_QOI         0x00000020
  46 #define RIO_MSG_OSR_QFI         0x00000010
  47 #define RIO_MSG_OSR_MUB         0x00000004
  48 #define RIO_MSG_OSR_EOMI        0x00000002
  49 #define RIO_MSG_OSR_QEI         0x00000001
  50
  51 #define RIO_MSG_IMR_MI          0x00000002
  52 #define RIO_MSG_ISR_TE          0x00000080
  53 #define RIO_MSG_ISR_QFI         0x00000010
  54 #define RIO_MSG_ISR_DIQI        0x00000001
  55
  56 #define RIO_MSG_DESC_SIZE       32
  57 #define RIO_MSG_BUFFER_SIZE     4096
  58 #define RIO_MIN_TX_RING_SIZE    2
  59 #define RIO_MAX_TX_RING_SIZE    2048
  60 #define RIO_MIN_RX_RING_SIZE    2
  61 #define RIO_MAX_RX_RING_SIZE    2048
  62
  63 #define DOORBELL_DMR_DI         0x00000002
  64 #define DOORBELL_DSR_TE         0x00000080
  65 #define DOORBELL_DSR_QFI        0x00000010
  66 #define DOORBELL_DSR_DIQI       0x00000001
  67 #define DOORBELL_TID_OFFSET     0x02
  68 #define DOORBELL_SID_OFFSET     0x04
  69 #define DOORBELL_INFO_OFFSET    0x06
  70
  71 #define DOORBELL_MESSAGE_SIZE   0x08
  72 #define DBELL_SID(x)            (*(u16 *)(x + DOORBELL_SID_OFFSET))
  73 #define DBELL_TID(x)            (*(u16 *)(x + DOORBELL_TID_OFFSET))
  74 #define DBELL_INF(x)            (*(u16 *)(x + DOORBELL_INFO_OFFSET))
  75
  76 struct rio_atmu_regs {
  77         u32 rowtar;
  78         u32 rowtear;
  79         u32 rowbar;
  80         u32 pad2;
  81         u32 rowar;
  82         u32 pad3[3];
  83 };
  84
  85 struct rio_msg_regs {
  86         u32 omr;
  87         u32 osr;
  88         u32 pad1;
  89         u32 odqdpar;
  90         u32 pad2;
  91         u32 osar;
  92         u32 odpr;
  93         u32 odatr;
  94         u32 odcr;
  95         u32 pad3;
  96         u32 odqepar;
  97         u32 pad4[13];
  98         u32 imr;
  99         u32 isr;
 100         u32 pad5;
 101         u32 ifqdpar;
 102         u32 pad6;
 103         u32 ifqepar;
 104         u32 pad7[226];
 105         u32 odmr;
 106         u32 odsr;
 107         u32 res0[4];
 108         u32 oddpr;
 109         u32 oddatr;
 110         u32 res1[3];
 111         u32 odretcr;
 112         u32 res2[12];
 113         u32 dmr;
 114         u32 dsr;
 115         u32 pad8;
 116         u32 dqdpar;
 117         u32 pad9;
 118         u32 dqepar;
 119         u32 pad10[26];
 120         u32 pwmr;
 121         u32 pwsr;
 122         u32 pad11;
 123         u32 pwqbar;
 124 };
 125
 126 struct rio_tx_desc {
 127         u32 res1;
 128         u32 saddr;
 129         u32 dport;
 130         u32 dattr;
 131         u32 res2;
 132         u32 res3;
 133         u32 dwcnt;
 134         u32 res4;
 135 };
 136
 137 struct rio_dbell_ring {
 138         void *virt;
 139         dma_addr_t phys;
 140 };
 141
 142 struct rio_msg_tx_ring {
 143         void *virt;
 144         dma_addr_t phys;
 145         void *virt_buffer[RIO_MAX_TX_RING_SIZE];
 146         dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
 147         int tx_slot;
 148         int size;
 149         void *dev_id;
 150 };
 151
 152 struct rio_msg_rx_ring {
 153         void *virt;
 154         dma_addr_t phys;
 155         void *virt_buffer[RIO_MAX_RX_RING_SIZE];
 156         int rx_slot;
 157         int size;
 158         void *dev_id;
 159 };
 160
 161 struct rio_priv {
 162         void __iomem *regs_win;
 163         struct rio_atmu_regs __iomem *atmu_regs;
 164         struct rio_atmu_regs __iomem *maint_atmu_regs;
 165         struct rio_atmu_regs __iomem *dbell_atmu_regs;
 166         void __iomem *dbell_win;
 167         void __iomem *maint_win;
 168         struct rio_msg_regs __iomem *msg_regs;
 169         struct rio_dbell_ring dbell_ring;
 170         struct rio_msg_tx_ring msg_tx_ring;
 171         struct rio_msg_rx_ring msg_rx_ring;
 172         int bellirq;
 173         int txirq;
 174         int rxirq;
 175 };
 176
 177 /**
 178  * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
 179  * @index: ID of RapidIO interface
 180  * @destid: Destination ID of target device
 181  * @data: 16-bit info field of RapidIO doorbell message
 182  *
 183  * Sends a MPC85xx doorbell message. Returns %0 on success or
 184  * %-EINVAL on failure.
 185  */
 186 static int fsl_rio_doorbell_send(struct rio_mport *mport,
 187                                 int index, u16 destid, u16 data)
 188 {
 189         struct rio_priv *priv = mport->priv;
 190         pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
 191                  index, destid, data);
 192         switch (mport->phy_type) {
 193         case RIO_PHY_PARALLEL:
 194                 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
 195                 out_be16(priv->dbell_win, data);
 196                 break;
 197         case RIO_PHY_SERIAL:
 198                 /* In the serial version silicons, such as MPC8548, MPC8641,
 199                  * below operations is must be.
 200                  */
 201                 out_be32(&priv->msg_regs->odmr, 0x00000000);
 202                 out_be32(&priv->msg_regs->odretcr, 0x00000004);
 203                 out_be32(&priv->msg_regs->oddpr, destid << 16);
 204                 out_be32(&priv->msg_regs->oddatr, data);
 205                 out_be32(&priv->msg_regs->odmr, 0x00000001);
 206                 break;
 207         }
 208
 209         return 0;
 210 }
 211
 212 /**
 213  * fsl_local_config_read - Generate a MPC85xx local config space read
 214  * @index: ID of RapdiIO interface
 215  * @offset: Offset into configuration space
 216  * @len: Length (in bytes) of the maintenance transaction
 217  * @data: Value to be read into
 218  *
 219  * Generates a MPC85xx local configuration space read. Returns %0 on
 220  * success or %-EINVAL on failure.
 221  */
 222 static int fsl_local_config_read(struct rio_mport *mport,
 223                                 int index, u32 offset, int len, u32 *data)
 224 {
 225         struct rio_priv *priv = mport->priv;
 226         pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
 227                  offset);
 228         *data = in_be32(priv->regs_win + offset);
 229
 230         return 0;
 231 }
 232
 233 /**
 234  * fsl_local_config_write - Generate a MPC85xx local config space write
 235  * @index: ID of RapdiIO interface
 236  * @offset: Offset into configuration space
 237  * @len: Length (in bytes) of the maintenance transaction
 238  * @data: Value to be written
 239  *
 240  * Generates a MPC85xx local configuration space write. Returns %0 on
 241  * success or %-EINVAL on failure.
 242  */
 243 static int fsl_local_config_write(struct rio_mport *mport,
 244                                 int index, u32 offset, int len, u32 data)
 245 {
 246         struct rio_priv *priv = mport->priv;
 247         pr_debug
 248             ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
 249              index, offset, data);
 250         out_be32(priv->regs_win + offset, data);
 251
 252         return 0;
 253 }
 254
 255 /**
 256  * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
 257  * @index: ID of RapdiIO interface
 258  * @destid: Destination ID of transaction
 259  * @hopcount: Number of hops to target device
 260  * @offset: Offset into configuration space
 261  * @len: Length (in bytes) of the maintenance transaction
 262  * @val: Location to be read into
 263  *
 264  * Generates a MPC85xx read maintenance transaction. Returns %0 on
 265  * success or %-EINVAL on failure.
 266  */
 267 static int
 268 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
 269                         u8 hopcount, u32 offset, int len, u32 *val)
 270 {
 271         struct rio_priv *priv = mport->priv;
 272         u8 *data;
 273
 274         pr_debug
 275             ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
 276              index, destid, hopcount, offset, len);
 277         out_be32(&priv->maint_atmu_regs->rowtar,
 278                  (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
 279
 280         data = (u8 *) priv->maint_win + offset;
 281         switch (len) {
 282         case 1:
 283                 *val = in_8((u8 *) data);
 284                 break;
 285         case 2:
 286                 *val = in_be16((u16 *) data);
 287                 break;
 288         default:
 289                 *val = in_be32((u32 *) data);
 290                 break;
 291         }
 292
 293         return 0;
 294 }
 295
 296 /**
 297  * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
 298  * @index: ID of RapdiIO interface
 299  * @destid: Destination ID of transaction
 300  * @hopcount: Number of hops to target device
 301  * @offset: Offset into configuration space
 302  * @len: Length (in bytes) of the maintenance transaction
 303  * @val: Value to be written
 304  *
 305  * Generates an MPC85xx write maintenance transaction. Returns %0 on
 306  * success or %-EINVAL on failure.
 307  */
 308 static int
 309 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
 310                         u8 hopcount, u32 offset, int len, u32 val)
 311 {
 312         struct rio_priv *priv = mport->priv;
 313         u8 *data;
 314         pr_debug
 315             ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
 316              index, destid, hopcount, offset, len, val);
 317         out_be32(&priv->maint_atmu_regs->rowtar,
 318                  (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
 319
 320         data = (u8 *) priv->maint_win + offset;
 321         switch (len) {
 322         case 1:
 323                 out_8((u8 *) data, val);
 324                 break;
 325         case 2:
 326                 out_be16((u16 *) data, val);
 327                 break;
 328         default:
 329                 out_be32((u32 *) data, val);
 330                 break;
 331         }
 332
 333         return 0;
 334 }
 335
 336 /**
 337  * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
 338  * @mport: Master port with outbound message queue
 339  * @rdev: Target of outbound message
 340  * @mbox: Outbound mailbox
 341  * @buffer: Message to add to outbound queue
 342  * @len: Length of message
 343  *
 344  * Adds the @buffer message to the MPC85xx outbound message queue. Returns
 345  * %0 on success or %-EINVAL on failure.
 346  */
 347 int
 348 rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
 349                         void *buffer, size_t len)
 350 {
 351         struct rio_priv *priv = mport->priv;
 352         u32 omr;
 353         struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
 354                                         + priv->msg_tx_ring.tx_slot;
 355         int ret = 0;
 356
 357         pr_debug
 358             ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
 359              rdev->destid, mbox, (int)buffer, len);
 360
 361         if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
 362                 ret = -EINVAL;
 363                 goto out;
 364         }
 365
 366         /* Copy and clear rest of buffer */
 367         memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
 368                         len);
 369         if (len < (RIO_MAX_MSG_SIZE - 4))
 370                 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
 371                                 + len, 0, RIO_MAX_MSG_SIZE - len);
 372
 373         switch (mport->phy_type) {
 374         case RIO_PHY_PARALLEL:
 375                 /* Set mbox field for message */
 376                 desc->dport = mbox & 0x3;
 377
 378                 /* Enable EOMI interrupt, set priority, and set destid */
 379                 desc->dattr = 0x28000000 | (rdev->destid << 2);
 380                 break;
 381         case RIO_PHY_SERIAL:
 382                 /* Set mbox field for message, and set destid */
 383                 desc->dport = (rdev->destid << 16) | (mbox & 0x3);
 384
 385                 /* Enable EOMI interrupt and priority */
 386                 desc->dattr = 0x28000000;
 387                 break;
 388         }
 389
 390         /* Set transfer size aligned to next power of 2 (in double words) */
 391         desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
 392
 393         /* Set snooping and source buffer address */
 394         desc->saddr = 0x00000004
 395                 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
 396
 397         /* Increment enqueue pointer */
 398         omr = in_be32(&priv->msg_regs->omr);
 399         out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
 400
 401         /* Go to next descriptor */
 402         if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
 403                 priv->msg_tx_ring.tx_slot = 0;
 404
 405       out:
 406         return ret;
 407 }
 408
 409 EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
 410
 411 /**
 412  * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
 413  * @irq: Linux interrupt number
 414  * @dev_instance: Pointer to interrupt-specific data
 415  *
 416  * Handles outbound message interrupts. Executes a register outbound
 417  * mailbox event handler and acks the interrupt occurrence.
 418  */
 419 static irqreturn_t
 420 fsl_rio_tx_handler(int irq, void *dev_instance)
 421 {
 422         int osr;
 423         struct rio_mport *port = (struct rio_mport *)dev_instance;
 424         struct rio_priv *priv = port->priv;
 425
 426         osr = in_be32(&priv->msg_regs->osr);
 427
 428         if (osr & RIO_MSG_OSR_TE) {
 429                 pr_info("RIO: outbound message transmission error\n");
 430                 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
 431                 goto out;
 432         }
 433
 434         if (osr & RIO_MSG_OSR_QOI) {
 435                 pr_info("RIO: outbound message queue overflow\n");
 436                 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
 437                 goto out;
 438         }
 439
 440         if (osr & RIO_MSG_OSR_EOMI) {
 441                 u32 dqp = in_be32(&priv->msg_regs->odqdpar);
 442                 int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
 443                 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
 444                                 slot);
 445
 446                 /* Ack the end-of-message interrupt */
 447                 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
 448         }
 449
 450       out:
 451         return IRQ_HANDLED;
 452 }
 453
 454 /**
 455  * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
 456  * @mport: Master port implementing the outbound message unit
 457  * @dev_id: Device specific pointer to pass on event
 458  * @mbox: Mailbox to open
 459  * @entries: Number of entries in the outbound mailbox ring
 460  *
 461  * Initializes buffer ring, request the outbound message interrupt,
 462  * and enables the outbound message unit. Returns %0 on success and
 463  * %-EINVAL or %-ENOMEM on failure.
 464  */
 465 int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
 466 {
 467         int i, j, rc = 0;
 468         struct rio_priv *priv = mport->priv;
 469
 470         if ((entries < RIO_MIN_TX_RING_SIZE) ||
 471             (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
 472                 rc = -EINVAL;
 473                 goto out;
 474         }
 475
 476         /* Initialize shadow copy ring */
 477         priv->msg_tx_ring.dev_id = dev_id;
 478         priv->msg_tx_ring.size = entries;
 479
 480         for (i = 0; i < priv->msg_tx_ring.size; i++) {
 481                 priv->msg_tx_ring.virt_buffer[i] =
 482                         dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE,
 483                                 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
 484                 if (!priv->msg_tx_ring.virt_buffer[i]) {
 485                         rc = -ENOMEM;
 486                         for (j = 0; j < priv->msg_tx_ring.size; j++)
 487                                 if (priv->msg_tx_ring.virt_buffer[j])
 488                                         dma_free_coherent(NULL,
 489                                                         RIO_MSG_BUFFER_SIZE,
 490                                                         priv->msg_tx_ring.
 491                                                         virt_buffer[j],
 492                                                         priv->msg_tx_ring.
 493                                                         phys_buffer[j]);
 494                         goto out;
 495                 }
 496         }
 497
 498         /* Initialize outbound message descriptor ring */
 499         priv->msg_tx_ring.virt = dma_alloc_coherent(NULL,
 500                                 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
 501                                 &priv->msg_tx_ring.phys, GFP_KERNEL);
 502         if (!priv->msg_tx_ring.virt) {
 503                 rc = -ENOMEM;
 504                 goto out_dma;
 505         }
 506         memset(priv->msg_tx_ring.virt, 0,
 507                         priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
 508         priv->msg_tx_ring.tx_slot = 0;
 509
 510         /* Point dequeue/enqueue pointers at first entry in ring */
 511         out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
 512         out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
 513
 514         /* Configure for snooping */
 515         out_be32(&priv->msg_regs->osar, 0x00000004);
 516
 517         /* Clear interrupt status */
 518         out_be32(&priv->msg_regs->osr, 0x000000b3);
 519
 520         /* Hook up outbound message handler */
 521         rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
 522                          "msg_tx", (void *)mport);
 523         if (rc < 0)
 524                 goto out_irq;
 525
 526         /*
 527          * Configure outbound message unit
 528          *      Snooping
 529          *      Interrupts (all enabled, except QEIE)
 530          *      Chaining mode
 531          *      Disable
 532          */
 533         out_be32(&priv->msg_regs->omr, 0x00100220);
 534
 535         /* Set number of entries */
 536         out_be32(&priv->msg_regs->omr,
 537                  in_be32(&priv->msg_regs->omr) |
 538                  ((get_bitmask_order(entries) - 2) << 12));
 539
 540         /* Now enable the unit */
 541         out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
 542
 543       out:
 544         return rc;
 545
 546       out_irq:
 547         dma_free_coherent(NULL, priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
 548                           priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
 549
 550       out_dma:
 551         for (i = 0; i < priv->msg_tx_ring.size; i++)
 552                 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
 553                                   priv->msg_tx_ring.virt_buffer[i],
 554                                   priv->msg_tx_ring.phys_buffer[i]);
 555
 556         return rc;
 557 }
 558
 559 /**
 560  * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
 561  * @mport: Master port implementing the outbound message unit
 562  * @mbox: Mailbox to close
 563  *
 564  * Disables the outbound message unit, free all buffers, and
 565  * frees the outbound message interrupt.
 566  */
 567 void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
 568 {
 569         struct rio_priv *priv = mport->priv;
 570         /* Disable inbound message unit */
 571         out_be32(&priv->msg_regs->omr, 0);
 572
 573         /* Free ring */
 574         dma_free_coherent(NULL, priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
 575                           priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
 576
 577         /* Free interrupt */
 578         free_irq(IRQ_RIO_TX(mport), (void *)mport);
 579 }
 580
 581 /**
 582  * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
 583  * @irq: Linux interrupt number
 584  * @dev_instance: Pointer to interrupt-specific data
 585  *
 586  * Handles inbound message interrupts. Executes a registered inbound
 587  * mailbox event handler and acks the interrupt occurrence.
 588  */
 589 static irqreturn_t
 590 fsl_rio_rx_handler(int irq, void *dev_instance)
 591 {
 592         int isr;
 593         struct rio_mport *port = (struct rio_mport *)dev_instance;
 594         struct rio_priv *priv = port->priv;
 595
 596         isr = in_be32(&priv->msg_regs->isr);
 597
 598         if (isr & RIO_MSG_ISR_TE) {
 599                 pr_info("RIO: inbound message reception error\n");
 600                 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
 601                 goto out;
 602         }
 603
 604         /* XXX Need to check/dispatch until queue empty */
 605         if (isr & RIO_MSG_ISR_DIQI) {
 606                 /*
 607                  * We implement *only* mailbox 0, but can receive messages
 608                  * for any mailbox/letter to that mailbox destination. So,
 609                  * make the callback with an unknown/invalid mailbox number
 610                  * argument.
 611                  */
 612                 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
 613
 614                 /* Ack the queueing interrupt */
 615                 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
 616         }
 617
 618       out:
 619         return IRQ_HANDLED;
 620 }
 621
 622 /**
 623  * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
 624  * @mport: Master port implementing the inbound message unit
 625  * @dev_id: Device specific pointer to pass on event
 626  * @mbox: Mailbox to open
 627  * @entries: Number of entries in the inbound mailbox ring
 628  *
 629  * Initializes buffer ring, request the inbound message interrupt,
 630  * and enables the inbound message unit. Returns %0 on success
 631  * and %-EINVAL or %-ENOMEM on failure.
 632  */
 633 int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
 634 {
 635         int i, rc = 0;
 636         struct rio_priv *priv = mport->priv;
 637
 638         if ((entries < RIO_MIN_RX_RING_SIZE) ||
 639             (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
 640                 rc = -EINVAL;
 641                 goto out;
 642         }
 643
 644         /* Initialize client buffer ring */
 645         priv->msg_rx_ring.dev_id = dev_id;
 646         priv->msg_rx_ring.size = entries;
 647         priv->msg_rx_ring.rx_slot = 0;
 648         for (i = 0; i < priv->msg_rx_ring.size; i++)
 649                 priv->msg_rx_ring.virt_buffer[i] = NULL;
 650
 651         /* Initialize inbound message ring */
 652         priv->msg_rx_ring.virt = dma_alloc_coherent(NULL,
 653                                 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
 654                                 &priv->msg_rx_ring.phys, GFP_KERNEL);
 655         if (!priv->msg_rx_ring.virt) {
 656                 rc = -ENOMEM;
 657                 goto out;
 658         }
 659
 660         /* Point dequeue/enqueue pointers at first entry in ring */
 661         out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
 662         out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
 663
 664         /* Clear interrupt status */
 665         out_be32(&priv->msg_regs->isr, 0x00000091);
 666
 667         /* Hook up inbound message handler */
 668         rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
 669                          "msg_rx", (void *)mport);
 670         if (rc < 0) {
 671                 dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
 672                                   priv->msg_tx_ring.virt_buffer[i],
 673                                   priv->msg_tx_ring.phys_buffer[i]);
 674                 goto out;
 675         }
 676
 677         /*
 678          * Configure inbound message unit:
 679          *      Snooping
 680          *      4KB max message size
 681          *      Unmask all interrupt sources
 682          *      Disable
 683          */
 684         out_be32(&priv->msg_regs->imr, 0x001b0060);
 685
 686         /* Set number of queue entries */
 687         setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
 688
 689         /* Now enable the unit */
 690         setbits32(&priv->msg_regs->imr, 0x1);
 691
 692       out:
 693         return rc;
 694 }
 695
 696 /**
 697  * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
 698  * @mport: Master port implementing the inbound message unit
 699  * @mbox: Mailbox to close
 700  *
 701  * Disables the inbound message unit, free all buffers, and
 702  * frees the inbound message interrupt.
 703  */
 704 void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
 705 {
 706         struct rio_priv *priv = mport->priv;
 707         /* Disable inbound message unit */
 708         out_be32(&priv->msg_regs->imr, 0);
 709
 710         /* Free ring */
 711         dma_free_coherent(NULL, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
 712                           priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
 713
 714         /* Free interrupt */
 715         free_irq(IRQ_RIO_RX(mport), (void *)mport);
 716 }
 717
 718 /**
 719  * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
 720  * @mport: Master port implementing the inbound message unit
 721  * @mbox: Inbound mailbox number
 722  * @buf: Buffer to add to inbound queue
 723  *
 724  * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
 725  * %0 on success or %-EINVAL on failure.
 726  */
 727 int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
 728 {
 729         int rc = 0;
 730         struct rio_priv *priv = mport->priv;
 731
 732         pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
 733                  priv->msg_rx_ring.rx_slot);
 734
 735         if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
 736                 printk(KERN_ERR
 737                        "RIO: error adding inbound buffer %d, buffer exists\n",
 738                        priv->msg_rx_ring.rx_slot);
 739                 rc = -EINVAL;
 740                 goto out;
 741         }
 742
 743         priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
 744         if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
 745                 priv->msg_rx_ring.rx_slot = 0;
 746
 747       out:
 748         return rc;
 749 }
 750
 751 EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
 752
 753 /**
 754  * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
 755  * @mport: Master port implementing the inbound message unit
 756  * @mbox: Inbound mailbox number
 757  *
 758  * Gets the next available inbound message from the inbound message queue.
 759  * A pointer to the message is returned on success or NULL on failure.
 760  */
 761 void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
 762 {
 763         struct rio_priv *priv = mport->priv;
 764         u32 phys_buf, virt_buf;
 765         void *buf = NULL;
 766         int buf_idx;
 767
 768         phys_buf = in_be32(&priv->msg_regs->ifqdpar);
 769
 770         /* If no more messages, then bail out */
 771         if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
 772                 goto out2;
 773
 774         virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
 775                                                 - priv->msg_rx_ring.phys);
 776         buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
 777         buf = priv->msg_rx_ring.virt_buffer[buf_idx];
 778
 779         if (!buf) {
 780                 printk(KERN_ERR
 781                        "RIO: inbound message copy failed, no buffers\n");
 782                 goto out1;
 783         }
 784
 785         /* Copy max message size, caller is expected to allocate that big */
 786         memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
 787
 788         /* Clear the available buffer */
 789         priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
 790
 791       out1:
 792         setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
 793
 794       out2:
 795         return buf;
 796 }
 797
 798 EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
 799
 800 /**
 801  * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
 802  * @irq: Linux interrupt number
 803  * @dev_instance: Pointer to interrupt-specific data
 804  *
 805  * Handles doorbell interrupts. Parses a list of registered
 806  * doorbell event handlers and executes a matching event handler.
 807  */
 808 static irqreturn_t
 809 fsl_rio_dbell_handler(int irq, void *dev_instance)
 810 {
 811         int dsr;
 812         struct rio_mport *port = (struct rio_mport *)dev_instance;
 813         struct rio_priv *priv = port->priv;
 814
 815         dsr = in_be32(&priv->msg_regs->dsr);
 816
 817         if (dsr & DOORBELL_DSR_TE) {
 818                 pr_info("RIO: doorbell reception error\n");
 819                 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
 820                 goto out;
 821         }
 822
 823         if (dsr & DOORBELL_DSR_QFI) {
 824                 pr_info("RIO: doorbell queue full\n");
 825                 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
 826                 goto out;
 827         }
 828
 829         /* XXX Need to check/dispatch until queue empty */
 830         if (dsr & DOORBELL_DSR_DIQI) {
 831                 u32 dmsg =
 832                     (u32) priv->dbell_ring.virt +
 833                     (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
 834                 struct rio_dbell *dbell;
 835                 int found = 0;
 836
 837                 pr_debug
 838                     ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
 839                      DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
 840
 841                 list_for_each_entry(dbell, &port->dbells, node) {
 842                         if ((dbell->res->start <= DBELL_INF(dmsg)) &&
 843                             (dbell->res->end >= DBELL_INF(dmsg))) {
 844                                 found = 1;
 845                                 break;
 846                         }
 847                 }
 848                 if (found) {
 849                         dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
 850                                     DBELL_INF(dmsg));
 851                 } else {
 852                         pr_debug
 853                             ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
 854                              DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
 855                 }
 856                 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
 857                 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
 858         }
 859
 860       out:
 861         return IRQ_HANDLED;
 862 }
 863
 864 /**
 865  * fsl_rio_doorbell_init - MPC85xx doorbell interface init
 866  * @mport: Master port implementing the inbound doorbell unit
 867  *
 868  * Initializes doorbell unit hardware and inbound DMA buffer
 869  * ring. Called from fsl_rio_setup(). Returns %0 on success
 870  * or %-ENOMEM on failure.
 871  */
 872 static int fsl_rio_doorbell_init(struct rio_mport *mport)
 873 {
 874         struct rio_priv *priv = mport->priv;
 875         int rc = 0;
 876
 877         /* Map outbound doorbell window immediately after maintenance window */
 878         priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
 879                             RIO_DBELL_WIN_SIZE);
 880         if (!priv->dbell_win) {
 881                 printk(KERN_ERR
 882                        "RIO: unable to map outbound doorbell window\n");
 883                 rc = -ENOMEM;
 884                 goto out;
 885         }
 886
 887         /* Initialize inbound doorbells */
 888         priv->dbell_ring.virt = dma_alloc_coherent(NULL, 512 *
 889                     DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
 890         if (!priv->dbell_ring.virt) {
 891                 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
 892                 rc = -ENOMEM;
 893                 iounmap(priv->dbell_win);
 894                 goto out;
 895         }
 896
 897         /* Point dequeue/enqueue pointers at first entry in ring */
 898         out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
 899         out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
 900
 901         /* Clear interrupt status */
 902         out_be32(&priv->msg_regs->dsr, 0x00000091);
 903
 904         /* Hook up doorbell handler */
 905         rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
 906                          "dbell_rx", (void *)mport);
 907         if (rc < 0) {
 908                 iounmap(priv->dbell_win);
 909                 dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE,
 910                                   priv->dbell_ring.virt, priv->dbell_ring.phys);
 911                 printk(KERN_ERR
 912                        "MPC85xx RIO: unable to request inbound doorbell irq");
 913                 goto out;
 914         }
 915
 916         /* Configure doorbells for snooping, 512 entries, and enable */
 917         out_be32(&priv->msg_regs->dmr, 0x00108161);
 918
 919       out:
 920         return rc;
 921 }
 922
 923 static char *cmdline = NULL;
 924
 925 static int fsl_rio_get_hdid(int index)
 926 {
 927         /* XXX Need to parse multiple entries in some format */
 928         if (!cmdline)
 929                 return -1;
 930
 931         return simple_strtol(cmdline, NULL, 0);
 932 }
 933
 934 static int fsl_rio_get_cmdline(char *s)
 935 {
 936         if (!s)
 937                 return 0;
 938
 939         cmdline = s;
 940         return 1;
 941 }
 942
 943 __setup("riohdid=", fsl_rio_get_cmdline);
 944
 945 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
 946 {
 947         const char *str;
 948         if (ccsr & 1) {
 949                 /* Serial phy */
 950                 switch (ccsr >> 30) {
 951                 case 0:
 952                         str = "1";
 953                         break;
 954                 case 1:
 955                         str = "4";
 956                         break;
 957                 default:
 958                         str = "Unknown";
 959                         break;;
 960                 }
 961                 dev_info(dev, "Hardware port width: %s\n", str);
 962
 963                 switch ((ccsr >> 27) & 7) {
 964                 case 0:
 965                         str = "Single-lane 0";
 966                         break;
 967                 case 1:
 968                         str = "Single-lane 2";
 969                         break;
 970                 case 2:
 971                         str = "Four-lane";
 972                         break;
 973                 default:
 974                         str = "Unknown";
 975                         break;
 976                 }
 977                 dev_info(dev, "Training connection status: %s\n", str);
 978         } else {
 979                 /* Parallel phy */
 980                 if (!(ccsr & 0x80000000))
 981                         dev_info(dev, "Output port operating in 8-bit mode\n");
 982                 if (!(ccsr & 0x08000000))
 983                         dev_info(dev, "Input port operating in 8-bit mode\n");
 984         }
 985 }
 986
 987 /**
 988  * fsl_rio_setup - Setup MPC85xx RapidIO interface
 989  * @fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
 990  *
 991  * Initializes MPC85xx RapidIO hardware interface, configures
 992  * master port with system-specific info, and registers the
 993  * master port with the RapidIO subsystem.
 994  */
 995 int fsl_rio_setup(struct of_device *dev)
 996 {
 997         struct rio_ops *ops;
 998         struct rio_mport *port;
 999         struct rio_priv *priv;
1000         int rc = 0;
1001         const u32 *dt_range, *cell;
1002         struct resource regs;
1003         int rlen;
1004         u32 ccsr;
1005         u64 law_start, law_size;
1006         int paw, aw, sw;
1007
1008         if (!dev->node) {
1009                 dev_err(&dev->dev, "Device OF-Node is NULL");
1010                 return -EFAULT;
1011         }
1012
1013         rc = of_address_to_resource(dev->node, 0, &regs);
1014         if (rc) {
1015                 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
1016                                 dev->node->full_name);
1017                 return -EFAULT;
1018         }
1019         dev_info(&dev->dev, "Of-device full name %s\n", dev->node->full_name);
1020         dev_info(&dev->dev, "Regs start 0x%08x size 0x%08x\n",  regs.start,
1021                                                 regs.end - regs.start + 1);
1022
1023         dt_range = of_get_property(dev->node, "ranges", &rlen);
1024         if (!dt_range) {
1025                 dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
1026                                 dev->node->full_name);
1027                 return -EFAULT;
1028         }
1029
1030         /* Get node address wide */
1031         cell = of_get_property(dev->node, "#address-cells", NULL);
1032         if (cell)
1033                 aw = *cell;
1034         else
1035                 aw = of_n_addr_cells(dev->node);
1036         /* Get node size wide */
1037         cell = of_get_property(dev->node, "#size-cells", NULL);
1038         if (cell)
1039                 sw = *cell;
1040         else
1041                 sw = of_n_size_cells(dev->node);
1042         /* Get parent address wide wide */
1043         paw = of_n_addr_cells(dev->node);
1044
1045         law_start = of_read_number(dt_range + aw, paw);
1046         law_size = of_read_number(dt_range + aw + paw, sw);
1047
1048         dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
1049                         law_start, law_size);
1050
1051         ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
1052         ops->lcread = fsl_local_config_read;
1053         ops->lcwrite = fsl_local_config_write;
1054         ops->cread = fsl_rio_config_read;
1055         ops->cwrite = fsl_rio_config_write;
1056         ops->dsend = fsl_rio_doorbell_send;
1057
1058         port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
1059         port->id = 0;
1060         port->index = 0;
1061
1062         priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
1063         if (!priv) {
1064                 printk(KERN_ERR "Can't alloc memory for 'priv'\n");
1065                 rc = -ENOMEM;
1066                 goto err;
1067         }
1068
1069         INIT_LIST_HEAD(&port->dbells);
1070         port->iores.start = law_start;
1071         port->iores.end = law_start + law_size;
1072         port->iores.flags = IORESOURCE_MEM;
1073
1074         priv->bellirq = irq_of_parse_and_map(dev->node, 2);
1075         priv->txirq = irq_of_parse_and_map(dev->node, 3);
1076         priv->rxirq = irq_of_parse_and_map(dev->node, 4);
1077         dev_info(&dev->dev, "bellirq: %d, txirq: %d, rxirq %d\n", priv->bellirq,
1078                                 priv->txirq, priv->rxirq);
1079
1080         rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1081         rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
1082         rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
1083         strcpy(port->name, "RIO0 mport");
1084
1085         port->ops = ops;
1086         port->host_deviceid = fsl_rio_get_hdid(port->id);
1087
1088         port->priv = priv;
1089         rio_register_mport(port);
1090
1091         priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);
1092
1093         /* Probe the master port phy type */
1094         ccsr = in_be32(priv->regs_win + RIO_CCSR);
1095         port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
1096         dev_info(&dev->dev, "RapidIO PHY type: %s\n",
1097                         (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" :
1098                         ((port->phy_type == RIO_PHY_SERIAL) ? "serial" :
1099                          "unknown"));
1100         /* Checking the port training status */
1101         if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1102                 dev_err(&dev->dev, "Port is not ready. "
1103                                    "Try to restart connection...\n");
1104                 switch (port->phy_type) {
1105                 case RIO_PHY_SERIAL:
1106                         /* Disable ports */
1107                         out_be32(priv->regs_win + RIO_CCSR, 0);
1108                         /* Set 1x lane */
1109                         setbits32(priv->regs_win + RIO_CCSR, 0x02000000);
1110                         /* Enable ports */
1111                         setbits32(priv->regs_win + RIO_CCSR, 0x00600000);
1112                         break;
1113                 case RIO_PHY_PARALLEL:
1114                         /* Disable ports */
1115                         out_be32(priv->regs_win + RIO_CCSR, 0x22000000);
1116                         /* Enable ports */
1117                         out_be32(priv->regs_win + RIO_CCSR, 0x44000000);
1118                         break;
1119                 }
1120                 msleep(100);
1121                 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1122                         dev_err(&dev->dev, "Port restart failed.\n");
1123                         rc = -ENOLINK;
1124                         goto err;
1125                 }
1126                 dev_info(&dev->dev, "Port restart success!\n");
1127         }
1128         fsl_rio_info(&dev->dev, ccsr);
1129
1130         port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
1131                                         & RIO_PEF_CTLS) >> 4;
1132         dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
1133                         port->sys_size ? 65536 : 256);
1134
1135         priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
1136                                         + RIO_ATMU_REGS_OFFSET);
1137         priv->maint_atmu_regs = priv->atmu_regs + 1;
1138         priv->dbell_atmu_regs = priv->atmu_regs + 2;
1139         priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
1140                                 ((port->phy_type == RIO_PHY_SERIAL) ?
1141                                 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
1142
1143         /* Set to receive any dist ID for serial RapidIO controller. */
1144         if (port->phy_type == RIO_PHY_SERIAL)
1145                 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
1146
1147         /* Configure maintenance transaction window */
1148         out_be32(&priv->maint_atmu_regs->rowbar, 0x000c0000);
1149         out_be32(&priv->maint_atmu_regs->rowar, 0x80077015);
1150
1151         priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
1152
1153         /* Configure outbound doorbell window */
1154         out_be32(&priv->dbell_atmu_regs->rowbar, 0x000c0400);
1155         out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b);
1156         fsl_rio_doorbell_init(port);
1157
1158         return 0;
1159 err:
1160         if (priv)
1161                 iounmap(priv->regs_win);
1162         kfree(ops);
1163         kfree(priv);
1164         kfree(port);
1165         return rc;
1166 }
1167
1168 /* The probe function for RapidIO peer-to-peer network.
1169  */
1170 static int __devinit fsl_of_rio_rpn_probe(struct of_device *dev,
1171                                      const struct of_device_id *match)
1172 {
1173         int rc;
1174         printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
1175                         dev->node->full_name);
1176
1177         rc = fsl_rio_setup(dev);
1178         if (rc)
1179                 goto out;
1180
1181         /* Enumerate all registered ports */
1182         rc = rio_init_mports();
1183 out:
1184         return rc;
1185 };
1186
1187 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
1188         {
1189                 .compatible = "fsl,rapidio-delta",
1190         },
1191         {},
1192 };
1193
1194 static struct of_platform_driver fsl_of_rio_rpn_driver = {
1195         .name = "fsl-of-rio",
1196         .match_table = fsl_of_rio_rpn_ids,
1197         .probe = fsl_of_rio_rpn_probe,
1198 };
1199
1200 static __init int fsl_of_rio_rpn_init(void)
1201 {
1202         return of_register_platform_driver(&fsl_of_rio_rpn_driver);
1203 }
1204
1205 subsys_initcall(fsl_of_rio_rpn_init);