arch/sh/kernel/cpu/init.c

   1 /*
   2  * arch/sh/kernel/cpu/init.c
   3  *
   4  * CPU init code
   5  *
   6  * Copyright (C) 2002 - 2007  Paul Mundt
   7  * Copyright (C) 2003  Richard Curnow
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/kernel.h>
  15 #include <linux/mm.h>
  16 #include <linux/log2.h>
  17 #include <asm/mmu_context.h>
  18 #include <asm/processor.h>
  19 #include <asm/uaccess.h>
  20 #include <asm/page.h>
  21 #include <asm/system.h>
  22 #include <asm/cacheflush.h>
  23 #include <asm/cache.h>
  24 #include <asm/elf.h>
  25 #include <asm/io.h>
  26 #include <asm/smp.h>
  27 #ifdef CONFIG_SUPERH32
  28 #include <asm/ubc.h>
  29 #endif
  30
  31 /*
  32  * Generic wrapper for command line arguments to disable on-chip
  33  * peripherals (nofpu, nodsp, and so forth).
  34  */
  35 #define onchip_setup(x)                         \
  36 static int x##_disabled __initdata = 0;         \
  37                                                 \
  38 static int __init x##_setup(char *opts)         \
  39 {                                               \
  40         x##_disabled = 1;                       \
  41         return 1;                               \
  42 }                                               \
  43 __setup("no" __stringify(x), x##_setup);
  44
  45 onchip_setup(fpu);
  46 onchip_setup(dsp);
  47
  48 #ifdef CONFIG_SPECULATIVE_EXECUTION
  49 #define CPUOPM          0xff2f0000
  50 #define CPUOPM_RABD     (1 << 5)
  51
  52 static void __init speculative_execution_init(void)
  53 {
  54         /* Clear RABD */
  55         ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
  56
  57         /* Flush the update */
  58         (void)ctrl_inl(CPUOPM);
  59         ctrl_barrier();
  60 }
  61 #else
  62 #define speculative_execution_init()    do { } while (0)
  63 #endif
  64
  65 /*
  66  * Generic first-level cache init
  67  */
  68 #ifdef CONFIG_SUPERH32
  69 static void __uses_jump_to_uncached cache_init(void)
  70 {
  71         unsigned long ccr, flags;
  72
  73         jump_to_uncached();
  74         ccr = ctrl_inl(CCR);
  75
  76         /*
  77          * At this point we don't know whether the cache is enabled or not - a
  78          * bootloader may have enabled it.  There are at least 2 things that
  79          * could be dirty in the cache at this point:
  80          * 1. kernel command line set up by boot loader
  81          * 2. spilled registers from the prolog of this function
  82          * => before re-initialising the cache, we must do a purge of the whole
  83          * cache out to memory for safety.  As long as nothing is spilled
  84          * during the loop to lines that have already been done, this is safe.
  85          * - RPC
  86          */
  87         if (ccr & CCR_CACHE_ENABLE) {
  88                 unsigned long ways, waysize, addrstart;
  89
  90                 waysize = current_cpu_data.dcache.sets;
  91
  92 #ifdef CCR_CACHE_ORA
  93                 /*
  94                  * If the OC is already in RAM mode, we only have
  95                  * half of the entries to flush..
  96                  */
  97                 if (ccr & CCR_CACHE_ORA)
  98                         waysize >>= 1;
  99 #endif
 100
 101                 waysize <<= current_cpu_data.dcache.entry_shift;
 102
 103 #ifdef CCR_CACHE_EMODE
 104                 /* If EMODE is not set, we only have 1 way to flush. */
 105                 if (!(ccr & CCR_CACHE_EMODE))
 106                         ways = 1;
 107                 else
 108 #endif
 109                         ways = current_cpu_data.dcache.ways;
 110
 111                 addrstart = CACHE_OC_ADDRESS_ARRAY;
 112                 do {
 113                         unsigned long addr;
 114
 115                         for (addr = addrstart;
 116                              addr < addrstart + waysize;
 117                              addr += current_cpu_data.dcache.linesz)
 118                                 ctrl_outl(0, addr);
 119
 120                         addrstart += current_cpu_data.dcache.way_incr;
 121                 } while (--ways);
 122         }
 123
 124         /*
 125          * Default CCR values .. enable the caches
 126          * and invalidate them immediately..
 127          */
 128         flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE;
 129
 130 #ifdef CCR_CACHE_EMODE
 131         /* Force EMODE if possible */
 132         if (current_cpu_data.dcache.ways > 1)
 133                 flags |= CCR_CACHE_EMODE;
 134         else
 135                 flags &= ~CCR_CACHE_EMODE;
 136 #endif
 137
 138 #if defined(CONFIG_CACHE_WRITETHROUGH)
 139         /* Write-through */
 140         flags |= CCR_CACHE_WT;
 141 #elif defined(CONFIG_CACHE_WRITEBACK)
 142         /* Write-back */
 143         flags |= CCR_CACHE_CB;
 144 #else
 145         /* Off */
 146         flags &= ~CCR_CACHE_ENABLE;
 147 #endif
 148
 149         ctrl_outl(flags, CCR);
 150         back_to_cached();
 151 }
 152 #else
 153 #define cache_init()    do { } while (0)
 154 #endif
 155
 156 #define CSHAPE(totalsize, linesize, assoc) \
 157         ((totalsize & ~0xff) | (linesize << 4) | assoc)
 158
 159 #define CACHE_DESC_SHAPE(desc)  \
 160         CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways)
 161
 162 static void detect_cache_shape(void)
 163 {
 164         l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache);
 165
 166         if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED)
 167                 l1i_cache_shape = l1d_cache_shape;
 168         else
 169                 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache);
 170
 171         if (current_cpu_data.flags & CPU_HAS_L2_CACHE)
 172                 l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache);
 173         else
 174                 l2_cache_shape = -1; /* No S-cache */
 175 }
 176
 177 #ifdef CONFIG_SH_DSP
 178 static void __init release_dsp(void)
 179 {
 180         unsigned long sr;
 181
 182         /* Clear SR.DSP bit */
 183         __asm__ __volatile__ (
 184                 "stc\tsr, %0\n\t"
 185                 "and\t%1, %0\n\t"
 186                 "ldc\t%0, sr\n\t"
 187                 : "=&r" (sr)
 188                 : "r" (~SR_DSP)
 189         );
 190 }
 191
 192 static void __init dsp_init(void)
 193 {
 194         unsigned long sr;
 195
 196         /*
 197          * Set the SR.DSP bit, wait for one instruction, and then read
 198          * back the SR value.
 199          */
 200         __asm__ __volatile__ (
 201                 "stc\tsr, %0\n\t"
 202                 "or\t%1, %0\n\t"
 203                 "ldc\t%0, sr\n\t"
 204                 "nop\n\t"
 205                 "stc\tsr, %0\n\t"
 206                 : "=&r" (sr)
 207                 : "r" (SR_DSP)
 208         );
 209
 210         /* If the DSP bit is still set, this CPU has a DSP */
 211         if (sr & SR_DSP)
 212                 current_cpu_data.flags |= CPU_HAS_DSP;
 213
 214         /* Now that we've determined the DSP status, clear the DSP bit. */
 215         release_dsp();
 216 }
 217 #endif /* CONFIG_SH_DSP */
 218
 219 /**
 220  * sh_cpu_init
 221  *
 222  * This is our initial entry point for each CPU, and is invoked on the boot
 223  * CPU prior to calling start_kernel(). For SMP, a combination of this and
 224  * start_secondary() will bring up each processor to a ready state prior
 225  * to hand forking the idle loop.
 226  *
 227  * We do all of the basic processor init here, including setting up the
 228  * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is
 229  * hit (and subsequently platform_setup()) things like determining the
 230  * CPU subtype and initial configuration will all be done.
 231  *
 232  * Each processor family is still responsible for doing its own probing
 233  * and cache configuration in detect_cpu_and_cache_system().
 234  */
 235
 236 asmlinkage void __init sh_cpu_init(void)
 237 {
 238         current_thread_info()->cpu = hard_smp_processor_id();
 239
 240         /* First, probe the CPU */
 241         detect_cpu_and_cache_system();
 242
 243         if (current_cpu_data.type == CPU_SH_NONE)
 244                 panic("Unknown CPU");
 245
 246         /* First setup the rest of the I-cache info */
 247         current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
 248                                       current_cpu_data.icache.linesz;
 249
 250         current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
 251                                     current_cpu_data.icache.linesz;
 252
 253         /* And the D-cache too */
 254         current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
 255                                       current_cpu_data.dcache.linesz;
 256
 257         current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
 258                                     current_cpu_data.dcache.linesz;
 259
 260         /* Init the cache */
 261         cache_init();
 262
 263         if (raw_smp_processor_id() == 0) {
 264                 shm_align_mask = max_t(unsigned long,
 265                                        current_cpu_data.dcache.way_size - 1,
 266                                        PAGE_SIZE - 1);
 267
 268                 /* Boot CPU sets the cache shape */
 269                 detect_cache_shape();
 270         }
 271
 272         /* Disable the FPU */
 273         if (fpu_disabled) {
 274                 printk("FPU Disabled\n");
 275                 current_cpu_data.flags &= ~CPU_HAS_FPU;
 276                 disable_fpu();
 277         }
 278
 279         /* FPU initialization */
 280         if ((current_cpu_data.flags & CPU_HAS_FPU)) {
 281                 clear_thread_flag(TIF_USEDFPU);
 282                 clear_used_math();
 283         }
 284
 285         /*
 286          * Initialize the per-CPU ASID cache very early, since the
 287          * TLB flushing routines depend on this being setup.
 288          */
 289         current_cpu_data.asid_cache = NO_CONTEXT;
 290
 291 #ifdef CONFIG_SH_DSP
 292         /* Probe for DSP */
 293         dsp_init();
 294
 295         /* Disable the DSP */
 296         if (dsp_disabled) {
 297                 printk("DSP Disabled\n");
 298                 current_cpu_data.flags &= ~CPU_HAS_DSP;
 299                 release_dsp();
 300         }
 301 #endif
 302
 303         /*
 304          * Some brain-damaged loaders decided it would be a good idea to put
 305          * the UBC to sleep. This causes some issues when it comes to things
 306          * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB.  So ..
 307          * we wake it up and hope that all is well.
 308          */
 309 #ifdef CONFIG_SUPERH32
 310         if (raw_smp_processor_id() == 0)
 311                 ubc_wakeup();
 312 #endif
 313
 314         speculative_execution_init();
 315 }