arch/sh/kernel/cpu/sh2a/setup-sh7203.c

   1 /*
   2  * SH7203 and SH7263 Setup
   3  *
   4  *  Copyright (C) 2007  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14
  15 enum {
  16         UNUSED = 0,
  17
  18         /* interrupt sources */
  19         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  20         PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
  21         DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI,
  22         DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI,
  23         DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI,
  24         DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI,
  25         USB, LCDC, CMT0, CMT1, BSC, WDT,
  26         MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
  27         MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
  28         MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
  29         MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
  30         MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
  31         MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
  32         ADC_ADI,
  33         IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI,
  34         IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI,
  35         IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI,
  36         IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI, IIC33_TEI,
  37         SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
  38         SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
  39         SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
  40         SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
  41         SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI,
  42         SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI,
  43         SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
  44
  45         /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
  46         ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG, ROMDEC_ISEC, ROMDEC_IBUF,
  47         ROMDEC_IREADY,
  48
  49         FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
  50
  51         SDHI3, SDHI0, SDHI1,
  52
  53         RTC_ARM, RTC_PRD, RTC_CUP,
  54         RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, RCAN0_SLE,
  55         RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, RCAN1_SLE,
  56
  57         SRC_OVF, SRC_ODFI, SRC_IDEI, IEBI,
  58
  59         /* interrupt groups */
  60         PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
  61         MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
  62         MTU3_ABCD, MTU4_ABCD,
  63         IIC30, IIC31, IIC32, IIC33, SCIF0, SCIF1, SCIF2, SCIF3,
  64         SSU0, SSU1, ROMDEC, SDHI, FLCTL, RTC, RCAN0, RCAN1, SRC
  65 };
  66
  67 static struct intc_vect vectors[] __initdata = {
  68         INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
  69         INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
  70         INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
  71         INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
  72         INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
  73         INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
  74         INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
  75         INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
  76         INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109),
  77         INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113),
  78         INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117),
  79         INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121),
  80         INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125),
  81         INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129),
  82         INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133),
  83         INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137),
  84         INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
  85         INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
  86         INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
  87         INTC_IRQ(MTU2_TGI0A, 146), INTC_IRQ(MTU2_TGI0B, 147),
  88         INTC_IRQ(MTU2_TGI0C, 148), INTC_IRQ(MTU2_TGI0D, 149),
  89         INTC_IRQ(MTU2_TCI0V, 150),
  90         INTC_IRQ(MTU2_TGI0E, 151), INTC_IRQ(MTU2_TGI0F, 152),
  91         INTC_IRQ(MTU2_TGI1A, 153), INTC_IRQ(MTU2_TGI1B, 154),
  92         INTC_IRQ(MTU2_TCI1V, 155), INTC_IRQ(MTU2_TCI1U, 156),
  93         INTC_IRQ(MTU2_TGI2A, 157), INTC_IRQ(MTU2_TGI2B, 158),
  94         INTC_IRQ(MTU2_TCI2V, 159), INTC_IRQ(MTU2_TCI2U, 160),
  95         INTC_IRQ(MTU2_TGI3A, 161), INTC_IRQ(MTU2_TGI3B, 162),
  96         INTC_IRQ(MTU2_TGI3C, 163), INTC_IRQ(MTU2_TGI3D, 164),
  97         INTC_IRQ(MTU2_TCI3V, 165),
  98         INTC_IRQ(MTU2_TGI4A, 166), INTC_IRQ(MTU2_TGI4B, 167),
  99         INTC_IRQ(MTU2_TGI4C, 168), INTC_IRQ(MTU2_TGI4D, 169),
 100         INTC_IRQ(MTU2_TCI4V, 170),
 101         INTC_IRQ(ADC_ADI, 171),
 102         INTC_IRQ(IIC30_STPI, 172), INTC_IRQ(IIC30_NAKI, 173),
 103         INTC_IRQ(IIC30_RXI, 174), INTC_IRQ(IIC30_TXI, 175),
 104         INTC_IRQ(IIC30_TEI, 176),
 105         INTC_IRQ(IIC31_STPI, 177), INTC_IRQ(IIC31_NAKI, 178),
 106         INTC_IRQ(IIC31_RXI, 179), INTC_IRQ(IIC31_TXI, 180),
 107         INTC_IRQ(IIC31_TEI, 181),
 108         INTC_IRQ(IIC32_STPI, 182), INTC_IRQ(IIC32_NAKI, 183),
 109         INTC_IRQ(IIC32_RXI, 184), INTC_IRQ(IIC32_TXI, 185),
 110         INTC_IRQ(IIC32_TEI, 186),
 111         INTC_IRQ(IIC33_STPI, 187), INTC_IRQ(IIC33_NAKI, 188),
 112         INTC_IRQ(IIC33_RXI, 189), INTC_IRQ(IIC33_TXI, 190),
 113         INTC_IRQ(IIC33_TEI, 191),
 114         INTC_IRQ(SCIF0_BRI, 192), INTC_IRQ(SCIF0_ERI, 193),
 115         INTC_IRQ(SCIF0_RXI, 194), INTC_IRQ(SCIF0_TXI, 195),
 116         INTC_IRQ(SCIF1_BRI, 196), INTC_IRQ(SCIF1_ERI, 197),
 117         INTC_IRQ(SCIF1_RXI, 198), INTC_IRQ(SCIF1_TXI, 199),
 118         INTC_IRQ(SCIF2_BRI, 200), INTC_IRQ(SCIF2_ERI, 201),
 119         INTC_IRQ(SCIF2_RXI, 202), INTC_IRQ(SCIF2_TXI, 203),
 120         INTC_IRQ(SCIF3_BRI, 204), INTC_IRQ(SCIF3_ERI, 205),
 121         INTC_IRQ(SCIF3_RXI, 206), INTC_IRQ(SCIF3_TXI, 207),
 122         INTC_IRQ(SSU0_SSERI, 208), INTC_IRQ(SSU0_SSRXI, 209),
 123         INTC_IRQ(SSU0_SSTXI, 210),
 124         INTC_IRQ(SSU1_SSERI, 211), INTC_IRQ(SSU1_SSRXI, 212),
 125         INTC_IRQ(SSU1_SSTXI, 213),
 126         INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
 127         INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
 128         INTC_IRQ(FLCTL_FLSTEI, 224), INTC_IRQ(FLCTL_FLTENDI, 225),
 129         INTC_IRQ(FLCTL_FLTREQ0I, 226), INTC_IRQ(FLCTL_FLTREQ1I, 227),
 130         INTC_IRQ(RTC_ARM, 231), INTC_IRQ(RTC_PRD, 232),
 131         INTC_IRQ(RTC_CUP, 233),
 132         INTC_IRQ(RCAN0_ERS, 234), INTC_IRQ(RCAN0_OVR, 235),
 133         INTC_IRQ(RCAN0_RM0, 236), INTC_IRQ(RCAN0_RM1, 237),
 134         INTC_IRQ(RCAN0_SLE, 238),
 135         INTC_IRQ(RCAN1_ERS, 239), INTC_IRQ(RCAN1_OVR, 240),
 136         INTC_IRQ(RCAN1_RM0, 241), INTC_IRQ(RCAN1_RM1, 242),
 137         INTC_IRQ(RCAN1_SLE, 243),
 138
 139         /* SH7263-specific trash */
 140 #ifdef CONFIG_CPU_SUBTYPE_SH7263
 141         INTC_IRQ(ROMDEC_ISY, 218), INTC_IRQ(ROMDEC_IERR, 219),
 142         INTC_IRQ(ROMDEC_IARG, 220), INTC_IRQ(ROMDEC_ISEC, 221),
 143         INTC_IRQ(ROMDEC_IBUF, 222), INTC_IRQ(ROMDEC_IREADY, 223),
 144
 145         INTC_IRQ(SDHI3, 228), INTC_IRQ(SDHI0, 229), INTC_IRQ(SDHI1, 230),
 146
 147         INTC_IRQ(SRC_OVF, 244), INTC_IRQ(SRC_ODFI, 245),
 148         INTC_IRQ(SRC_IDEI, 246),
 149
 150         INTC_IRQ(IEBI, 247),
 151 #endif
 152 };
 153
 154 static struct intc_group groups[] __initdata = {
 155         INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
 156                    PINT4, PINT5, PINT6, PINT7),
 157         INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI),
 158         INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI),
 159         INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI),
 160         INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI),
 161         INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI),
 162         INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI),
 163         INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI),
 164         INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI),
 165         INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
 166         INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
 167         INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B),
 168         INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U),
 169         INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B),
 170         INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U),
 171         INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
 172         INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
 173         INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI,
 174                    IIC30_TEI),
 175         INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI,
 176                    IIC31_TEI),
 177         INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI,
 178                    IIC32_TEI),
 179         INTC_GROUP(IIC33, IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI,
 180                    IIC33_TEI),
 181         INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
 182         INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
 183         INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
 184         INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
 185         INTC_GROUP(SSU0, SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI),
 186         INTC_GROUP(SSU1, SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI),
 187         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I,
 188                    FLCTL_FLTREQ1I),
 189         INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP),
 190         INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1,
 191                    RCAN0_SLE),
 192         INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,
 193                    RCAN1_SLE),
 194
 195 #ifdef CONFIG_CPU_SUBTYPE_SH7263
 196         INTC_GROUP(ROMDEC, ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG,
 197                    ROMDEC_ISEC, ROMDEC_IBUF, ROMDEC_IREADY),
 198         INTC_GROUP(SDHI, SDHI3, SDHI0, SDHI1),
 199         INTC_GROUP(SRC, SRC_OVF, SRC_ODFI, SRC_IDEI),
 200 #endif
 201 };
 202
 203 static struct intc_prio_reg prio_registers[] __initdata = {
 204         { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
 205         { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
 206         { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
 207         { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
 208         { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
 209         { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
 210         { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
 211         { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB,
 212                                               MTU2_VU } },
 213         { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
 214                                               MTU2_TCI4V } },
 215         { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },
 216         { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },
 217         { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },
 218 #ifdef CONFIG_CPU_SUBTYPE_SH7203
 219         { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
 220                                               SSI3_SSII, 0 } },
 221         { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
 222         { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },
 223 #else
 224         { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
 225                                               SSI3_SSII, ROMDEC } },
 226         { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },
 227         { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } },
 228 #endif
 229 };
 230
 231 static struct intc_mask_reg mask_registers[] __initdata = {
 232         { 0xfffe0808, 0, 16, /* PINTER */
 233           { 0, 0, 0, 0, 0, 0, 0, 0,
 234             PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
 235 };
 236
 237 static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
 238                          mask_registers, prio_registers, NULL);
 239
 240 static struct plat_sci_port sci_platform_data[] = {
 241         {
 242                 .mapbase        = 0xfffe8000,
 243                 .flags          = UPF_BOOT_AUTOCONF,
 244                 .type           = PORT_SCIF,
 245                 .irqs           =  { 193, 194, 195, 192 },
 246         }, {
 247                 .mapbase        = 0xfffe8800,
 248                 .flags          = UPF_BOOT_AUTOCONF,
 249                 .type           = PORT_SCIF,
 250                 .irqs           =  { 197, 198, 199, 196 },
 251         }, {
 252                 .mapbase        = 0xfffe9000,
 253                 .flags          = UPF_BOOT_AUTOCONF,
 254                 .type           = PORT_SCIF,
 255                 .irqs           =  { 201, 202, 203, 200 },
 256         }, {
 257                 .mapbase        = 0xfffe9800,
 258                 .flags          = UPF_BOOT_AUTOCONF,
 259                 .type           = PORT_SCIF,
 260                 .irqs           =  { 205, 206, 207, 204 },
 261         }, {
 262                 .flags = 0,
 263         }
 264 };
 265
 266 static struct platform_device sci_device = {
 267         .name           = "sh-sci",
 268         .id             = -1,
 269         .dev            = {
 270                 .platform_data  = sci_platform_data,
 271         },
 272 };
 273
 274 static struct resource rtc_resources[] = {
 275         [0] = {
 276                 .start  = 0xffff2000,
 277                 .end    = 0xffff2000 + 0x58 - 1,
 278                 .flags  = IORESOURCE_IO,
 279         },
 280         [1] = {
 281                 /* Period IRQ */
 282                 .start  = 232,
 283                 .flags  = IORESOURCE_IRQ,
 284         },
 285         [2] = {
 286                 /* Carry IRQ */
 287                 .start  = 233,
 288                 .flags  = IORESOURCE_IRQ,
 289         },
 290         [3] = {
 291                 /* Alarm IRQ */
 292                 .start  = 231,
 293                 .flags  = IORESOURCE_IRQ,
 294         },
 295 };
 296
 297 static struct platform_device rtc_device = {
 298         .name           = "sh-rtc",
 299         .id             = -1,
 300         .num_resources  = ARRAY_SIZE(rtc_resources),
 301         .resource       = rtc_resources,
 302 };
 303
 304 static struct platform_device *sh7203_devices[] __initdata = {
 305         &sci_device,
 306         &rtc_device,
 307 };
 308
 309 static int __init sh7203_devices_setup(void)
 310 {
 311         return platform_add_devices(sh7203_devices,
 312                                     ARRAY_SIZE(sh7203_devices));
 313 }
 314 __initcall(sh7203_devices_setup);
 315
 316 void __init plat_irq_setup(void)
 317 {
 318         register_intc_controller(&intc_desc);
 319 }