arch/sh/kernel/cpu/sh4a/setup-sh7780.c

   1 /*
   2  * SH7780 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/io.h>
  14 #include <linux/serial_sci.h>
  15
  16 static struct resource rtc_resources[] = {
  17         [0] = {
  18                 .start  = 0xffe80000,
  19                 .end    = 0xffe80000 + 0x58 - 1,
  20                 .flags  = IORESOURCE_IO,
  21         },
  22         [1] = {
  23                 /* Period IRQ */
  24                 .start  = 21,
  25                 .flags  = IORESOURCE_IRQ,
  26         },
  27         [2] = {
  28                 /* Carry IRQ */
  29                 .start  = 22,
  30                 .flags  = IORESOURCE_IRQ,
  31         },
  32         [3] = {
  33                 /* Alarm IRQ */
  34                 .start  = 20,
  35                 .flags  = IORESOURCE_IRQ,
  36         },
  37 };
  38
  39 static struct platform_device rtc_device = {
  40         .name           = "sh-rtc",
  41         .id             = -1,
  42         .num_resources  = ARRAY_SIZE(rtc_resources),
  43         .resource       = rtc_resources,
  44 };
  45
  46 static struct plat_sci_port sci_platform_data[] = {
  47         {
  48                 .mapbase        = 0xffe00000,
  49                 .flags          = UPF_BOOT_AUTOCONF,
  50                 .type           = PORT_SCIF,
  51                 .irqs           = { 40, 41, 43, 42 },
  52         }, {
  53                 .mapbase        = 0xffe10000,
  54                 .flags          = UPF_BOOT_AUTOCONF,
  55                 .type           = PORT_SCIF,
  56                 .irqs           = { 76, 77, 79, 78 },
  57         }, {
  58                 .flags = 0,
  59         }
  60 };
  61
  62 static struct platform_device sci_device = {
  63         .name           = "sh-sci",
  64         .id             = -1,
  65         .dev            = {
  66                 .platform_data  = sci_platform_data,
  67         },
  68 };
  69
  70 static struct platform_device *sh7780_devices[] __initdata = {
  71         &rtc_device,
  72         &sci_device,
  73 };
  74
  75 static int __init sh7780_devices_setup(void)
  76 {
  77         return platform_add_devices(sh7780_devices,
  78                                     ARRAY_SIZE(sh7780_devices));
  79 }
  80 __initcall(sh7780_devices_setup);
  81
  82 enum {
  83         UNUSED = 0,
  84
  85         /* interrupt sources */
  86
  87         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
  88         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
  89         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
  90         IRL_HHLL, IRL_HHLH, IRL_HHHL,
  91
  92         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  93         RTC_ATI, RTC_PRI, RTC_CUI,
  94         WDT,
  95         TMU0, TMU1, TMU2, TMU2_TICPI,
  96         HUDI,
  97         DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE,
  98         SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
  99         DMAC0_DMINT4, DMAC0_DMINT5, DMAC1_DMINT6, DMAC1_DMINT7,
 100         CMT, HAC,
 101         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
 102         PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
 103         SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
 104         SIOF, HSPI,
 105         MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
 106         DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11,
 107         TMU3, TMU4, TMU5,
 108         SSI,
 109         FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
 110         GPIOI0, GPIOI1, GPIOI2, GPIOI3,
 111
 112         /* interrupt groups */
 113
 114         RTC, TMU012, DMAC0, SCIF0, DMAC45, DMAC1,
 115         PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
 116 };
 117
 118 static struct intc_vect vectors[] __initdata = {
 119         INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
 120         INTC_VECT(RTC_CUI, 0x4c0),
 121         INTC_VECT(WDT, 0x560),
 122         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 123         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 124         INTC_VECT(HUDI, 0x600),
 125         INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
 126         INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0),
 127         INTC_VECT(DMAC0_DMAE, 0x6c0),
 128         INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
 129         INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
 130         INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0),
 131         INTC_VECT(DMAC1_DMINT6, 0x7c0), INTC_VECT(DMAC1_DMINT7, 0x7e0),
 132         INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
 133         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 134         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 135         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
 136         INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
 137         INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
 138         INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0),
 139         INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0),
 140         INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
 141         INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
 142         INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
 143         INTC_VECT(DMAC1_DMINT8, 0xd80), INTC_VECT(DMAC1_DMINT9, 0xda0),
 144         INTC_VECT(DMAC1_DMINT10, 0xdc0), INTC_VECT(DMAC1_DMINT11, 0xde0),
 145         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 146         INTC_VECT(TMU5, 0xe40),
 147         INTC_VECT(SSI, 0xe80),
 148         INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
 149         INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
 150         INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
 151         INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
 152 };
 153
 154 static struct intc_group groups[] __initdata = {
 155         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 156         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 157         INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
 158                    DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
 159         INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
 160         INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
 161                    DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
 162         INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
 163         INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
 164         INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
 165         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 166         INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
 167                    FLCTL_FLTRQ0, FLCTL_FLTRQ1),
 168         INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
 169 };
 170
 171 static struct intc_mask_reg mask_registers[] __initdata = {
 172         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 173           { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
 174             SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 175             PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
 176             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 177 };
 178
 179 static struct intc_prio_reg prio_registers[] __initdata = {
 180         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 181                                                  TMU2, TMU2_TICPI } },
 182         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
 183         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
 184         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
 185         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
 186                                                  PCISERR, PCIINTA, } },
 187         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
 188                                                  PCIINTD, PCIC5 } },
 189         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
 190         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
 191 };
 192
 193 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
 194                          mask_registers, prio_registers, NULL);
 195
 196 /* Support for external interrupt pins in IRQ mode */
 197
 198 static struct intc_vect irq_vectors[] __initdata = {
 199         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 200         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 201         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 202         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 203 };
 204
 205 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 206         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 207           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 208 };
 209
 210 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 211         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 212                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 213 };
 214
 215 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 216         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 217                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 218 };
 219
 220 static DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors,
 221                          NULL, irq_mask_registers, irq_prio_registers,
 222                          irq_sense_registers);
 223
 224 /* External interrupt pins in IRL mode */
 225
 226 static struct intc_vect irl_vectors[] __initdata = {
 227         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 228         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 229         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 230         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 231         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 232         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 233         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 234         INTC_VECT(IRL_HHHL, 0x3c0),
 235 };
 236
 237 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 238         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 239           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 240             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 241             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 242             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 243 };
 244
 245 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 246         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 247           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 248             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 249             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 250             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 251             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 252 };
 253
 254 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
 255                          NULL, irl7654_mask_registers, NULL, NULL);
 256
 257 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 258                          NULL, irl3210_mask_registers, NULL, NULL);
 259
 260 #define INTC_ICR0       0xffd00000
 261 #define INTC_INTMSK0    0xffd00044
 262 #define INTC_INTMSK1    0xffd00048
 263 #define INTC_INTMSK2    0xffd40080
 264 #define INTC_INTMSKCLR1 0xffd00068
 265 #define INTC_INTMSKCLR2 0xffd40084
 266
 267 void __init plat_irq_setup(void)
 268 {
 269         /* disable IRQ7-0 */
 270         ctrl_outl(0xff000000, INTC_INTMSK0);
 271
 272         /* disable IRL3-0 + IRL7-4 */
 273         ctrl_outl(0xc0000000, INTC_INTMSK1);
 274         ctrl_outl(0xfffefffe, INTC_INTMSK2);
 275
 276         /* select IRL mode for IRL3-0 + IRL7-4 */
 277         ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 278
 279         /* disable holding function, ie enable "SH-4 Mode" */
 280         ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 281
 282         register_intc_controller(&intc_desc);
 283 }
 284
 285 void __init plat_irq_setup_pins(int mode)
 286 {
 287         switch (mode) {
 288         case IRQ_MODE_IRQ:
 289                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 290                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 291                 register_intc_controller(&intc_irq_desc);
 292                 break;
 293         case IRQ_MODE_IRL7654:
 294                 /* enable IRL7-4 but don't provide any masking */
 295                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 296                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
 297                 break;
 298         case IRQ_MODE_IRL3210:
 299                 /* enable IRL0-3 but don't provide any masking */
 300                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 301                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
 302                 break;
 303         case IRQ_MODE_IRL7654_MASK:
 304                 /* enable IRL7-4 and mask using cpu intc controller */
 305                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 306                 register_intc_controller(&intc_irl7654_desc);
 307                 break;
 308         case IRQ_MODE_IRL3210_MASK:
 309                 /* enable IRL0-3 and mask using cpu intc controller */
 310                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 311                 register_intc_controller(&intc_irl3210_desc);
 312                 break;
 313         default:
 314                 BUG();
 315         }
 316 }