drivers/net/wan/c101.c

   1 /*
   2  * Moxa C101 synchronous serial card driver for Linux
   3  *
   4  * Copyright (C) 2000-2003 Krzysztof Halasa <khc@pm.waw.pl>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License
   8  * as published by the Free Software Foundation.
   9  *
  10  * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>
  11  *
  12  * Sources of information:
  13  *    Hitachi HD64570 SCA User's Manual
  14  *    Moxa C101 User's Manual
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/slab.h>
  20 #include <linux/types.h>
  21 #include <linux/string.h>
  22 #include <linux/errno.h>
  23 #include <linux/init.h>
  24 #include <linux/moduleparam.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/hdlc.h>
  27 #include <linux/delay.h>
  28 #include <asm/io.h>
  29
  30 #include "hd64570.h"
  31
  32
  33 static const char* version = "Moxa C101 driver version: 1.15";
  34 static const char* devname = "C101";
  35
  36 #undef DEBUG_PKT
  37 #define DEBUG_RINGS
  38
  39 #define C101_PAGE 0x1D00
  40 #define C101_DTR 0x1E00
  41 #define C101_SCA 0x1F00
  42 #define C101_WINDOW_SIZE 0x2000
  43 #define C101_MAPPED_RAM_SIZE 0x4000
  44
  45 #define RAM_SIZE (256 * 1024)
  46 #define TX_RING_BUFFERS 10
  47 #define RX_RING_BUFFERS ((RAM_SIZE - C101_WINDOW_SIZE) /                \
  48                          (sizeof(pkt_desc) + HDLC_MAX_MRU) - TX_RING_BUFFERS)
  49
  50 #define CLOCK_BASE 9830400      /* 9.8304 MHz */
  51 #define PAGE0_ALWAYS_MAPPED
  52
  53 static char *hw;                /* pointer to hw=xxx command line string */
  54
  55
  56 typedef struct card_s {
  57         struct net_device *dev;
  58         spinlock_t lock;        /* TX lock */
  59         u8 __iomem *win0base;   /* ISA window base address */
  60         u32 phy_winbase;        /* ISA physical base address */
  61         sync_serial_settings settings;
  62         int rxpart;             /* partial frame received, next frame invalid*/
  63         unsigned short encoding;
  64         unsigned short parity;
  65         u16 rx_ring_buffers;    /* number of buffers in a ring */
  66         u16 tx_ring_buffers;
  67         u16 buff_offset;        /* offset of first buffer of first channel */
  68         u16 rxin;               /* rx ring buffer 'in' pointer */
  69         u16 txin;               /* tx ring buffer 'in' and 'last' pointers */
  70         u16 txlast;
  71         u8 rxs, txs, tmc;       /* SCA registers */
  72         u8 irq;                 /* IRQ (3-15) */
  73         u8 page;
  74
  75         struct card_s *next_card;
  76 }card_t;
  77
  78 typedef card_t port_t;
  79
  80 static card_t *first_card;
  81 static card_t **new_card = &first_card;
  82
  83
  84 #define sca_in(reg, card)          readb((card)->win0base + C101_SCA + (reg))
  85 #define sca_out(value, reg, card)  writeb(value, (card)->win0base + C101_SCA + (reg))
  86 #define sca_inw(reg, card)         readw((card)->win0base + C101_SCA + (reg))
  87
  88 /* EDA address register must be set in EDAL, EDAH order - 8 bit ISA bus */
  89 #define sca_outw(value, reg, card) do { \
  90         writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \
  91         writeb((value >> 8 ) & 0xFF, (card)->win0base + C101_SCA + (reg + 1));\
  92 } while(0)
  93
  94 #define port_to_card(port)         (port)
  95 #define log_node(port)             (0)
  96 #define phy_node(port)             (0)
  97 #define winsize(card)              (C101_WINDOW_SIZE)
  98 #define win0base(card)             ((card)->win0base)
  99 #define winbase(card)              ((card)->win0base + 0x2000)
 100 #define get_port(card, port)       (card)
 101 static void sca_msci_intr(port_t *port);
 102
 103
 104 static inline u8 sca_get_page(card_t *card)
 105 {
 106         return card->page;
 107 }
 108
 109 static inline void openwin(card_t *card, u8 page)
 110 {
 111         card->page = page;
 112         writeb(page, card->win0base + C101_PAGE);
 113 }
 114
 115
 116 #include "hd64570.c"
 117
 118
 119 static inline void set_carrier(port_t *port)
 120 {
 121         if (!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD))
 122                 netif_carrier_on(port_to_dev(port));
 123         else
 124                 netif_carrier_off(port_to_dev(port));
 125 }
 126
 127
 128 static void sca_msci_intr(port_t *port)
 129 {
 130         u8 stat = sca_in(MSCI0_OFFSET + ST1, port); /* read MSCI ST1 status */
 131
 132         /* Reset MSCI TX underrun and CDCD (ignored) status bit */
 133         sca_out(stat & (ST1_UDRN | ST1_CDCD), MSCI0_OFFSET + ST1, port);
 134
 135         if (stat & ST1_UDRN) {
 136                 /* TX Underrun error detected */
 137                 port_to_dev(port)->stats.tx_errors++;
 138                 port_to_dev(port)->stats.tx_fifo_errors++;
 139         }
 140
 141         stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI1 ST1 status */
 142         /* Reset MSCI CDCD status bit - uses ch#2 DCD input */
 143         sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port);
 144
 145         if (stat & ST1_CDCD)
 146                 set_carrier(port);
 147 }
 148
 149
 150 static void c101_set_iface(port_t *port)
 151 {
 152         u8 rxs = port->rxs & CLK_BRG_MASK;
 153         u8 txs = port->txs & CLK_BRG_MASK;
 154
 155         switch(port->settings.clock_type) {
 156         case CLOCK_INT:
 157                 rxs |= CLK_BRG_RX; /* TX clock */
 158                 txs |= CLK_RXCLK_TX; /* BRG output */
 159                 break;
 160
 161         case CLOCK_TXINT:
 162                 rxs |= CLK_LINE_RX; /* RXC input */
 163                 txs |= CLK_BRG_TX; /* BRG output */
 164                 break;
 165
 166         case CLOCK_TXFROMRX:
 167                 rxs |= CLK_LINE_RX; /* RXC input */
 168                 txs |= CLK_RXCLK_TX; /* RX clock */
 169                 break;
 170
 171         default:        /* EXTernal clock */
 172                 rxs |= CLK_LINE_RX; /* RXC input */
 173                 txs |= CLK_LINE_TX; /* TXC input */
 174         }
 175
 176         port->rxs = rxs;
 177         port->txs = txs;
 178         sca_out(rxs, MSCI1_OFFSET + RXS, port);
 179         sca_out(txs, MSCI1_OFFSET + TXS, port);
 180         sca_set_port(port);
 181 }
 182
 183
 184 static int c101_open(struct net_device *dev)
 185 {
 186         port_t *port = dev_to_port(dev);
 187         int result;
 188
 189         result = hdlc_open(dev);
 190         if (result)
 191                 return result;
 192
 193         writeb(1, port->win0base + C101_DTR);
 194         sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */
 195         sca_open(dev);
 196         /* DCD is connected to port 2 !@#$%^& - disable MSCI0 CDCD interrupt */
 197         sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);
 198         sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);
 199
 200         set_carrier(port);
 201
 202         /* enable MSCI1 CDCD interrupt */
 203         sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);
 204         sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port);
 205         sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */
 206         c101_set_iface(port);
 207         return 0;
 208 }
 209
 210
 211 static int c101_close(struct net_device *dev)
 212 {
 213         port_t *port = dev_to_port(dev);
 214
 215         sca_close(dev);
 216         writeb(0, port->win0base + C101_DTR);
 217         sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);
 218         hdlc_close(dev);
 219         return 0;
 220 }
 221
 222
 223 static int c101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 224 {
 225         const size_t size = sizeof(sync_serial_settings);
 226         sync_serial_settings new_line;
 227         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
 228         port_t *port = dev_to_port(dev);
 229
 230 #ifdef DEBUG_RINGS
 231         if (cmd == SIOCDEVPRIVATE) {
 232                 sca_dump_rings(dev);
 233                 printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n",
 234                        sca_in(MSCI1_OFFSET + ST0, port),
 235                        sca_in(MSCI1_OFFSET + ST1, port),
 236                        sca_in(MSCI1_OFFSET + ST2, port),
 237                        sca_in(MSCI1_OFFSET + ST3, port));
 238                 return 0;
 239         }
 240 #endif
 241         if (cmd != SIOCWANDEV)
 242                 return hdlc_ioctl(dev, ifr, cmd);
 243
 244         switch(ifr->ifr_settings.type) {
 245         case IF_GET_IFACE:
 246                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
 247                 if (ifr->ifr_settings.size < size) {
 248                         ifr->ifr_settings.size = size; /* data size wanted */
 249                         return -ENOBUFS;
 250                 }
 251                 if (copy_to_user(line, &port->settings, size))
 252                         return -EFAULT;
 253                 return 0;
 254
 255         case IF_IFACE_SYNC_SERIAL:
 256                 if(!capable(CAP_NET_ADMIN))
 257                         return -EPERM;
 258
 259                 if (copy_from_user(&new_line, line, size))
 260                         return -EFAULT;
 261
 262                 if (new_line.clock_type != CLOCK_EXT &&
 263                     new_line.clock_type != CLOCK_TXFROMRX &&
 264                     new_line.clock_type != CLOCK_INT &&
 265                     new_line.clock_type != CLOCK_TXINT)
 266                 return -EINVAL; /* No such clock setting */
 267
 268                 if (new_line.loopback != 0 && new_line.loopback != 1)
 269                         return -EINVAL;
 270
 271                 memcpy(&port->settings, &new_line, size); /* Update settings */
 272                 c101_set_iface(port);
 273                 return 0;
 274
 275         default:
 276                 return hdlc_ioctl(dev, ifr, cmd);
 277         }
 278 }
 279
 280
 281
 282 static void c101_destroy_card(card_t *card)
 283 {
 284         readb(card->win0base + C101_PAGE); /* Resets SCA? */
 285
 286         if (card->irq)
 287                 free_irq(card->irq, card);
 288
 289         if (card->win0base) {
 290                 iounmap(card->win0base);
 291                 release_mem_region(card->phy_winbase, C101_MAPPED_RAM_SIZE);
 292         }
 293
 294         free_netdev(card->dev);
 295
 296         kfree(card);
 297 }
 298
 299 static const struct net_device_ops c101_ops = {
 300         .ndo_open       = c101_open,
 301         .ndo_stop       = c101_close,
 302         .ndo_change_mtu = hdlc_change_mtu,
 303         .ndo_start_xmit = hdlc_start_xmit,
 304         .ndo_do_ioctl   = c101_ioctl,
 305 };
 306
 307 static int __init c101_run(unsigned long irq, unsigned long winbase)
 308 {
 309         struct net_device *dev;
 310         hdlc_device *hdlc;
 311         card_t *card;
 312         int result;
 313
 314         if (irq<3 || irq>15 || irq == 6) /* FIXME */ {
 315                 printk(KERN_ERR "c101: invalid IRQ value\n");
 316                 return -ENODEV;
 317         }
 318
 319         if (winbase < 0xC0000 || winbase > 0xDFFFF || (winbase & 0x3FFF) !=0) {
 320                 printk(KERN_ERR "c101: invalid RAM value\n");
 321                 return -ENODEV;
 322         }
 323
 324         card = kzalloc(sizeof(card_t), GFP_KERNEL);
 325         if (card == NULL) {
 326                 printk(KERN_ERR "c101: unable to allocate memory\n");
 327                 return -ENOBUFS;
 328         }
 329
 330         card->dev = alloc_hdlcdev(card);
 331         if (!card->dev) {
 332                 printk(KERN_ERR "c101: unable to allocate memory\n");
 333                 kfree(card);
 334                 return -ENOBUFS;
 335         }
 336
 337         if (request_irq(irq, sca_intr, 0, devname, card)) {
 338                 printk(KERN_ERR "c101: could not allocate IRQ\n");
 339                 c101_destroy_card(card);
 340                 return -EBUSY;
 341         }
 342         card->irq = irq;
 343
 344         if (!request_mem_region(winbase, C101_MAPPED_RAM_SIZE, devname)) {
 345                 printk(KERN_ERR "c101: could not request RAM window\n");
 346                 c101_destroy_card(card);
 347                 return -EBUSY;
 348         }
 349         card->phy_winbase = winbase;
 350         card->win0base = ioremap(winbase, C101_MAPPED_RAM_SIZE);
 351         if (!card->win0base) {
 352                 printk(KERN_ERR "c101: could not map I/O address\n");
 353                 c101_destroy_card(card);
 354                 return -EFAULT;
 355         }
 356
 357         card->tx_ring_buffers = TX_RING_BUFFERS;
 358         card->rx_ring_buffers = RX_RING_BUFFERS;
 359         card->buff_offset = C101_WINDOW_SIZE; /* Bytes 1D00-1FFF reserved */
 360
 361         readb(card->win0base + C101_PAGE); /* Resets SCA? */
 362         udelay(100);
 363         writeb(0, card->win0base + C101_PAGE);
 364         writeb(0, card->win0base + C101_DTR); /* Power-up for RAM? */
 365
 366         sca_init(card, 0);
 367
 368         dev = port_to_dev(card);
 369         hdlc = dev_to_hdlc(dev);
 370
 371         spin_lock_init(&card->lock);
 372         dev->irq = irq;
 373         dev->mem_start = winbase;
 374         dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1;
 375         dev->tx_queue_len = 50;
 376         dev->netdev_ops = &c101_ops;
 377         hdlc->attach = sca_attach;
 378         hdlc->xmit = sca_xmit;
 379         card->settings.clock_type = CLOCK_EXT;
 380
 381         result = register_hdlc_device(dev);
 382         if (result) {
 383                 printk(KERN_WARNING "c101: unable to register hdlc device\n");
 384                 c101_destroy_card(card);
 385                 return result;
 386         }
 387
 388         sca_init_port(card); /* Set up C101 memory */
 389         set_carrier(card);
 390
 391         printk(KERN_INFO "%s: Moxa C101 on IRQ%u,"
 392                " using %u TX + %u RX packets rings\n",
 393                dev->name, card->irq,
 394                card->tx_ring_buffers, card->rx_ring_buffers);
 395
 396         *new_card = card;
 397         new_card = &card->next_card;
 398         return 0;
 399 }
 400
 401
 402
 403 static int __init c101_init(void)
 404 {
 405         if (hw == NULL) {
 406 #ifdef MODULE
 407                 printk(KERN_INFO "c101: no card initialized\n");
 408 #endif
 409                 return -EINVAL; /* no parameters specified, abort */
 410         }
 411
 412         printk(KERN_INFO "%s\n", version);
 413
 414         do {
 415                 unsigned long irq, ram;
 416
 417                 irq = simple_strtoul(hw, &hw, 0);
 418
 419                 if (*hw++ != ',')
 420                         break;
 421                 ram = simple_strtoul(hw, &hw, 0);
 422
 423                 if (*hw == ':' || *hw == '\x0')
 424                         c101_run(irq, ram);
 425
 426                 if (*hw == '\x0')
 427                         return first_card ? 0 : -EINVAL;
 428         }while(*hw++ == ':');
 429
 430         printk(KERN_ERR "c101: invalid hardware parameters\n");
 431         return first_card ? 0 : -EINVAL;
 432 }
 433
 434
 435 static void __exit c101_cleanup(void)
 436 {
 437         card_t *card = first_card;
 438
 439         while (card) {
 440                 card_t *ptr = card;
 441                 card = card->next_card;
 442                 unregister_hdlc_device(port_to_dev(ptr));
 443                 c101_destroy_card(ptr);
 444         }
 445 }
 446
 447
 448 module_init(c101_init);
 449 module_exit(c101_cleanup);
 450
 451 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
 452 MODULE_DESCRIPTION("Moxa C101 serial port driver");
 453 MODULE_LICENSE("GPL v2");
 454 module_param(hw, charp, 0444);
 455 MODULE_PARM_DESC(hw, "irq,ram:irq,...");