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jbd2: Annotate transaction start also for jbd2_journal_restart()
[linux/fpc-iii.git] / drivers / net / wan / farsync.c
blob3e90eb816181b508ee2c4e151206a72eb4eafbe7
1 /*
2 * FarSync WAN driver for Linux (2.6.x kernel version)
3 *
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
5 *
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
7 * www.farsite.co.uk
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk>
15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/version.h>
21 #include <linux/pci.h>
22 #include <linux/ioport.h>
23 #include <linux/init.h>
24 #include <linux/if.h>
25 #include <linux/hdlc.h>
26 #include <asm/io.h>
27 #include <asm/uaccess.h>
28
29 #include "farsync.h"
30
31 /*
32 * Module info
33 */
34 MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>");
35 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
36 MODULE_LICENSE("GPL");
37
38 /* Driver configuration and global parameters
39 * ==========================================
40 */
41
42 /* Number of ports (per card) and cards supported
43 */
44 #define FST_MAX_PORTS 4
45 #define FST_MAX_CARDS 32
46
47 /* Default parameters for the link
48 */
49 #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
50 * useful */
51 #define FST_TXQ_DEPTH 16 /* This one is for the buffering
52 * of frames on the way down to the card
53 * so that we can keep the card busy
54 * and maximise throughput
55 */
56 #define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
57 * network layer */
58 #define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
59 * control from network layer */
60 #define FST_MAX_MTU 8000 /* Huge but possible */
61 #define FST_DEF_MTU 1500 /* Common sane value */
62
63 #define FST_TX_TIMEOUT (2*HZ)
64
65 #ifdef ARPHRD_RAWHDLC
66 #define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
67 #else
68 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
69 #endif
70
71 /*
72 * Modules parameters and associated variables
73 */
74 static int fst_txq_low = FST_LOW_WATER_MARK;
75 static int fst_txq_high = FST_HIGH_WATER_MARK;
76 static int fst_max_reads = 7;
77 static int fst_excluded_cards = 0;
78 static int fst_excluded_list[FST_MAX_CARDS];
79
80 module_param(fst_txq_low, int, 0);
81 module_param(fst_txq_high, int, 0);
82 module_param(fst_max_reads, int, 0);
83 module_param(fst_excluded_cards, int, 0);
84 module_param_array(fst_excluded_list, int, NULL, 0);
85
86 /* Card shared memory layout
87 * =========================
88 */
89 #pragma pack(1)
90
91 /* This information is derived in part from the FarSite FarSync Smc.h
92 * file. Unfortunately various name clashes and the non-portability of the
93 * bit field declarations in that file have meant that I have chosen to
94 * recreate the information here.
95 *
96 * The SMC (Shared Memory Configuration) has a version number that is
97 * incremented every time there is a significant change. This number can
98 * be used to check that we have not got out of step with the firmware
99 * contained in the .CDE files.
100 */
101 #define SMC_VERSION 24
102
103 #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
104
105 #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
106 * configuration structure */
107 #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
108 * buffers */
109
110 #define LEN_TX_BUFFER 8192 /* Size of packet buffers */
111 #define LEN_RX_BUFFER 8192
112
113 #define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
114 #define LEN_SMALL_RX_BUFFER 256
115
116 #define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
117 #define NUM_RX_BUFFER 8
118
119 /* Interrupt retry time in milliseconds */
120 #define INT_RETRY_TIME 2
121
122 /* The Am186CH/CC processors support a SmartDMA mode using circular pools
123 * of buffer descriptors. The structure is almost identical to that used
124 * in the LANCE Ethernet controllers. Details available as PDF from the
125 * AMD web site: http://www.amd.com/products/epd/processors/\
126 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf
127 */
128 struct txdesc { /* Transmit descriptor */
129 volatile u16 ladr; /* Low order address of packet. This is a
130 * linear address in the Am186 memory space
131 */
132 volatile u8 hadr; /* High order address. Low 4 bits only, high 4
133 * bits must be zero
134 */
135 volatile u8 bits; /* Status and config */
136 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits.
137 * Transmit terminal count interrupt enable in
138 * top bit.
139 */
140 u16 unused; /* Not used in Tx */
141 };
142
143 struct rxdesc { /* Receive descriptor */
144 volatile u16 ladr; /* Low order address of packet */
145 volatile u8 hadr; /* High order address */
146 volatile u8 bits; /* Status and config */
147 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits.
148 * Receive terminal count interrupt enable in
149 * top bit.
150 */
151 volatile u16 mcnt; /* Message byte count (15 bits) */
152 };
153
154 /* Convert a length into the 15 bit 2's complement */
155 /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
156 /* Since we need to set the high bit to enable the completion interrupt this
157 * can be made a lot simpler
158 */
159 #define cnv_bcnt(len) (-(len))
160
161 /* Status and config bits for the above */
162 #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
163 #define TX_STP 0x02 /* Tx: start of packet */
164 #define TX_ENP 0x01 /* Tx: end of packet */
165 #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
166 #define RX_FRAM 0x20 /* Rx: framing error */
167 #define RX_OFLO 0x10 /* Rx: overflow error */
168 #define RX_CRC 0x08 /* Rx: CRC error */
169 #define RX_HBUF 0x04 /* Rx: buffer error */
170 #define RX_STP 0x02 /* Rx: start of packet */
171 #define RX_ENP 0x01 /* Rx: end of packet */
172
173 /* Interrupts from the card are caused by various events which are presented
174 * in a circular buffer as several events may be processed on one physical int
175 */
176 #define MAX_CIRBUFF 32
177
178 struct cirbuff {
179 u8 rdindex; /* read, then increment and wrap */
180 u8 wrindex; /* write, then increment and wrap */
181 u8 evntbuff[MAX_CIRBUFF];
182 };
183
184 /* Interrupt event codes.
185 * Where appropriate the two low order bits indicate the port number
186 */
187 #define CTLA_CHG 0x18 /* Control signal changed */
188 #define CTLB_CHG 0x19
189 #define CTLC_CHG 0x1A
190 #define CTLD_CHG 0x1B
191
192 #define INIT_CPLT 0x20 /* Initialisation complete */
193 #define INIT_FAIL 0x21 /* Initialisation failed */
194
195 #define ABTA_SENT 0x24 /* Abort sent */
196 #define ABTB_SENT 0x25
197 #define ABTC_SENT 0x26
198 #define ABTD_SENT 0x27
199
200 #define TXA_UNDF 0x28 /* Transmission underflow */
201 #define TXB_UNDF 0x29
202 #define TXC_UNDF 0x2A
203 #define TXD_UNDF 0x2B
204
205 #define F56_INT 0x2C
206 #define M32_INT 0x2D
207
208 #define TE1_ALMA 0x30
209
210 /* Port physical configuration. See farsync.h for field values */
211 struct port_cfg {
212 u16 lineInterface; /* Physical interface type */
213 u8 x25op; /* Unused at present */
214 u8 internalClock; /* 1 => internal clock, 0 => external */
215 u8 transparentMode; /* 1 => on, 0 => off */
216 u8 invertClock; /* 0 => normal, 1 => inverted */
217 u8 padBytes[6]; /* Padding */
218 u32 lineSpeed; /* Speed in bps */
219 };
220
221 /* TE1 port physical configuration */
222 struct su_config {
223 u32 dataRate;
224 u8 clocking;
225 u8 framing;
226 u8 structure;
227 u8 interface;
228 u8 coding;
229 u8 lineBuildOut;
230 u8 equalizer;
231 u8 transparentMode;
232 u8 loopMode;
233 u8 range;
234 u8 txBufferMode;
235 u8 rxBufferMode;
236 u8 startingSlot;
237 u8 losThreshold;
238 u8 enableIdleCode;
239 u8 idleCode;
240 u8 spare[44];
241 };
242
243 /* TE1 Status */
244 struct su_status {
245 u32 receiveBufferDelay;
246 u32 framingErrorCount;
247 u32 codeViolationCount;
248 u32 crcErrorCount;
249 u32 lineAttenuation;
250 u8 portStarted;
251 u8 lossOfSignal;
252 u8 receiveRemoteAlarm;
253 u8 alarmIndicationSignal;
254 u8 spare[40];
255 };
256
257 /* Finally sling all the above together into the shared memory structure.
258 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
259 * evolving under NT for some time so I guess we're stuck with it.
260 * The structure starts at offset SMC_BASE.
261 * See farsync.h for some field values.
262 */
263 struct fst_shared {
264 /* DMA descriptor rings */
265 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];
266 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];
267
268 /* Obsolete small buffers */
269 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];
270 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];
271
272 u8 taskStatus; /* 0x00 => initialising, 0x01 => running,
273 * 0xFF => halted
274 */
275
276 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,
277 * set to 0xEE by host to acknowledge interrupt
278 */
279
280 u16 smcVersion; /* Must match SMC_VERSION */
281
282 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major
283 * version, RR = revision and BB = build
284 */
285
286 u16 txa_done; /* Obsolete completion flags */
287 u16 rxa_done;
288 u16 txb_done;
289 u16 rxb_done;
290 u16 txc_done;
291 u16 rxc_done;
292 u16 txd_done;
293 u16 rxd_done;
294
295 u16 mailbox[4]; /* Diagnostics mailbox. Not used */
296
297 struct cirbuff interruptEvent; /* interrupt causes */
298
299 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */
300 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */
301
302 struct port_cfg portConfig[FST_MAX_PORTS];
303
304 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */
305
306 u16 cableStatus; /* lsb: 0=> present, 1=> absent */
307
308 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */
309 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */
310
311 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */
312 u16 cardMailbox[4]; /* Not used */
313
314 /* Number of times the card thinks the host has
315 * missed an interrupt by not acknowledging
316 * within 2mS (I guess NT has problems)
317 */
318 u32 interruptRetryCount;
319
320 /* Driver private data used as an ID. We'll not
321 * use this as I'd rather keep such things
322 * in main memory rather than on the PCI bus
323 */
324 u32 portHandle[FST_MAX_PORTS];
325
326 /* Count of Tx underflows for stats */
327 u32 transmitBufferUnderflow[FST_MAX_PORTS];
328
329 /* Debounced V.24 control input status */
330 u32 v24DebouncedSts[FST_MAX_PORTS];
331
332 /* Adapter debounce timers. Don't touch */
333 u32 ctsTimer[FST_MAX_PORTS];
334 u32 ctsTimerRun[FST_MAX_PORTS];
335 u32 dcdTimer[FST_MAX_PORTS];
336 u32 dcdTimerRun[FST_MAX_PORTS];
337
338 u32 numberOfPorts; /* Number of ports detected at startup */
339
340 u16 _reserved[64];
341
342 u16 cardMode; /* Bit-mask to enable features:
343 * Bit 0: 1 enables LED identify mode
344 */
345
346 u16 portScheduleOffset;
347
348 struct su_config suConfig; /* TE1 Bits */
349 struct su_status suStatus;
350
351 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of
352 * the structure and marks the end of shared
353 * memory. Adapter code initializes it as
354 * END_SIG.
355 */
356 };
357
358 /* endOfSmcSignature value */
359 #define END_SIG 0x12345678
360
361 /* Mailbox values. (portMailbox) */
362 #define NOP 0 /* No operation */
363 #define ACK 1 /* Positive acknowledgement to PC driver */
364 #define NAK 2 /* Negative acknowledgement to PC driver */
365 #define STARTPORT 3 /* Start an HDLC port */
366 #define STOPPORT 4 /* Stop an HDLC port */
367 #define ABORTTX 5 /* Abort the transmitter for a port */
368 #define SETV24O 6 /* Set V24 outputs */
369
370 /* PLX Chip Register Offsets */
371 #define CNTRL_9052 0x50 /* Control Register */
372 #define CNTRL_9054 0x6c /* Control Register */
373
374 #define INTCSR_9052 0x4c /* Interrupt control/status register */
375 #define INTCSR_9054 0x68 /* Interrupt control/status register */
376
377 /* 9054 DMA Registers */
378 /*
379 * Note that we will be using DMA Channel 0 for copying rx data
380 * and Channel 1 for copying tx data
381 */
382 #define DMAMODE0 0x80
383 #define DMAPADR0 0x84
384 #define DMALADR0 0x88
385 #define DMASIZ0 0x8c
386 #define DMADPR0 0x90
387 #define DMAMODE1 0x94
388 #define DMAPADR1 0x98
389 #define DMALADR1 0x9c
390 #define DMASIZ1 0xa0
391 #define DMADPR1 0xa4
392 #define DMACSR0 0xa8
393 #define DMACSR1 0xa9
394 #define DMAARB 0xac
395 #define DMATHR 0xb0
396 #define DMADAC0 0xb4
397 #define DMADAC1 0xb8
398 #define DMAMARBR 0xac
399
400 #define FST_MIN_DMA_LEN 64
401 #define FST_RX_DMA_INT 0x01
402 #define FST_TX_DMA_INT 0x02
403 #define FST_CARD_INT 0x04
404
405 /* Larger buffers are positioned in memory at offset BFM_BASE */
406 struct buf_window {
407 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];
408 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];
409 };
410
411 /* Calculate offset of a buffer object within the shared memory window */
412 #define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))
413
414 #pragma pack()
415
416 /* Device driver private information
417 * =================================
418 */
419 /* Per port (line or channel) information
420 */
421 struct fst_port_info {
422 struct net_device *dev; /* Device struct - must be first */
423 struct fst_card_info *card; /* Card we're associated with */
424 int index; /* Port index on the card */
425 int hwif; /* Line hardware (lineInterface copy) */
426 int run; /* Port is running */
427 int mode; /* Normal or FarSync raw */
428 int rxpos; /* Next Rx buffer to use */
429 int txpos; /* Next Tx buffer to use */
430 int txipos; /* Next Tx buffer to check for free */
431 int start; /* Indication of start/stop to network */
432 /*
433 * A sixteen entry transmit queue
434 */
435 int txqs; /* index to get next buffer to tx */
436 int txqe; /* index to queue next packet */
437 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */
438 int rxqdepth;
439 };
440
441 /* Per card information
442 */
443 struct fst_card_info {
444 char __iomem *mem; /* Card memory mapped to kernel space */
445 char __iomem *ctlmem; /* Control memory for PCI cards */
446 unsigned int phys_mem; /* Physical memory window address */
447 unsigned int phys_ctlmem; /* Physical control memory address */
448 unsigned int irq; /* Interrupt request line number */
449 unsigned int nports; /* Number of serial ports */
450 unsigned int type; /* Type index of card */
451 unsigned int state; /* State of card */
452 spinlock_t card_lock; /* Lock for SMP access */
453 unsigned short pci_conf; /* PCI card config in I/O space */
454 /* Per port info */
455 struct fst_port_info ports[FST_MAX_PORTS];
456 struct pci_dev *device; /* Information about the pci device */
457 int card_no; /* Inst of the card on the system */
458 int family; /* TxP or TxU */
459 int dmarx_in_progress;
460 int dmatx_in_progress;
461 unsigned long int_count;
462 unsigned long int_time_ave;
463 void *rx_dma_handle_host;
464 dma_addr_t rx_dma_handle_card;
465 void *tx_dma_handle_host;
466 dma_addr_t tx_dma_handle_card;
467 struct sk_buff *dma_skb_rx;
468 struct fst_port_info *dma_port_rx;
469 struct fst_port_info *dma_port_tx;
470 int dma_len_rx;
471 int dma_len_tx;
472 int dma_txpos;
473 int dma_rxpos;
474 };
475
476 /* Convert an HDLC device pointer into a port info pointer and similar */
477 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
478 #define port_to_dev(P) ((P)->dev)
479
480
481 /*
482 * Shared memory window access macros
483 *
484 * We have a nice memory based structure above, which could be directly
485 * mapped on i386 but might not work on other architectures unless we use
486 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take
487 * physical offsets so we have to convert. The only saving grace is that
488 * this should all collapse back to a simple indirection eventually.
489 */
490 #define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
491
492 #define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E))
493 #define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E))
494 #define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E))
495
496 #define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E))
497 #define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E))
498 #define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E))
499
500 /*
501 * Debug support
502 */
503 #if FST_DEBUG
504
505 static int fst_debug_mask = { FST_DEBUG };
506
507 /* Most common debug activity is to print something if the corresponding bit
508 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
509 * support variable numbers of macro parameters. The inverted if prevents us
510 * eating someone else's else clause.
511 */
512 #define dbg(F,fmt,A...) if ( ! ( fst_debug_mask & (F))) \
513 ; \
514 else \
515 printk ( KERN_DEBUG FST_NAME ": " fmt, ## A )
516
517 #else
518 #define dbg(X...) /* NOP */
519 #endif
520
521 /* Printing short cuts
522 */
523 #define printk_err(fmt,A...) printk ( KERN_ERR FST_NAME ": " fmt, ## A )
524 #define printk_warn(fmt,A...) printk ( KERN_WARNING FST_NAME ": " fmt, ## A )
525 #define printk_info(fmt,A...) printk ( KERN_INFO FST_NAME ": " fmt, ## A )
526
527 /*
528 * PCI ID lookup table
529 */
530 static struct pci_device_id fst_pci_dev_id[] __devinitdata = {
531 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID,
532 PCI_ANY_ID, 0, 0, FST_TYPE_T2P},
533
534 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID,
535 PCI_ANY_ID, 0, 0, FST_TYPE_T4P},
536
537 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID,
538 PCI_ANY_ID, 0, 0, FST_TYPE_T1U},
539
540 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID,
541 PCI_ANY_ID, 0, 0, FST_TYPE_T2U},
542
543 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID,
544 PCI_ANY_ID, 0, 0, FST_TYPE_T4U},
545
546 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID,
547 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
548
549 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID,
550 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
551 {0,} /* End */
552 };
553
554 MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);
555
556 /*
557 * Device Driver Work Queues
558 *
559 * So that we don't spend too much time processing events in the
560 * Interrupt Service routine, we will declare a work queue per Card
561 * and make the ISR schedule a task in the queue for later execution.
562 * In the 2.4 Kernel we used to use the immediate queue for BH's
563 * Now that they are gone, tasklets seem to be much better than work
564 * queues.
565 */
566
567 static void do_bottom_half_tx(struct fst_card_info *card);
568 static void do_bottom_half_rx(struct fst_card_info *card);
569 static void fst_process_tx_work_q(unsigned long work_q);
570 static void fst_process_int_work_q(unsigned long work_q);
571
572 static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0);
573 static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0);
574
575 static struct fst_card_info *fst_card_array[FST_MAX_CARDS];
576 static spinlock_t fst_work_q_lock;
577 static u64 fst_work_txq;
578 static u64 fst_work_intq;
579
580 static void
581 fst_q_work_item(u64 * queue, int card_index)
582 {
583 unsigned long flags;
584 u64 mask;
585
586 /*
587 * Grab the queue exclusively
588 */
589 spin_lock_irqsave(&fst_work_q_lock, flags);
590
591 /*
592 * Making an entry in the queue is simply a matter of setting
593 * a bit for the card indicating that there is work to do in the
594 * bottom half for the card. Note the limitation of 64 cards.
595 * That ought to be enough
596 */
597 mask = 1 << card_index;
598 *queue |= mask;
599 spin_unlock_irqrestore(&fst_work_q_lock, flags);
600 }
601
602 static void
603 fst_process_tx_work_q(unsigned long /*void **/work_q)
604 {
605 unsigned long flags;
606 u64 work_txq;
607 int i;
608
609 /*
610 * Grab the queue exclusively
611 */
612 dbg(DBG_TX, "fst_process_tx_work_q\n");
613 spin_lock_irqsave(&fst_work_q_lock, flags);
614 work_txq = fst_work_txq;
615 fst_work_txq = 0;
616 spin_unlock_irqrestore(&fst_work_q_lock, flags);
617
618 /*
619 * Call the bottom half for each card with work waiting
620 */
621 for (i = 0; i < FST_MAX_CARDS; i++) {
622 if (work_txq & 0x01) {
623 if (fst_card_array[i] != NULL) {
624 dbg(DBG_TX, "Calling tx bh for card %d\n", i);
625 do_bottom_half_tx(fst_card_array[i]);
626 }
627 }
628 work_txq = work_txq >> 1;
629 }
630 }
631
632 static void
633 fst_process_int_work_q(unsigned long /*void **/work_q)
634 {
635 unsigned long flags;
636 u64 work_intq;
637 int i;
638
639 /*
640 * Grab the queue exclusively
641 */
642 dbg(DBG_INTR, "fst_process_int_work_q\n");
643 spin_lock_irqsave(&fst_work_q_lock, flags);
644 work_intq = fst_work_intq;
645 fst_work_intq = 0;
646 spin_unlock_irqrestore(&fst_work_q_lock, flags);
647
648 /*
649 * Call the bottom half for each card with work waiting
650 */
651 for (i = 0; i < FST_MAX_CARDS; i++) {
652 if (work_intq & 0x01) {
653 if (fst_card_array[i] != NULL) {
654 dbg(DBG_INTR,
655 "Calling rx & tx bh for card %d\n", i);
656 do_bottom_half_rx(fst_card_array[i]);
657 do_bottom_half_tx(fst_card_array[i]);
658 }
659 }
660 work_intq = work_intq >> 1;
661 }
662 }
663
664 /* Card control functions
665 * ======================
666 */
667 /* Place the processor in reset state
668 *
669 * Used to be a simple write to card control space but a glitch in the latest
670 * AMD Am186CH processor means that we now have to do it by asserting and de-
671 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
672 * at offset 9052_CNTRL. Note the updates for the TXU.
673 */
674 static inline void
675 fst_cpureset(struct fst_card_info *card)
676 {
677 unsigned char interrupt_line_register;
678 unsigned long j = jiffies + 1;
679 unsigned int regval;
680
681 if (card->family == FST_FAMILY_TXU) {
682 if (pci_read_config_byte
683 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
684 dbg(DBG_ASS,
685 "Error in reading interrupt line register\n");
686 }
687 /*
688 * Assert PLX software reset and Am186 hardware reset
689 * and then deassert the PLX software reset but 186 still in reset
690 */
691 outw(0x440f, card->pci_conf + CNTRL_9054 + 2);
692 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
693 /*
694 * We are delaying here to allow the 9054 to reset itself
695 */
696 j = jiffies + 1;
697 while (jiffies < j)
698 /* Do nothing */ ;
699 outw(0x240f, card->pci_conf + CNTRL_9054 + 2);
700 /*
701 * We are delaying here to allow the 9054 to reload its eeprom
702 */
703 j = jiffies + 1;
704 while (jiffies < j)
705 /* Do nothing */ ;
706 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
707
708 if (pci_write_config_byte
709 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
710 dbg(DBG_ASS,
711 "Error in writing interrupt line register\n");
712 }
713
714 } else {
715 regval = inl(card->pci_conf + CNTRL_9052);
716
717 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);
718 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);
719 }
720 }
721
722 /* Release the processor from reset
723 */
724 static inline void
725 fst_cpurelease(struct fst_card_info *card)
726 {
727 if (card->family == FST_FAMILY_TXU) {
728 /*
729 * Force posted writes to complete
730 */
731 (void) readb(card->mem);
732
733 /*
734 * Release LRESET DO = 1
735 * Then release Local Hold, DO = 1
736 */
737 outw(0x040e, card->pci_conf + CNTRL_9054 + 2);
738 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
739 } else {
740 (void) readb(card->ctlmem);
741 }
742 }
743
744 /* Clear the cards interrupt flag
745 */
746 static inline void
747 fst_clear_intr(struct fst_card_info *card)
748 {
749 if (card->family == FST_FAMILY_TXU) {
750 (void) readb(card->ctlmem);
751 } else {
752 /* Poke the appropriate PLX chip register (same as enabling interrupts)
753 */
754 outw(0x0543, card->pci_conf + INTCSR_9052);
755 }
756 }
757
758 /* Enable card interrupts
759 */
760 static inline void
761 fst_enable_intr(struct fst_card_info *card)
762 {
763 if (card->family == FST_FAMILY_TXU) {
764 outl(0x0f0c0900, card->pci_conf + INTCSR_9054);
765 } else {
766 outw(0x0543, card->pci_conf + INTCSR_9052);
767 }
768 }
769
770 /* Disable card interrupts
771 */
772 static inline void
773 fst_disable_intr(struct fst_card_info *card)
774 {
775 if (card->family == FST_FAMILY_TXU) {
776 outl(0x00000000, card->pci_conf + INTCSR_9054);
777 } else {
778 outw(0x0000, card->pci_conf + INTCSR_9052);
779 }
780 }
781
782 /* Process the result of trying to pass a received frame up the stack
783 */
784 static void
785 fst_process_rx_status(int rx_status, char *name)
786 {
787 switch (rx_status) {
788 case NET_RX_SUCCESS:
789 {
790 /*
791 * Nothing to do here
792 */
793 break;
794 }
795 case NET_RX_DROP:
796 {
797 dbg(DBG_ASS, "%s: Received packet dropped\n", name);
798 break;
799 }
800 }
801 }
802
803 /* Initilaise DMA for PLX 9054
804 */
805 static inline void
806 fst_init_dma(struct fst_card_info *card)
807 {
808 /*
809 * This is only required for the PLX 9054
810 */
811 if (card->family == FST_FAMILY_TXU) {
812 pci_set_master(card->device);
813 outl(0x00020441, card->pci_conf + DMAMODE0);
814 outl(0x00020441, card->pci_conf + DMAMODE1);
815 outl(0x0, card->pci_conf + DMATHR);
816 }
817 }
818
819 /* Tx dma complete interrupt
820 */
821 static void
822 fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
823 int len, int txpos)
824 {
825 struct net_device *dev = port_to_dev(port);
826
827 /*
828 * Everything is now set, just tell the card to go
829 */
830 dbg(DBG_TX, "fst_tx_dma_complete\n");
831 FST_WRB(card, txDescrRing[port->index][txpos].bits,
832 DMA_OWN | TX_STP | TX_ENP);
833 dev->stats.tx_packets++;
834 dev->stats.tx_bytes += len;
835 dev->trans_start = jiffies;
836 }
837
838 /*
839 * Mark it for our own raw sockets interface
840 */
841 static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev)
842 {
843 skb->dev = dev;
844 skb_reset_mac_header(skb);
845 skb->pkt_type = PACKET_HOST;
846 return htons(ETH_P_CUST);
847 }
848
849 /* Rx dma complete interrupt
850 */
851 static void
852 fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
853 int len, struct sk_buff *skb, int rxp)
854 {
855 struct net_device *dev = port_to_dev(port);
856 int pi;
857 int rx_status;
858
859 dbg(DBG_TX, "fst_rx_dma_complete\n");
860 pi = port->index;
861 memcpy(skb_put(skb, len), card->rx_dma_handle_host, len);
862
863 /* Reset buffer descriptor */
864 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
865
866 /* Update stats */
867 dev->stats.rx_packets++;
868 dev->stats.rx_bytes += len;
869
870 /* Push upstream */
871 dbg(DBG_RX, "Pushing the frame up the stack\n");
872 if (port->mode == FST_RAW)
873 skb->protocol = farsync_type_trans(skb, dev);
874 else
875 skb->protocol = hdlc_type_trans(skb, dev);
876 rx_status = netif_rx(skb);
877 fst_process_rx_status(rx_status, port_to_dev(port)->name);
878 if (rx_status == NET_RX_DROP)
879 dev->stats.rx_dropped++;
880 }
881
882 /*
883 * Receive a frame through the DMA
884 */
885 static inline void
886 fst_rx_dma(struct fst_card_info *card, unsigned char *skb,
887 unsigned char *mem, int len)
888 {
889 /*
890 * This routine will setup the DMA and start it
891 */
892
893 dbg(DBG_RX, "In fst_rx_dma %p %p %d\n", skb, mem, len);
894 if (card->dmarx_in_progress) {
895 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");
896 }
897
898 outl((unsigned long) skb, card->pci_conf + DMAPADR0); /* Copy to here */
899 outl((unsigned long) mem, card->pci_conf + DMALADR0); /* from here */
900 outl(len, card->pci_conf + DMASIZ0); /* for this length */
901 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */
902
903 /*
904 * We use the dmarx_in_progress flag to flag the channel as busy
905 */
906 card->dmarx_in_progress = 1;
907 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */
908 }
909
910 /*
911 * Send a frame through the DMA
912 */
913 static inline void
914 fst_tx_dma(struct fst_card_info *card, unsigned char *skb,
915 unsigned char *mem, int len)
916 {
917 /*
918 * This routine will setup the DMA and start it.
919 */
920
921 dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len);
922 if (card->dmatx_in_progress) {
923 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");
924 }
925
926 outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */
927 outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */
928 outl(len, card->pci_conf + DMASIZ1); /* for this length */
929 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */
930
931 /*
932 * We use the dmatx_in_progress to flag the channel as busy
933 */
934 card->dmatx_in_progress = 1;
935 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */
936 }
937
938 /* Issue a Mailbox command for a port.
939 * Note we issue them on a fire and forget basis, not expecting to see an
940 * error and not waiting for completion.
941 */
942 static void
943 fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
944 {
945 struct fst_card_info *card;
946 unsigned short mbval;
947 unsigned long flags;
948 int safety;
949
950 card = port->card;
951 spin_lock_irqsave(&card->card_lock, flags);
952 mbval = FST_RDW(card, portMailbox[port->index][0]);
953
954 safety = 0;
955 /* Wait for any previous command to complete */
956 while (mbval > NAK) {
957 spin_unlock_irqrestore(&card->card_lock, flags);
958 schedule_timeout_uninterruptible(1);
959 spin_lock_irqsave(&card->card_lock, flags);
960
961 if (++safety > 2000) {
962 printk_err("Mailbox safety timeout\n");
963 break;
964 }
965
966 mbval = FST_RDW(card, portMailbox[port->index][0]);
967 }
968 if (safety > 0) {
969 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);
970 }
971 if (mbval == NAK) {
972 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");
973 }
974
975 FST_WRW(card, portMailbox[port->index][0], cmd);
976
977 if (cmd == ABORTTX || cmd == STARTPORT) {
978 port->txpos = 0;
979 port->txipos = 0;
980 port->start = 0;
981 }
982
983 spin_unlock_irqrestore(&card->card_lock, flags);
984 }
985
986 /* Port output signals control
987 */
988 static inline void
989 fst_op_raise(struct fst_port_info *port, unsigned int outputs)
990 {
991 outputs |= FST_RDL(port->card, v24OpSts[port->index]);
992 FST_WRL(port->card, v24OpSts[port->index], outputs);
993
994 if (port->run)
995 fst_issue_cmd(port, SETV24O);
996 }
997
998 static inline void
999 fst_op_lower(struct fst_port_info *port, unsigned int outputs)
1000 {
1001 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]);
1002 FST_WRL(port->card, v24OpSts[port->index], outputs);
1003
1004 if (port->run)
1005 fst_issue_cmd(port, SETV24O);
1006 }
1007
1008 /*
1009 * Setup port Rx buffers
1010 */
1011 static void
1012 fst_rx_config(struct fst_port_info *port)
1013 {
1014 int i;
1015 int pi;
1016 unsigned int offset;
1017 unsigned long flags;
1018 struct fst_card_info *card;
1019
1020 pi = port->index;
1021 card = port->card;
1022 spin_lock_irqsave(&card->card_lock, flags);
1023 for (i = 0; i < NUM_RX_BUFFER; i++) {
1024 offset = BUF_OFFSET(rxBuffer[pi][i][0]);
1025
1026 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset);
1027 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16));
1028 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER));
1029 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER);
1030 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN);
1031 }
1032 port->rxpos = 0;
1033 spin_unlock_irqrestore(&card->card_lock, flags);
1034 }
1035
1036 /*
1037 * Setup port Tx buffers
1038 */
1039 static void
1040 fst_tx_config(struct fst_port_info *port)
1041 {
1042 int i;
1043 int pi;
1044 unsigned int offset;
1045 unsigned long flags;
1046 struct fst_card_info *card;
1047
1048 pi = port->index;
1049 card = port->card;
1050 spin_lock_irqsave(&card->card_lock, flags);
1051 for (i = 0; i < NUM_TX_BUFFER; i++) {
1052 offset = BUF_OFFSET(txBuffer[pi][i][0]);
1053
1054 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset);
1055 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16));
1056 FST_WRW(card, txDescrRing[pi][i].bcnt, 0);
1057 FST_WRB(card, txDescrRing[pi][i].bits, 0);
1058 }
1059 port->txpos = 0;
1060 port->txipos = 0;
1061 port->start = 0;
1062 spin_unlock_irqrestore(&card->card_lock, flags);
1063 }
1064
1065 /* TE1 Alarm change interrupt event
1066 */
1067 static void
1068 fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port)
1069 {
1070 u8 los;
1071 u8 rra;
1072 u8 ais;
1073
1074 los = FST_RDB(card, suStatus.lossOfSignal);
1075 rra = FST_RDB(card, suStatus.receiveRemoteAlarm);
1076 ais = FST_RDB(card, suStatus.alarmIndicationSignal);
1077
1078 if (los) {
1079 /*
1080 * Lost the link
1081 */
1082 if (netif_carrier_ok(port_to_dev(port))) {
1083 dbg(DBG_INTR, "Net carrier off\n");
1084 netif_carrier_off(port_to_dev(port));
1085 }
1086 } else {
1087 /*
1088 * Link available
1089 */
1090 if (!netif_carrier_ok(port_to_dev(port))) {
1091 dbg(DBG_INTR, "Net carrier on\n");
1092 netif_carrier_on(port_to_dev(port));
1093 }
1094 }
1095
1096 if (los)
1097 dbg(DBG_INTR, "Assert LOS Alarm\n");
1098 else
1099 dbg(DBG_INTR, "De-assert LOS Alarm\n");
1100 if (rra)
1101 dbg(DBG_INTR, "Assert RRA Alarm\n");
1102 else
1103 dbg(DBG_INTR, "De-assert RRA Alarm\n");
1104
1105 if (ais)
1106 dbg(DBG_INTR, "Assert AIS Alarm\n");
1107 else
1108 dbg(DBG_INTR, "De-assert AIS Alarm\n");
1109 }
1110
1111 /* Control signal change interrupt event
1112 */
1113 static void
1114 fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port)
1115 {
1116 int signals;
1117
1118 signals = FST_RDL(card, v24DebouncedSts[port->index]);
1119
1120 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
1121 ? IPSTS_INDICATE : IPSTS_DCD)) {
1122 if (!netif_carrier_ok(port_to_dev(port))) {
1123 dbg(DBG_INTR, "DCD active\n");
1124 netif_carrier_on(port_to_dev(port));
1125 }
1126 } else {
1127 if (netif_carrier_ok(port_to_dev(port))) {
1128 dbg(DBG_INTR, "DCD lost\n");
1129 netif_carrier_off(port_to_dev(port));
1130 }
1131 }
1132 }
1133
1134 /* Log Rx Errors
1135 */
1136 static void
1137 fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1138 unsigned char dmabits, int rxp, unsigned short len)
1139 {
1140 struct net_device *dev = port_to_dev(port);
1141
1142 /*
1143 * Increment the appropriate error counter
1144 */
1145 dev->stats.rx_errors++;
1146 if (dmabits & RX_OFLO) {
1147 dev->stats.rx_fifo_errors++;
1148 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",
1149 card->card_no, port->index, rxp);
1150 }
1151 if (dmabits & RX_CRC) {
1152 dev->stats.rx_crc_errors++;
1153 dbg(DBG_ASS, "Rx crc error on card %d port %d\n",
1154 card->card_no, port->index);
1155 }
1156 if (dmabits & RX_FRAM) {
1157 dev->stats.rx_frame_errors++;
1158 dbg(DBG_ASS, "Rx frame error on card %d port %d\n",
1159 card->card_no, port->index);
1160 }
1161 if (dmabits == (RX_STP | RX_ENP)) {
1162 dev->stats.rx_length_errors++;
1163 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",
1164 len, card->card_no, port->index);
1165 }
1166 }
1167
1168 /* Rx Error Recovery
1169 */
1170 static void
1171 fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1172 unsigned char dmabits, int rxp, unsigned short len)
1173 {
1174 int i;
1175 int pi;
1176
1177 pi = port->index;
1178 /*
1179 * Discard buffer descriptors until we see the start of the
1180 * next frame. Note that for long frames this could be in
1181 * a subsequent interrupt.
1182 */
1183 i = 0;
1184 while ((dmabits & (DMA_OWN | RX_STP)) == 0) {
1185 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1186 rxp = (rxp+1) % NUM_RX_BUFFER;
1187 if (++i > NUM_RX_BUFFER) {
1188 dbg(DBG_ASS, "intr_rx: Discarding more bufs"
1189 " than we have\n");
1190 break;
1191 }
1192 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1193 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits);
1194 }
1195 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i);
1196
1197 /* Discard the terminal buffer */
1198 if (!(dmabits & DMA_OWN)) {
1199 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1200 rxp = (rxp+1) % NUM_RX_BUFFER;
1201 }
1202 port->rxpos = rxp;
1203 return;
1204
1205 }
1206
1207 /* Rx complete interrupt
1208 */
1209 static void
1210 fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1211 {
1212 unsigned char dmabits;
1213 int pi;
1214 int rxp;
1215 int rx_status;
1216 unsigned short len;
1217 struct sk_buff *skb;
1218 struct net_device *dev = port_to_dev(port);
1219
1220 /* Check we have a buffer to process */
1221 pi = port->index;
1222 rxp = port->rxpos;
1223 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1224 if (dmabits & DMA_OWN) {
1225 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n",
1226 pi, rxp);
1227 return;
1228 }
1229 if (card->dmarx_in_progress) {
1230 return;
1231 }
1232
1233 /* Get buffer length */
1234 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt);
1235 /* Discard the CRC */
1236 len -= 2;
1237 if (len == 0) {
1238 /*
1239 * This seems to happen on the TE1 interface sometimes
1240 * so throw the frame away and log the event.
1241 */
1242 printk_err("Frame received with 0 length. Card %d Port %d\n",
1243 card->card_no, port->index);
1244 /* Return descriptor to card */
1245 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1246
1247 rxp = (rxp+1) % NUM_RX_BUFFER;
1248 port->rxpos = rxp;
1249 return;
1250 }
1251
1252 /* Check buffer length and for other errors. We insist on one packet
1253 * in one buffer. This simplifies things greatly and since we've
1254 * allocated 8K it shouldn't be a real world limitation
1255 */
1256 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len);
1257 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) {
1258 fst_log_rx_error(card, port, dmabits, rxp, len);
1259 fst_recover_rx_error(card, port, dmabits, rxp, len);
1260 return;
1261 }
1262
1263 /* Allocate SKB */
1264 if ((skb = dev_alloc_skb(len)) == NULL) {
1265 dbg(DBG_RX, "intr_rx: can't allocate buffer\n");
1266
1267 dev->stats.rx_dropped++;
1268
1269 /* Return descriptor to card */
1270 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1271
1272 rxp = (rxp+1) % NUM_RX_BUFFER;
1273 port->rxpos = rxp;
1274 return;
1275 }
1276
1277 /*
1278 * We know the length we need to receive, len.
1279 * It's not worth using the DMA for reads of less than
1280 * FST_MIN_DMA_LEN
1281 */
1282
1283 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) {
1284 memcpy_fromio(skb_put(skb, len),
1285 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]),
1286 len);
1287
1288 /* Reset buffer descriptor */
1289 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1290
1291 /* Update stats */
1292 dev->stats.rx_packets++;
1293 dev->stats.rx_bytes += len;
1294
1295 /* Push upstream */
1296 dbg(DBG_RX, "Pushing frame up the stack\n");
1297 if (port->mode == FST_RAW)
1298 skb->protocol = farsync_type_trans(skb, dev);
1299 else
1300 skb->protocol = hdlc_type_trans(skb, dev);
1301 rx_status = netif_rx(skb);
1302 fst_process_rx_status(rx_status, port_to_dev(port)->name);
1303 if (rx_status == NET_RX_DROP)
1304 dev->stats.rx_dropped++;
1305 } else {
1306 card->dma_skb_rx = skb;
1307 card->dma_port_rx = port;
1308 card->dma_len_rx = len;
1309 card->dma_rxpos = rxp;
1310 fst_rx_dma(card, (char *) card->rx_dma_handle_card,
1311 (char *) BUF_OFFSET(rxBuffer[pi][rxp][0]), len);
1312 }
1313 if (rxp != port->rxpos) {
1314 dbg(DBG_ASS, "About to increment rxpos by more than 1\n");
1315 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos);
1316 }
1317 rxp = (rxp+1) % NUM_RX_BUFFER;
1318 port->rxpos = rxp;
1319 }
1320
1321 /*
1322 * The bottom halfs to the ISR
1323 *
1324 */
1325
1326 static void
1327 do_bottom_half_tx(struct fst_card_info *card)
1328 {
1329 struct fst_port_info *port;
1330 int pi;
1331 int txq_length;
1332 struct sk_buff *skb;
1333 unsigned long flags;
1334 struct net_device *dev;
1335
1336 /*
1337 * Find a free buffer for the transmit
1338 * Step through each port on this card
1339 */
1340
1341 dbg(DBG_TX, "do_bottom_half_tx\n");
1342 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1343 if (!port->run)
1344 continue;
1345
1346 dev = port_to_dev(port);
1347 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) &
1348 DMA_OWN)
1349 && !(card->dmatx_in_progress)) {
1350 /*
1351 * There doesn't seem to be a txdone event per-se
1352 * We seem to have to deduce it, by checking the DMA_OWN
1353 * bit on the next buffer we think we can use
1354 */
1355 spin_lock_irqsave(&card->card_lock, flags);
1356 if ((txq_length = port->txqe - port->txqs) < 0) {
1357 /*
1358 * This is the case where one has wrapped and the
1359 * maths gives us a negative number
1360 */
1361 txq_length = txq_length + FST_TXQ_DEPTH;
1362 }
1363 spin_unlock_irqrestore(&card->card_lock, flags);
1364 if (txq_length > 0) {
1365 /*
1366 * There is something to send
1367 */
1368 spin_lock_irqsave(&card->card_lock, flags);
1369 skb = port->txq[port->txqs];
1370 port->txqs++;
1371 if (port->txqs == FST_TXQ_DEPTH) {
1372 port->txqs = 0;
1373 }
1374 spin_unlock_irqrestore(&card->card_lock, flags);
1375 /*
1376 * copy the data and set the required indicators on the
1377 * card.
1378 */
1379 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt,
1380 cnv_bcnt(skb->len));
1381 if ((skb->len < FST_MIN_DMA_LEN)
1382 || (card->family == FST_FAMILY_TXP)) {
1383 /* Enqueue the packet with normal io */
1384 memcpy_toio(card->mem +
1385 BUF_OFFSET(txBuffer[pi]
1386 [port->
1387 txpos][0]),
1388 skb->data, skb->len);
1389 FST_WRB(card,
1390 txDescrRing[pi][port->txpos].
1391 bits,
1392 DMA_OWN | TX_STP | TX_ENP);
1393 dev->stats.tx_packets++;
1394 dev->stats.tx_bytes += skb->len;
1395 dev->trans_start = jiffies;
1396 } else {
1397 /* Or do it through dma */
1398 memcpy(card->tx_dma_handle_host,
1399 skb->data, skb->len);
1400 card->dma_port_tx = port;
1401 card->dma_len_tx = skb->len;
1402 card->dma_txpos = port->txpos;
1403 fst_tx_dma(card,
1404 (char *) card->
1405 tx_dma_handle_card,
1406 (char *)
1407 BUF_OFFSET(txBuffer[pi]
1408 [port->txpos][0]),
1409 skb->len);
1410 }
1411 if (++port->txpos >= NUM_TX_BUFFER)
1412 port->txpos = 0;
1413 /*
1414 * If we have flow control on, can we now release it?
1415 */
1416 if (port->start) {
1417 if (txq_length < fst_txq_low) {
1418 netif_wake_queue(port_to_dev
1419 (port));
1420 port->start = 0;
1421 }
1422 }
1423 dev_kfree_skb(skb);
1424 } else {
1425 /*
1426 * Nothing to send so break out of the while loop
1427 */
1428 break;
1429 }
1430 }
1431 }
1432 }
1433
1434 static void
1435 do_bottom_half_rx(struct fst_card_info *card)
1436 {
1437 struct fst_port_info *port;
1438 int pi;
1439 int rx_count = 0;
1440
1441 /* Check for rx completions on all ports on this card */
1442 dbg(DBG_RX, "do_bottom_half_rx\n");
1443 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1444 if (!port->run)
1445 continue;
1446
1447 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits)
1448 & DMA_OWN) && !(card->dmarx_in_progress)) {
1449 if (rx_count > fst_max_reads) {
1450 /*
1451 * Don't spend forever in receive processing
1452 * Schedule another event
1453 */
1454 fst_q_work_item(&fst_work_intq, card->card_no);
1455 tasklet_schedule(&fst_int_task);
1456 break; /* Leave the loop */
1457 }
1458 fst_intr_rx(card, port);
1459 rx_count++;
1460 }
1461 }
1462 }
1463
1464 /*
1465 * The interrupt service routine
1466 * Dev_id is our fst_card_info pointer
1467 */
1468 static irqreturn_t
1469 fst_intr(int dummy, void *dev_id)
1470 {
1471 struct fst_card_info *card = dev_id;
1472 struct fst_port_info *port;
1473 int rdidx; /* Event buffer indices */
1474 int wridx;
1475 int event; /* Actual event for processing */
1476 unsigned int dma_intcsr = 0;
1477 unsigned int do_card_interrupt;
1478 unsigned int int_retry_count;
1479
1480 /*
1481 * Check to see if the interrupt was for this card
1482 * return if not
1483 * Note that the call to clear the interrupt is important
1484 */
1485 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card);
1486 if (card->state != FST_RUNNING) {
1487 printk_err
1488 ("Interrupt received for card %d in a non running state (%d)\n",
1489 card->card_no, card->state);
1490
1491 /*
1492 * It is possible to really be running, i.e. we have re-loaded
1493 * a running card
1494 * Clear and reprime the interrupt source
1495 */
1496 fst_clear_intr(card);
1497 return IRQ_HANDLED;
1498 }
1499
1500 /* Clear and reprime the interrupt source */
1501 fst_clear_intr(card);
1502
1503 /*
1504 * Is the interrupt for this card (handshake == 1)
1505 */
1506 do_card_interrupt = 0;
1507 if (FST_RDB(card, interruptHandshake) == 1) {
1508 do_card_interrupt += FST_CARD_INT;
1509 /* Set the software acknowledge */
1510 FST_WRB(card, interruptHandshake, 0xEE);
1511 }
1512 if (card->family == FST_FAMILY_TXU) {
1513 /*
1514 * Is it a DMA Interrupt
1515 */
1516 dma_intcsr = inl(card->pci_conf + INTCSR_9054);
1517 if (dma_intcsr & 0x00200000) {
1518 /*
1519 * DMA Channel 0 (Rx transfer complete)
1520 */
1521 dbg(DBG_RX, "DMA Rx xfer complete\n");
1522 outb(0x8, card->pci_conf + DMACSR0);
1523 fst_rx_dma_complete(card, card->dma_port_rx,
1524 card->dma_len_rx, card->dma_skb_rx,
1525 card->dma_rxpos);
1526 card->dmarx_in_progress = 0;
1527 do_card_interrupt += FST_RX_DMA_INT;
1528 }
1529 if (dma_intcsr & 0x00400000) {
1530 /*
1531 * DMA Channel 1 (Tx transfer complete)
1532 */
1533 dbg(DBG_TX, "DMA Tx xfer complete\n");
1534 outb(0x8, card->pci_conf + DMACSR1);
1535 fst_tx_dma_complete(card, card->dma_port_tx,
1536 card->dma_len_tx, card->dma_txpos);
1537 card->dmatx_in_progress = 0;
1538 do_card_interrupt += FST_TX_DMA_INT;
1539 }
1540 }
1541
1542 /*
1543 * Have we been missing Interrupts
1544 */
1545 int_retry_count = FST_RDL(card, interruptRetryCount);
1546 if (int_retry_count) {
1547 dbg(DBG_ASS, "Card %d int_retry_count is %d\n",
1548 card->card_no, int_retry_count);
1549 FST_WRL(card, interruptRetryCount, 0);
1550 }
1551
1552 if (!do_card_interrupt) {
1553 return IRQ_HANDLED;
1554 }
1555
1556 /* Scehdule the bottom half of the ISR */
1557 fst_q_work_item(&fst_work_intq, card->card_no);
1558 tasklet_schedule(&fst_int_task);
1559
1560 /* Drain the event queue */
1561 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f;
1562 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f;
1563 while (rdidx != wridx) {
1564 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]);
1565 port = &card->ports[event & 0x03];
1566
1567 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event);
1568
1569 switch (event) {
1570 case TE1_ALMA:
1571 dbg(DBG_INTR, "TE1 Alarm intr\n");
1572 if (port->run)
1573 fst_intr_te1_alarm(card, port);
1574 break;
1575
1576 case CTLA_CHG:
1577 case CTLB_CHG:
1578 case CTLC_CHG:
1579 case CTLD_CHG:
1580 if (port->run)
1581 fst_intr_ctlchg(card, port);
1582 break;
1583
1584 case ABTA_SENT:
1585 case ABTB_SENT:
1586 case ABTC_SENT:
1587 case ABTD_SENT:
1588 dbg(DBG_TX, "Abort complete port %d\n", port->index);
1589 break;
1590
1591 case TXA_UNDF:
1592 case TXB_UNDF:
1593 case TXC_UNDF:
1594 case TXD_UNDF:
1595 /* Difficult to see how we'd get this given that we
1596 * always load up the entire packet for DMA.
1597 */
1598 dbg(DBG_TX, "Tx underflow port %d\n", port->index);
1599 port_to_dev(port)->stats.tx_errors++;
1600 port_to_dev(port)->stats.tx_fifo_errors++;
1601 dbg(DBG_ASS, "Tx underflow on card %d port %d\n",
1602 card->card_no, port->index);
1603 break;
1604
1605 case INIT_CPLT:
1606 dbg(DBG_INIT, "Card init OK intr\n");
1607 break;
1608
1609 case INIT_FAIL:
1610 dbg(DBG_INIT, "Card init FAILED intr\n");
1611 card->state = FST_IFAILED;
1612 break;
1613
1614 default:
1615 printk_err("intr: unknown card event %d. ignored\n",
1616 event);
1617 break;
1618 }
1619
1620 /* Bump and wrap the index */
1621 if (++rdidx >= MAX_CIRBUFF)
1622 rdidx = 0;
1623 }
1624 FST_WRB(card, interruptEvent.rdindex, rdidx);
1625 return IRQ_HANDLED;
1626 }
1627
1628 /* Check that the shared memory configuration is one that we can handle
1629 * and that some basic parameters are correct
1630 */
1631 static void
1632 check_started_ok(struct fst_card_info *card)
1633 {
1634 int i;
1635
1636 /* Check structure version and end marker */
1637 if (FST_RDW(card, smcVersion) != SMC_VERSION) {
1638 printk_err("Bad shared memory version %d expected %d\n",
1639 FST_RDW(card, smcVersion), SMC_VERSION);
1640 card->state = FST_BADVERSION;
1641 return;
1642 }
1643 if (FST_RDL(card, endOfSmcSignature) != END_SIG) {
1644 printk_err("Missing shared memory signature\n");
1645 card->state = FST_BADVERSION;
1646 return;
1647 }
1648 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
1649 if ((i = FST_RDB(card, taskStatus)) == 0x01) {
1650 card->state = FST_RUNNING;
1651 } else if (i == 0xFF) {
1652 printk_err("Firmware initialisation failed. Card halted\n");
1653 card->state = FST_HALTED;
1654 return;
1655 } else if (i != 0x00) {
1656 printk_err("Unknown firmware status 0x%x\n", i);
1657 card->state = FST_HALTED;
1658 return;
1659 }
1660
1661 /* Finally check the number of ports reported by firmware against the
1662 * number we assumed at card detection. Should never happen with
1663 * existing firmware etc so we just report it for the moment.
1664 */
1665 if (FST_RDL(card, numberOfPorts) != card->nports) {
1666 printk_warn("Port count mismatch on card %d."
1667 " Firmware thinks %d we say %d\n", card->card_no,
1668 FST_RDL(card, numberOfPorts), card->nports);
1669 }
1670 }
1671
1672 static int
1673 set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port,
1674 struct fstioc_info *info)
1675 {
1676 int err;
1677 unsigned char my_framing;
1678
1679 /* Set things according to the user set valid flags
1680 * Several of the old options have been invalidated/replaced by the
1681 * generic hdlc package.
1682 */
1683 err = 0;
1684 if (info->valid & FSTVAL_PROTO) {
1685 if (info->proto == FST_RAW)
1686 port->mode = FST_RAW;
1687 else
1688 port->mode = FST_GEN_HDLC;
1689 }
1690
1691 if (info->valid & FSTVAL_CABLE)
1692 err = -EINVAL;
1693
1694 if (info->valid & FSTVAL_SPEED)
1695 err = -EINVAL;
1696
1697 if (info->valid & FSTVAL_PHASE)
1698 FST_WRB(card, portConfig[port->index].invertClock,
1699 info->invertClock);
1700 if (info->valid & FSTVAL_MODE)
1701 FST_WRW(card, cardMode, info->cardMode);
1702 if (info->valid & FSTVAL_TE1) {
1703 FST_WRL(card, suConfig.dataRate, info->lineSpeed);
1704 FST_WRB(card, suConfig.clocking, info->clockSource);
1705 my_framing = FRAMING_E1;
1706 if (info->framing == E1)
1707 my_framing = FRAMING_E1;
1708 if (info->framing == T1)
1709 my_framing = FRAMING_T1;
1710 if (info->framing == J1)
1711 my_framing = FRAMING_J1;
1712 FST_WRB(card, suConfig.framing, my_framing);
1713 FST_WRB(card, suConfig.structure, info->structure);
1714 FST_WRB(card, suConfig.interface, info->interface);
1715 FST_WRB(card, suConfig.coding, info->coding);
1716 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut);
1717 FST_WRB(card, suConfig.equalizer, info->equalizer);
1718 FST_WRB(card, suConfig.transparentMode, info->transparentMode);
1719 FST_WRB(card, suConfig.loopMode, info->loopMode);
1720 FST_WRB(card, suConfig.range, info->range);
1721 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode);
1722 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode);
1723 FST_WRB(card, suConfig.startingSlot, info->startingSlot);
1724 FST_WRB(card, suConfig.losThreshold, info->losThreshold);
1725 if (info->idleCode)
1726 FST_WRB(card, suConfig.enableIdleCode, 1);
1727 else
1728 FST_WRB(card, suConfig.enableIdleCode, 0);
1729 FST_WRB(card, suConfig.idleCode, info->idleCode);
1730 #if FST_DEBUG
1731 if (info->valid & FSTVAL_TE1) {
1732 printk("Setting TE1 data\n");
1733 printk("Line Speed = %d\n", info->lineSpeed);
1734 printk("Start slot = %d\n", info->startingSlot);
1735 printk("Clock source = %d\n", info->clockSource);
1736 printk("Framing = %d\n", my_framing);
1737 printk("Structure = %d\n", info->structure);
1738 printk("interface = %d\n", info->interface);
1739 printk("Coding = %d\n", info->coding);
1740 printk("Line build out = %d\n", info->lineBuildOut);
1741 printk("Equaliser = %d\n", info->equalizer);
1742 printk("Transparent mode = %d\n",
1743 info->transparentMode);
1744 printk("Loop mode = %d\n", info->loopMode);
1745 printk("Range = %d\n", info->range);
1746 printk("Tx Buffer mode = %d\n", info->txBufferMode);
1747 printk("Rx Buffer mode = %d\n", info->rxBufferMode);
1748 printk("LOS Threshold = %d\n", info->losThreshold);
1749 printk("Idle Code = %d\n", info->idleCode);
1750 }
1751 #endif
1752 }
1753 #if FST_DEBUG
1754 if (info->valid & FSTVAL_DEBUG) {
1755 fst_debug_mask = info->debug;
1756 }
1757 #endif
1758
1759 return err;
1760 }
1761
1762 static void
1763 gather_conf_info(struct fst_card_info *card, struct fst_port_info *port,
1764 struct fstioc_info *info)
1765 {
1766 int i;
1767
1768 memset(info, 0, sizeof (struct fstioc_info));
1769
1770 i = port->index;
1771 info->kernelVersion = LINUX_VERSION_CODE;
1772 info->nports = card->nports;
1773 info->type = card->type;
1774 info->state = card->state;
1775 info->proto = FST_GEN_HDLC;
1776 info->index = i;
1777 #if FST_DEBUG
1778 info->debug = fst_debug_mask;
1779 #endif
1780
1781 /* Only mark information as valid if card is running.
1782 * Copy the data anyway in case it is useful for diagnostics
1783 */
1784 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD)
1785 #if FST_DEBUG
1786 | FSTVAL_DEBUG
1787 #endif
1788 ;
1789
1790 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface);
1791 info->internalClock = FST_RDB(card, portConfig[i].internalClock);
1792 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed);
1793 info->invertClock = FST_RDB(card, portConfig[i].invertClock);
1794 info->v24IpSts = FST_RDL(card, v24IpSts[i]);
1795 info->v24OpSts = FST_RDL(card, v24OpSts[i]);
1796 info->clockStatus = FST_RDW(card, clockStatus[i]);
1797 info->cableStatus = FST_RDW(card, cableStatus);
1798 info->cardMode = FST_RDW(card, cardMode);
1799 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion);
1800
1801 /*
1802 * The T2U can report cable presence for both A or B
1803 * in bits 0 and 1 of cableStatus. See which port we are and
1804 * do the mapping.
1805 */
1806 if (card->family == FST_FAMILY_TXU) {
1807 if (port->index == 0) {
1808 /*
1809 * Port A
1810 */
1811 info->cableStatus = info->cableStatus & 1;
1812 } else {
1813 /*
1814 * Port B
1815 */
1816 info->cableStatus = info->cableStatus >> 1;
1817 info->cableStatus = info->cableStatus & 1;
1818 }
1819 }
1820 /*
1821 * Some additional bits if we are TE1
1822 */
1823 if (card->type == FST_TYPE_TE1) {
1824 info->lineSpeed = FST_RDL(card, suConfig.dataRate);
1825 info->clockSource = FST_RDB(card, suConfig.clocking);
1826 info->framing = FST_RDB(card, suConfig.framing);
1827 info->structure = FST_RDB(card, suConfig.structure);
1828 info->interface = FST_RDB(card, suConfig.interface);
1829 info->coding = FST_RDB(card, suConfig.coding);
1830 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut);
1831 info->equalizer = FST_RDB(card, suConfig.equalizer);
1832 info->loopMode = FST_RDB(card, suConfig.loopMode);
1833 info->range = FST_RDB(card, suConfig.range);
1834 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode);
1835 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode);
1836 info->startingSlot = FST_RDB(card, suConfig.startingSlot);
1837 info->losThreshold = FST_RDB(card, suConfig.losThreshold);
1838 if (FST_RDB(card, suConfig.enableIdleCode))
1839 info->idleCode = FST_RDB(card, suConfig.idleCode);
1840 else
1841 info->idleCode = 0;
1842 info->receiveBufferDelay =
1843 FST_RDL(card, suStatus.receiveBufferDelay);
1844 info->framingErrorCount =
1845 FST_RDL(card, suStatus.framingErrorCount);
1846 info->codeViolationCount =
1847 FST_RDL(card, suStatus.codeViolationCount);
1848 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount);
1849 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation);
1850 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal);
1851 info->receiveRemoteAlarm =
1852 FST_RDB(card, suStatus.receiveRemoteAlarm);
1853 info->alarmIndicationSignal =
1854 FST_RDB(card, suStatus.alarmIndicationSignal);
1855 }
1856 }
1857
1858 static int
1859 fst_set_iface(struct fst_card_info *card, struct fst_port_info *port,
1860 struct ifreq *ifr)
1861 {
1862 sync_serial_settings sync;
1863 int i;
1864
1865 if (ifr->ifr_settings.size != sizeof (sync)) {
1866 return -ENOMEM;
1867 }
1868
1869 if (copy_from_user
1870 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) {
1871 return -EFAULT;
1872 }
1873
1874 if (sync.loopback)
1875 return -EINVAL;
1876
1877 i = port->index;
1878
1879 switch (ifr->ifr_settings.type) {
1880 case IF_IFACE_V35:
1881 FST_WRW(card, portConfig[i].lineInterface, V35);
1882 port->hwif = V35;
1883 break;
1884
1885 case IF_IFACE_V24:
1886 FST_WRW(card, portConfig[i].lineInterface, V24);
1887 port->hwif = V24;
1888 break;
1889
1890 case IF_IFACE_X21:
1891 FST_WRW(card, portConfig[i].lineInterface, X21);
1892 port->hwif = X21;
1893 break;
1894
1895 case IF_IFACE_X21D:
1896 FST_WRW(card, portConfig[i].lineInterface, X21D);
1897 port->hwif = X21D;
1898 break;
1899
1900 case IF_IFACE_T1:
1901 FST_WRW(card, portConfig[i].lineInterface, T1);
1902 port->hwif = T1;
1903 break;
1904
1905 case IF_IFACE_E1:
1906 FST_WRW(card, portConfig[i].lineInterface, E1);
1907 port->hwif = E1;
1908 break;
1909
1910 case IF_IFACE_SYNC_SERIAL:
1911 break;
1912
1913 default:
1914 return -EINVAL;
1915 }
1916
1917 switch (sync.clock_type) {
1918 case CLOCK_EXT:
1919 FST_WRB(card, portConfig[i].internalClock, EXTCLK);
1920 break;
1921
1922 case CLOCK_INT:
1923 FST_WRB(card, portConfig[i].internalClock, INTCLK);
1924 break;
1925
1926 default:
1927 return -EINVAL;
1928 }
1929 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate);
1930 return 0;
1931 }
1932
1933 static int
1934 fst_get_iface(struct fst_card_info *card, struct fst_port_info *port,
1935 struct ifreq *ifr)
1936 {
1937 sync_serial_settings sync;
1938 int i;
1939
1940 /* First check what line type is set, we'll default to reporting X.21
1941 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
1942 * changed
1943 */
1944 switch (port->hwif) {
1945 case E1:
1946 ifr->ifr_settings.type = IF_IFACE_E1;
1947 break;
1948 case T1:
1949 ifr->ifr_settings.type = IF_IFACE_T1;
1950 break;
1951 case V35:
1952 ifr->ifr_settings.type = IF_IFACE_V35;
1953 break;
1954 case V24:
1955 ifr->ifr_settings.type = IF_IFACE_V24;
1956 break;
1957 case X21D:
1958 ifr->ifr_settings.type = IF_IFACE_X21D;
1959 break;
1960 case X21:
1961 default:
1962 ifr->ifr_settings.type = IF_IFACE_X21;
1963 break;
1964 }
1965 if (ifr->ifr_settings.size == 0) {
1966 return 0; /* only type requested */
1967 }
1968 if (ifr->ifr_settings.size < sizeof (sync)) {
1969 return -ENOMEM;
1970 }
1971
1972 i = port->index;
1973 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed);
1974 /* Lucky card and linux use same encoding here */
1975 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
1976 INTCLK ? CLOCK_INT : CLOCK_EXT;
1977 sync.loopback = 0;
1978
1979 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) {
1980 return -EFAULT;
1981 }
1982
1983 ifr->ifr_settings.size = sizeof (sync);
1984 return 0;
1985 }
1986
1987 static int
1988 fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1989 {
1990 struct fst_card_info *card;
1991 struct fst_port_info *port;
1992 struct fstioc_write wrthdr;
1993 struct fstioc_info info;
1994 unsigned long flags;
1995 void *buf;
1996
1997 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data);
1998
1999 port = dev_to_port(dev);
2000 card = port->card;
2001
2002 if (!capable(CAP_NET_ADMIN))
2003 return -EPERM;
2004
2005 switch (cmd) {
2006 case FSTCPURESET:
2007 fst_cpureset(card);
2008 card->state = FST_RESET;
2009 return 0;
2010
2011 case FSTCPURELEASE:
2012 fst_cpurelease(card);
2013 card->state = FST_STARTING;
2014 return 0;
2015
2016 case FSTWRITE: /* Code write (download) */
2017
2018 /* First copy in the header with the length and offset of data
2019 * to write
2020 */
2021 if (ifr->ifr_data == NULL) {
2022 return -EINVAL;
2023 }
2024 if (copy_from_user(&wrthdr, ifr->ifr_data,
2025 sizeof (struct fstioc_write))) {
2026 return -EFAULT;
2027 }
2028
2029 /* Sanity check the parameters. We don't support partial writes
2030 * when going over the top
2031 */
2032 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE
2033 || wrthdr.size + wrthdr.offset > FST_MEMSIZE) {
2034 return -ENXIO;
2035 }
2036
2037 /* Now copy the data to the card. */
2038
2039 buf = kmalloc(wrthdr.size, GFP_KERNEL);
2040 if (!buf)
2041 return -ENOMEM;
2042
2043 if (copy_from_user(buf,
2044 ifr->ifr_data + sizeof (struct fstioc_write),
2045 wrthdr.size)) {
2046 kfree(buf);
2047 return -EFAULT;
2048 }
2049
2050 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size);
2051 kfree(buf);
2052
2053 /* Writes to the memory of a card in the reset state constitute
2054 * a download
2055 */
2056 if (card->state == FST_RESET) {
2057 card->state = FST_DOWNLOAD;
2058 }
2059 return 0;
2060
2061 case FSTGETCONF:
2062
2063 /* If card has just been started check the shared memory config
2064 * version and marker
2065 */
2066 if (card->state == FST_STARTING) {
2067 check_started_ok(card);
2068
2069 /* If everything checked out enable card interrupts */
2070 if (card->state == FST_RUNNING) {
2071 spin_lock_irqsave(&card->card_lock, flags);
2072 fst_enable_intr(card);
2073 FST_WRB(card, interruptHandshake, 0xEE);
2074 spin_unlock_irqrestore(&card->card_lock, flags);
2075 }
2076 }
2077
2078 if (ifr->ifr_data == NULL) {
2079 return -EINVAL;
2080 }
2081
2082 gather_conf_info(card, port, &info);
2083
2084 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) {
2085 return -EFAULT;
2086 }
2087 return 0;
2088
2089 case FSTSETCONF:
2090
2091 /*
2092 * Most of the settings have been moved to the generic ioctls
2093 * this just covers debug and board ident now
2094 */
2095
2096 if (card->state != FST_RUNNING) {
2097 printk_err
2098 ("Attempt to configure card %d in non-running state (%d)\n",
2099 card->card_no, card->state);
2100 return -EIO;
2101 }
2102 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) {
2103 return -EFAULT;
2104 }
2105
2106 return set_conf_from_info(card, port, &info);
2107
2108 case SIOCWANDEV:
2109 switch (ifr->ifr_settings.type) {
2110 case IF_GET_IFACE:
2111 return fst_get_iface(card, port, ifr);
2112
2113 case IF_IFACE_SYNC_SERIAL:
2114 case IF_IFACE_V35:
2115 case IF_IFACE_V24:
2116 case IF_IFACE_X21:
2117 case IF_IFACE_X21D:
2118 case IF_IFACE_T1:
2119 case IF_IFACE_E1:
2120 return fst_set_iface(card, port, ifr);
2121
2122 case IF_PROTO_RAW:
2123 port->mode = FST_RAW;
2124 return 0;
2125
2126 case IF_GET_PROTO:
2127 if (port->mode == FST_RAW) {
2128 ifr->ifr_settings.type = IF_PROTO_RAW;
2129 return 0;
2130 }
2131 return hdlc_ioctl(dev, ifr, cmd);
2132
2133 default:
2134 port->mode = FST_GEN_HDLC;
2135 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n",
2136 ifr->ifr_settings.type);
2137 return hdlc_ioctl(dev, ifr, cmd);
2138 }
2139
2140 default:
2141 /* Not one of ours. Pass through to HDLC package */
2142 return hdlc_ioctl(dev, ifr, cmd);
2143 }
2144 }
2145
2146 static void
2147 fst_openport(struct fst_port_info *port)
2148 {
2149 int signals;
2150 int txq_length;
2151
2152 /* Only init things if card is actually running. This allows open to
2153 * succeed for downloads etc.
2154 */
2155 if (port->card->state == FST_RUNNING) {
2156 if (port->run) {
2157 dbg(DBG_OPEN, "open: found port already running\n");
2158
2159 fst_issue_cmd(port, STOPPORT);
2160 port->run = 0;
2161 }
2162
2163 fst_rx_config(port);
2164 fst_tx_config(port);
2165 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR);
2166
2167 fst_issue_cmd(port, STARTPORT);
2168 port->run = 1;
2169
2170 signals = FST_RDL(port->card, v24DebouncedSts[port->index]);
2171 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
2172 ? IPSTS_INDICATE : IPSTS_DCD))
2173 netif_carrier_on(port_to_dev(port));
2174 else
2175 netif_carrier_off(port_to_dev(port));
2176
2177 txq_length = port->txqe - port->txqs;
2178 port->txqe = 0;
2179 port->txqs = 0;
2180 }
2181
2182 }
2183
2184 static void
2185 fst_closeport(struct fst_port_info *port)
2186 {
2187 if (port->card->state == FST_RUNNING) {
2188 if (port->run) {
2189 port->run = 0;
2190 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR);
2191
2192 fst_issue_cmd(port, STOPPORT);
2193 } else {
2194 dbg(DBG_OPEN, "close: port not running\n");
2195 }
2196 }
2197 }
2198
2199 static int
2200 fst_open(struct net_device *dev)
2201 {
2202 int err;
2203 struct fst_port_info *port;
2204
2205 port = dev_to_port(dev);
2206 if (!try_module_get(THIS_MODULE))
2207 return -EBUSY;
2208
2209 if (port->mode != FST_RAW) {
2210 err = hdlc_open(dev);
2211 if (err)
2212 return err;
2213 }
2214
2215 fst_openport(port);
2216 netif_wake_queue(dev);
2217 return 0;
2218 }
2219
2220 static int
2221 fst_close(struct net_device *dev)
2222 {
2223 struct fst_port_info *port;
2224 struct fst_card_info *card;
2225 unsigned char tx_dma_done;
2226 unsigned char rx_dma_done;
2227
2228 port = dev_to_port(dev);
2229 card = port->card;
2230
2231 tx_dma_done = inb(card->pci_conf + DMACSR1);
2232 rx_dma_done = inb(card->pci_conf + DMACSR0);
2233 dbg(DBG_OPEN,
2234 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
2235 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress,
2236 rx_dma_done);
2237
2238 netif_stop_queue(dev);
2239 fst_closeport(dev_to_port(dev));
2240 if (port->mode != FST_RAW) {
2241 hdlc_close(dev);
2242 }
2243 module_put(THIS_MODULE);
2244 return 0;
2245 }
2246
2247 static int
2248 fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity)
2249 {
2250 /*
2251 * Setting currently fixed in FarSync card so we check and forget
2252 */
2253 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT)
2254 return -EINVAL;
2255 return 0;
2256 }
2257
2258 static void
2259 fst_tx_timeout(struct net_device *dev)
2260 {
2261 struct fst_port_info *port;
2262 struct fst_card_info *card;
2263
2264 port = dev_to_port(dev);
2265 card = port->card;
2266 dev->stats.tx_errors++;
2267 dev->stats.tx_aborted_errors++;
2268 dbg(DBG_ASS, "Tx timeout card %d port %d\n",
2269 card->card_no, port->index);
2270 fst_issue_cmd(port, ABORTTX);
2271
2272 dev->trans_start = jiffies;
2273 netif_wake_queue(dev);
2274 port->start = 0;
2275 }
2276
2277 static netdev_tx_t
2278 fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2279 {
2280 struct fst_card_info *card;
2281 struct fst_port_info *port;
2282 unsigned long flags;
2283 int txq_length;
2284
2285 port = dev_to_port(dev);
2286 card = port->card;
2287 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len);
2288
2289 /* Drop packet with error if we don't have carrier */
2290 if (!netif_carrier_ok(dev)) {
2291 dev_kfree_skb(skb);
2292 dev->stats.tx_errors++;
2293 dev->stats.tx_carrier_errors++;
2294 dbg(DBG_ASS,
2295 "Tried to transmit but no carrier on card %d port %d\n",
2296 card->card_no, port->index);
2297 return NETDEV_TX_OK;
2298 }
2299
2300 /* Drop it if it's too big! MTU failure ? */
2301 if (skb->len > LEN_TX_BUFFER) {
2302 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,
2303 LEN_TX_BUFFER);
2304 dev_kfree_skb(skb);
2305 dev->stats.tx_errors++;
2306 return NETDEV_TX_OK;
2307 }
2308
2309 /*
2310 * We are always going to queue the packet
2311 * so that the bottom half is the only place we tx from
2312 * Check there is room in the port txq
2313 */
2314 spin_lock_irqsave(&card->card_lock, flags);
2315 if ((txq_length = port->txqe - port->txqs) < 0) {
2316 /*
2317 * This is the case where the next free has wrapped but the
2318 * last used hasn't
2319 */
2320 txq_length = txq_length + FST_TXQ_DEPTH;
2321 }
2322 spin_unlock_irqrestore(&card->card_lock, flags);
2323 if (txq_length > fst_txq_high) {
2324 /*
2325 * We have got enough buffers in the pipeline. Ask the network
2326 * layer to stop sending frames down
2327 */
2328 netif_stop_queue(dev);
2329 port->start = 1; /* I'm using this to signal stop sent up */
2330 }
2331
2332 if (txq_length == FST_TXQ_DEPTH - 1) {
2333 /*
2334 * This shouldn't have happened but such is life
2335 */
2336 dev_kfree_skb(skb);
2337 dev->stats.tx_errors++;
2338 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",
2339 card->card_no, port->index);
2340 return NETDEV_TX_OK;
2341 }
2342
2343 /*
2344 * queue the buffer
2345 */
2346 spin_lock_irqsave(&card->card_lock, flags);
2347 port->txq[port->txqe] = skb;
2348 port->txqe++;
2349 if (port->txqe == FST_TXQ_DEPTH)
2350 port->txqe = 0;
2351 spin_unlock_irqrestore(&card->card_lock, flags);
2352
2353 /* Scehdule the bottom half which now does transmit processing */
2354 fst_q_work_item(&fst_work_txq, card->card_no);
2355 tasklet_schedule(&fst_tx_task);
2356
2357 return NETDEV_TX_OK;
2358 }
2359
2360 /*
2361 * Card setup having checked hardware resources.
2362 * Should be pretty bizarre if we get an error here (kernel memory
2363 * exhaustion is one possibility). If we do see a problem we report it
2364 * via a printk and leave the corresponding interface and all that follow
2365 * disabled.
2366 */
2367 static char *type_strings[] __devinitdata = {
2368 "no hardware", /* Should never be seen */
2369 "FarSync T2P",
2370 "FarSync T4P",
2371 "FarSync T1U",
2372 "FarSync T2U",
2373 "FarSync T4U",
2374 "FarSync TE1"
2375 };
2376
2377 static void __devinit
2378 fst_init_card(struct fst_card_info *card)
2379 {
2380 int i;
2381 int err;
2382
2383 /* We're working on a number of ports based on the card ID. If the
2384 * firmware detects something different later (should never happen)
2385 * we'll have to revise it in some way then.
2386 */
2387 for (i = 0; i < card->nports; i++) {
2388 err = register_hdlc_device(card->ports[i].dev);
2389 if (err < 0) {
2390 int j;
2391 printk_err ("Cannot register HDLC device for port %d"
2392 " (errno %d)\n", i, -err );
2393 for (j = i; j < card->nports; j++) {
2394 free_netdev(card->ports[j].dev);
2395 card->ports[j].dev = NULL;
2396 }
2397 card->nports = i;
2398 break;
2399 }
2400 }
2401
2402 printk_info("%s-%s: %s IRQ%d, %d ports\n",
2403 port_to_dev(&card->ports[0])->name,
2404 port_to_dev(&card->ports[card->nports - 1])->name,
2405 type_strings[card->type], card->irq, card->nports);
2406 }
2407
2408 static const struct net_device_ops fst_ops = {
2409 .ndo_open = fst_open,
2410 .ndo_stop = fst_close,
2411 .ndo_change_mtu = hdlc_change_mtu,
2412 .ndo_start_xmit = hdlc_start_xmit,
2413 .ndo_do_ioctl = fst_ioctl,
2414 .ndo_tx_timeout = fst_tx_timeout,
2415 };
2416
2417 /*
2418 * Initialise card when detected.
2419 * Returns 0 to indicate success, or errno otherwise.
2420 */
2421 static int __devinit
2422 fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2423 {
2424 static int firsttime_done = 0;
2425 static int no_of_cards_added = 0;
2426 struct fst_card_info *card;
2427 int err = 0;
2428 int i;
2429
2430 if (!firsttime_done) {
2431 printk_info("FarSync WAN driver " FST_USER_VERSION
2432 " (c) 2001-2004 FarSite Communications Ltd.\n");
2433 firsttime_done = 1;
2434 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask);
2435 }
2436
2437 /*
2438 * We are going to be clever and allow certain cards not to be
2439 * configured. An exclude list can be provided in /etc/modules.conf
2440 */
2441 if (fst_excluded_cards != 0) {
2442 /*
2443 * There are cards to exclude
2444 *
2445 */
2446 for (i = 0; i < fst_excluded_cards; i++) {
2447 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) {
2448 printk_info("FarSync PCI device %d not assigned\n",
2449 (pdev->devfn) >> 3);
2450 return -EBUSY;
2451 }
2452 }
2453 }
2454
2455 /* Allocate driver private data */
2456 card = kzalloc(sizeof (struct fst_card_info), GFP_KERNEL);
2457 if (card == NULL) {
2458 printk_err("FarSync card found but insufficient memory for"
2459 " driver storage\n");
2460 return -ENOMEM;
2461 }
2462
2463 /* Try to enable the device */
2464 if ((err = pci_enable_device(pdev)) != 0) {
2465 printk_err("Failed to enable card. Err %d\n", -err);
2466 kfree(card);
2467 return err;
2468 }
2469
2470 if ((err = pci_request_regions(pdev, "FarSync")) !=0) {
2471 printk_err("Failed to allocate regions. Err %d\n", -err);
2472 pci_disable_device(pdev);
2473 kfree(card);
2474 return err;
2475 }
2476
2477 /* Get virtual addresses of memory regions */
2478 card->pci_conf = pci_resource_start(pdev, 1);
2479 card->phys_mem = pci_resource_start(pdev, 2);
2480 card->phys_ctlmem = pci_resource_start(pdev, 3);
2481 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) {
2482 printk_err("Physical memory remap failed\n");
2483 pci_release_regions(pdev);
2484 pci_disable_device(pdev);
2485 kfree(card);
2486 return -ENODEV;
2487 }
2488 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) {
2489 printk_err("Control memory remap failed\n");
2490 pci_release_regions(pdev);
2491 pci_disable_device(pdev);
2492 kfree(card);
2493 return -ENODEV;
2494 }
2495 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem);
2496
2497 /* Register the interrupt handler */
2498 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) {
2499 printk_err("Unable to register interrupt %d\n", card->irq);
2500 pci_release_regions(pdev);
2501 pci_disable_device(pdev);
2502 iounmap(card->ctlmem);
2503 iounmap(card->mem);
2504 kfree(card);
2505 return -ENODEV;
2506 }
2507
2508 /* Record info we need */
2509 card->irq = pdev->irq;
2510 card->type = ent->driver_data;
2511 card->family = ((ent->driver_data == FST_TYPE_T2P) ||
2512 (ent->driver_data == FST_TYPE_T4P))
2513 ? FST_FAMILY_TXP : FST_FAMILY_TXU;
2514 if ((ent->driver_data == FST_TYPE_T1U) ||
2515 (ent->driver_data == FST_TYPE_TE1))
2516 card->nports = 1;
2517 else
2518 card->nports = ((ent->driver_data == FST_TYPE_T2P) ||
2519 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4;
2520
2521 card->state = FST_UNINIT;
2522 spin_lock_init ( &card->card_lock );
2523
2524 for ( i = 0 ; i < card->nports ; i++ ) {
2525 struct net_device *dev = alloc_hdlcdev(&card->ports[i]);
2526 hdlc_device *hdlc;
2527 if (!dev) {
2528 while (i--)
2529 free_netdev(card->ports[i].dev);
2530 printk_err ("FarSync: out of memory\n");
2531 free_irq(card->irq, card);
2532 pci_release_regions(pdev);
2533 pci_disable_device(pdev);
2534 iounmap(card->ctlmem);
2535 iounmap(card->mem);
2536 kfree(card);
2537 return -ENODEV;
2538 }
2539 card->ports[i].dev = dev;
2540 card->ports[i].card = card;
2541 card->ports[i].index = i;
2542 card->ports[i].run = 0;
2543
2544 hdlc = dev_to_hdlc(dev);
2545
2546 /* Fill in the net device info */
2547 /* Since this is a PCI setup this is purely
2548 * informational. Give them the buffer addresses
2549 * and basic card I/O.
2550 */
2551 dev->mem_start = card->phys_mem
2552 + BUF_OFFSET ( txBuffer[i][0][0]);
2553 dev->mem_end = card->phys_mem
2554 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER][0]);
2555 dev->base_addr = card->pci_conf;
2556 dev->irq = card->irq;
2557
2558 dev->netdev_ops = &fst_ops;
2559 dev->tx_queue_len = FST_TX_QUEUE_LEN;
2560 dev->watchdog_timeo = FST_TX_TIMEOUT;
2561 hdlc->attach = fst_attach;
2562 hdlc->xmit = fst_start_xmit;
2563 }
2564
2565 card->device = pdev;
2566
2567 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type,
2568 card->nports, card->irq);
2569 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n",
2570 card->pci_conf, card->phys_mem, card->phys_ctlmem);
2571
2572 /* Reset the card's processor */
2573 fst_cpureset(card);
2574 card->state = FST_RESET;
2575
2576 /* Initialise DMA (if required) */
2577 fst_init_dma(card);
2578
2579 /* Record driver data for later use */
2580 pci_set_drvdata(pdev, card);
2581
2582 /* Remainder of card setup */
2583 fst_card_array[no_of_cards_added] = card;
2584 card->card_no = no_of_cards_added++; /* Record instance and bump it */
2585 fst_init_card(card);
2586 if (card->family == FST_FAMILY_TXU) {
2587 /*
2588 * Allocate a dma buffer for transmit and receives
2589 */
2590 card->rx_dma_handle_host =
2591 pci_alloc_consistent(card->device, FST_MAX_MTU,
2592 &card->rx_dma_handle_card);
2593 if (card->rx_dma_handle_host == NULL) {
2594 printk_err("Could not allocate rx dma buffer\n");
2595 fst_disable_intr(card);
2596 pci_release_regions(pdev);
2597 pci_disable_device(pdev);
2598 iounmap(card->ctlmem);
2599 iounmap(card->mem);
2600 kfree(card);
2601 return -ENOMEM;
2602 }
2603 card->tx_dma_handle_host =
2604 pci_alloc_consistent(card->device, FST_MAX_MTU,
2605 &card->tx_dma_handle_card);
2606 if (card->tx_dma_handle_host == NULL) {
2607 printk_err("Could not allocate tx dma buffer\n");
2608 fst_disable_intr(card);
2609 pci_release_regions(pdev);
2610 pci_disable_device(pdev);
2611 iounmap(card->ctlmem);
2612 iounmap(card->mem);
2613 kfree(card);
2614 return -ENOMEM;
2615 }
2616 }
2617 return 0; /* Success */
2618 }
2619
2620 /*
2621 * Cleanup and close down a card
2622 */
2623 static void __devexit
2624 fst_remove_one(struct pci_dev *pdev)
2625 {
2626 struct fst_card_info *card;
2627 int i;
2628
2629 card = pci_get_drvdata(pdev);
2630
2631 for (i = 0; i < card->nports; i++) {
2632 struct net_device *dev = port_to_dev(&card->ports[i]);
2633 unregister_hdlc_device(dev);
2634 }
2635
2636 fst_disable_intr(card);
2637 free_irq(card->irq, card);
2638
2639 iounmap(card->ctlmem);
2640 iounmap(card->mem);
2641 pci_release_regions(pdev);
2642 if (card->family == FST_FAMILY_TXU) {
2643 /*
2644 * Free dma buffers
2645 */
2646 pci_free_consistent(card->device, FST_MAX_MTU,
2647 card->rx_dma_handle_host,
2648 card->rx_dma_handle_card);
2649 pci_free_consistent(card->device, FST_MAX_MTU,
2650 card->tx_dma_handle_host,
2651 card->tx_dma_handle_card);
2652 }
2653 fst_card_array[card->card_no] = NULL;
2654 }
2655
2656 static struct pci_driver fst_driver = {
2657 .name = FST_NAME,
2658 .id_table = fst_pci_dev_id,
2659 .probe = fst_add_one,
2660 .remove = __devexit_p(fst_remove_one),
2661 .suspend = NULL,
2662 .resume = NULL,
2663 };
2664
2665 static int __init
2666 fst_init(void)
2667 {
2668 int i;
2669
2670 for (i = 0; i < FST_MAX_CARDS; i++)
2671 fst_card_array[i] = NULL;
2672 spin_lock_init(&fst_work_q_lock);
2673 return pci_register_driver(&fst_driver);
2674 }
2675
2676 static void __exit
2677 fst_cleanup_module(void)
2678 {
2679 printk_info("FarSync WAN driver unloading\n");
2680 pci_unregister_driver(&fst_driver);
2681 }
2682
2683 module_init(fst_init);
2684 module_exit(fst_cleanup_module);
Linux with added FPC-III support