drivers/net/wan/lmc/lmc_var.h

   1 #ifndef _LMC_VAR_H_
   2 #define _LMC_VAR_H_
   3
   4  /*
   5   * Copyright (c) 1997-2000 LAN Media Corporation (LMC)
   6   * All rights reserved.  www.lanmedia.com
   7   *
   8   * This code is written by:
   9   * Andrew Stanley-Jones (asj@cban.com)
  10   * Rob Braun (bbraun@vix.com),
  11   * Michael Graff (explorer@vix.com) and
  12   * Matt Thomas (matt@3am-software.com).
  13   *
  14   * This software may be used and distributed according to the terms
  15   * of the GNU General Public License version 2, incorporated herein by reference.
  16   */
  17
  18 #include <linux/timer.h>
  19
  20 /*
  21  * basic definitions used in lmc include files
  22  */
  23
  24 typedef struct lmc___softc lmc_softc_t;
  25 typedef struct lmc___media lmc_media_t;
  26 typedef struct lmc___ctl lmc_ctl_t;
  27
  28 #define lmc_csrptr_t    unsigned long
  29
  30 #define LMC_REG_RANGE 0x80
  31
  32 #define LMC_PRINTF_FMT  "%s"
  33 #define LMC_PRINTF_ARGS (sc->lmc_device->name)
  34
  35 #define TX_TIMEOUT (2*HZ)
  36
  37 #define LMC_TXDESCS            32
  38 #define LMC_RXDESCS            32
  39
  40 #define LMC_LINK_UP            1
  41 #define LMC_LINK_DOWN          0
  42
  43 /* These macros for generic read and write to and from the dec chip */
  44 #define LMC_CSR_READ(sc, csr) \
  45         inl((sc)->lmc_csrs.csr)
  46 #define LMC_CSR_WRITE(sc, reg, val) \
  47         outl((val), (sc)->lmc_csrs.reg)
  48
  49 //#ifdef _LINUX_DELAY_H
  50 //      #define SLOW_DOWN_IO udelay(2);
  51 //      #undef __SLOW_DOWN_IO
  52 //      #define __SLOW_DOWN_IO udelay(2);
  53 //#endif
  54
  55 #define DELAY(n) SLOW_DOWN_IO
  56
  57 #define lmc_delay() inl(sc->lmc_csrs.csr_9)
  58
  59 /* This macro sync's up with the mii so that reads and writes can take place */
  60 #define LMC_MII_SYNC(sc) do {int n=32; while( n >= 0 ) { \
  61                 LMC_CSR_WRITE((sc), csr_9, 0x20000); \
  62                 lmc_delay(); \
  63                 LMC_CSR_WRITE((sc), csr_9, 0x30000); \
  64                 lmc_delay(); \
  65                 n--; }} while(0)
  66
  67 struct lmc_regfile_t {
  68     lmc_csrptr_t csr_busmode;                  /* CSR0 */
  69     lmc_csrptr_t csr_txpoll;                   /* CSR1 */
  70     lmc_csrptr_t csr_rxpoll;                   /* CSR2 */
  71     lmc_csrptr_t csr_rxlist;                   /* CSR3 */
  72     lmc_csrptr_t csr_txlist;                   /* CSR4 */
  73     lmc_csrptr_t csr_status;                   /* CSR5 */
  74     lmc_csrptr_t csr_command;                  /* CSR6 */
  75     lmc_csrptr_t csr_intr;                     /* CSR7 */
  76     lmc_csrptr_t csr_missed_frames;            /* CSR8 */
  77     lmc_csrptr_t csr_9;                        /* CSR9 */
  78     lmc_csrptr_t csr_10;                       /* CSR10 */
  79     lmc_csrptr_t csr_11;                       /* CSR11 */
  80     lmc_csrptr_t csr_12;                       /* CSR12 */
  81     lmc_csrptr_t csr_13;                       /* CSR13 */
  82     lmc_csrptr_t csr_14;                       /* CSR14 */
  83     lmc_csrptr_t csr_15;                       /* CSR15 */
  84 };
  85
  86 #define csr_enetrom             csr_9   /* 21040 */
  87 #define csr_reserved            csr_10  /* 21040 */
  88 #define csr_full_duplex         csr_11  /* 21040 */
  89 #define csr_bootrom             csr_10  /* 21041/21140A/?? */
  90 #define csr_gp                  csr_12  /* 21140* */
  91 #define csr_watchdog            csr_15  /* 21140* */
  92 #define csr_gp_timer            csr_11  /* 21041/21140* */
  93 #define csr_srom_mii            csr_9   /* 21041/21140* */
  94 #define csr_sia_status          csr_12  /* 2104x */
  95 #define csr_sia_connectivity    csr_13  /* 2104x */
  96 #define csr_sia_tx_rx           csr_14  /* 2104x */
  97 #define csr_sia_general         csr_15  /* 2104x */
  98
  99 /* tulip length/control transmit descriptor definitions
 100  *  used to define bits in the second tulip_desc_t field (length)
 101  *  for the transmit descriptor -baz */
 102
 103 #define LMC_TDES_FIRST_BUFFER_SIZE       ((u32)(0x000007FF))
 104 #define LMC_TDES_SECOND_BUFFER_SIZE      ((u32)(0x003FF800))
 105 #define LMC_TDES_HASH_FILTERING          ((u32)(0x00400000))
 106 #define LMC_TDES_DISABLE_PADDING         ((u32)(0x00800000))
 107 #define LMC_TDES_SECOND_ADDR_CHAINED     ((u32)(0x01000000))
 108 #define LMC_TDES_END_OF_RING             ((u32)(0x02000000))
 109 #define LMC_TDES_ADD_CRC_DISABLE         ((u32)(0x04000000))
 110 #define LMC_TDES_SETUP_PACKET            ((u32)(0x08000000))
 111 #define LMC_TDES_INVERSE_FILTERING       ((u32)(0x10000000))
 112 #define LMC_TDES_FIRST_SEGMENT           ((u32)(0x20000000))
 113 #define LMC_TDES_LAST_SEGMENT            ((u32)(0x40000000))
 114 #define LMC_TDES_INTERRUPT_ON_COMPLETION ((u32)(0x80000000))
 115
 116 #define TDES_SECOND_BUFFER_SIZE_BIT_NUMBER  11
 117 #define TDES_COLLISION_COUNT_BIT_NUMBER     3
 118
 119 /* Constants for the RCV descriptor RDES */
 120
 121 #define LMC_RDES_OVERFLOW             ((u32)(0x00000001))
 122 #define LMC_RDES_CRC_ERROR            ((u32)(0x00000002))
 123 #define LMC_RDES_DRIBBLING_BIT        ((u32)(0x00000004))
 124 #define LMC_RDES_REPORT_ON_MII_ERR    ((u32)(0x00000008))
 125 #define LMC_RDES_RCV_WATCHDOG_TIMEOUT ((u32)(0x00000010))
 126 #define LMC_RDES_FRAME_TYPE           ((u32)(0x00000020))
 127 #define LMC_RDES_COLLISION_SEEN       ((u32)(0x00000040))
 128 #define LMC_RDES_FRAME_TOO_LONG       ((u32)(0x00000080))
 129 #define LMC_RDES_LAST_DESCRIPTOR      ((u32)(0x00000100))
 130 #define LMC_RDES_FIRST_DESCRIPTOR     ((u32)(0x00000200))
 131 #define LMC_RDES_MULTICAST_FRAME      ((u32)(0x00000400))
 132 #define LMC_RDES_RUNT_FRAME           ((u32)(0x00000800))
 133 #define LMC_RDES_DATA_TYPE            ((u32)(0x00003000))
 134 #define LMC_RDES_LENGTH_ERROR         ((u32)(0x00004000))
 135 #define LMC_RDES_ERROR_SUMMARY        ((u32)(0x00008000))
 136 #define LMC_RDES_FRAME_LENGTH         ((u32)(0x3FFF0000))
 137 #define LMC_RDES_OWN_BIT              ((u32)(0x80000000))
 138
 139 #define RDES_FRAME_LENGTH_BIT_NUMBER       16
 140
 141 #define LMC_RDES_ERROR_MASK ( (u32)( \
 142           LMC_RDES_OVERFLOW \
 143         | LMC_RDES_DRIBBLING_BIT \
 144         | LMC_RDES_REPORT_ON_MII_ERR \
 145         | LMC_RDES_COLLISION_SEEN ) )
 146
 147
 148 /*
 149  * Ioctl info
 150  */
 151
 152 typedef struct {
 153         u32     n;
 154         u32     m;
 155         u32     v;
 156         u32     x;
 157         u32     r;
 158         u32     f;
 159         u32     exact;
 160 } lmc_av9110_t;
 161
 162 /*
 163  * Common structure passed to the ioctl code.
 164  */
 165 struct lmc___ctl {
 166         u32     cardtype;
 167         u32     clock_source;           /* HSSI, T1 */
 168         u32     clock_rate;             /* T1 */
 169         u32     crc_length;
 170         u32     cable_length;           /* DS3 */
 171         u32     scrambler_onoff;        /* DS3 */
 172         u32     cable_type;             /* T1 */
 173         u32     keepalive_onoff;        /* protocol */
 174         u32     ticks;                  /* ticks/sec */
 175         union {
 176                 lmc_av9110_t    ssi;
 177         } cardspec;
 178         u32       circuit_type;   /* T1 or E1 */
 179 };
 180
 181
 182 /*
 183  * Carefull, look at the data sheet, there's more to this
 184  * structure than meets the eye.  It should probably be:
 185  *
 186  * struct tulip_desc_t {
 187  *         u8  own:1;
 188  *         u32 status:31;
 189  *         u32 control:10;
 190  *         u32 buffer1;
 191  *         u32 buffer2;
 192  * };
 193  * You could also expand status control to provide more bit information
 194  */
 195
 196 struct tulip_desc_t {
 197         s32 status;
 198         s32 length;
 199         u32 buffer1;
 200         u32 buffer2;
 201 };
 202
 203 /*
 204  * media independent methods to check on media status, link, light LEDs,
 205  * etc.
 206  */
 207 struct lmc___media {
 208         void    (* init)(lmc_softc_t * const);
 209         void    (* defaults)(lmc_softc_t * const);
 210         void    (* set_status)(lmc_softc_t * const, lmc_ctl_t *);
 211         void    (* set_clock_source)(lmc_softc_t * const, int);
 212         void    (* set_speed)(lmc_softc_t * const, lmc_ctl_t *);
 213         void    (* set_cable_length)(lmc_softc_t * const, int);
 214         void    (* set_scrambler)(lmc_softc_t * const, int);
 215         int     (* get_link_status)(lmc_softc_t * const);
 216         void    (* set_link_status)(lmc_softc_t * const, int);
 217         void    (* set_crc_length)(lmc_softc_t * const, int);
 218         void    (* set_circuit_type)(lmc_softc_t * const, int);
 219         void    (* watchdog)(lmc_softc_t * const);
 220 };
 221
 222
 223 #define STATCHECK     0xBEEFCAFE
 224
 225 struct lmc_extra_statistics
 226 {
 227         u32       version_size;
 228         u32       lmc_cardtype;
 229
 230         u32       tx_ProcTimeout;
 231         u32       tx_IntTimeout;
 232         u32       tx_NoCompleteCnt;
 233         u32       tx_MaxXmtsB4Int;
 234         u32       tx_TimeoutCnt;
 235         u32       tx_OutOfSyncPtr;
 236         u32       tx_tbusy0;
 237         u32       tx_tbusy1;
 238         u32       tx_tbusy_calls;
 239         u32       resetCount;
 240         u32       lmc_txfull;
 241         u32       tbusy;
 242         u32       dirtyTx;
 243         u32       lmc_next_tx;
 244         u32       otherTypeCnt;
 245         u32       lastType;
 246         u32       lastTypeOK;
 247         u32       txLoopCnt;
 248         u32       usedXmtDescripCnt;
 249         u32       txIndexCnt;
 250         u32       rxIntLoopCnt;
 251
 252         u32       rx_SmallPktCnt;
 253         u32       rx_BadPktSurgeCnt;
 254         u32       rx_BuffAllocErr;
 255         u32       tx_lossOfClockCnt;
 256
 257         /* T1 error counters */
 258         u32       framingBitErrorCount;
 259         u32       lineCodeViolationCount;
 260
 261         u32       lossOfFrameCount;
 262         u32       changeOfFrameAlignmentCount;
 263         u32       severelyErroredFrameCount;
 264
 265         u32       check;
 266 };
 267
 268 typedef struct lmc_xinfo {
 269         u32       Magic0;                         /* BEEFCAFE */
 270
 271         u32       PciCardType;
 272         u32       PciSlotNumber;          /* PCI slot number       */
 273
 274         u16            DriverMajorVersion;
 275         u16            DriverMinorVersion;
 276         u16            DriverSubVersion;
 277
 278         u16            XilinxRevisionNumber;
 279         u16            MaxFrameSize;
 280
 281         u16               t1_alarm1_status;
 282         u16             t1_alarm2_status;
 283
 284         int             link_status;
 285         u32       mii_reg16;
 286
 287         u32       Magic1;                         /* DEADBEEF */
 288 } LMC_XINFO;
 289
 290
 291 /*
 292  * forward decl
 293  */
 294 struct lmc___softc {
 295         char                   *name;
 296         u8                      board_idx;
 297         struct lmc_extra_statistics extra_stats;
 298         struct net_device      *lmc_device;
 299
 300         int                     hang, rxdesc, bad_packet, some_counter;
 301         u32                     txgo;
 302         struct lmc_regfile_t    lmc_csrs;
 303         volatile u32            lmc_txtick;
 304         volatile u32            lmc_rxtick;
 305         u32                     lmc_flags;
 306         u32                     lmc_intrmask;   /* our copy of csr_intr */
 307         u32                     lmc_cmdmode;    /* our copy of csr_cmdmode */
 308         u32                     lmc_busmode;    /* our copy of csr_busmode */
 309         u32                     lmc_gpio_io;    /* state of in/out settings */
 310         u32                     lmc_gpio;       /* state of outputs */
 311         struct sk_buff*         lmc_txq[LMC_TXDESCS];
 312         struct sk_buff*         lmc_rxq[LMC_RXDESCS];
 313         volatile
 314         struct tulip_desc_t     lmc_rxring[LMC_RXDESCS];
 315         volatile
 316         struct tulip_desc_t     lmc_txring[LMC_TXDESCS];
 317         unsigned int            lmc_next_rx, lmc_next_tx;
 318         volatile
 319         unsigned int            lmc_taint_tx, lmc_taint_rx;
 320         int                     lmc_tx_start, lmc_txfull;
 321         int                     lmc_txbusy;
 322         u16                     lmc_miireg16;
 323         int                     lmc_ok;
 324         int                     last_link_status;
 325         int                     lmc_cardtype;
 326         u32                     last_frameerr;
 327         lmc_media_t            *lmc_media;
 328         struct timer_list       timer;
 329         lmc_ctl_t               ictl;
 330         u32                     TxDescriptControlInit;
 331
 332         int                     tx_TimeoutInd; /* additional driver state */
 333         int                     tx_TimeoutDisplay;
 334         unsigned int            lastlmc_taint_tx;
 335         int                     lasttx_packets;
 336         u32                     tx_clockState;
 337         u32                     lmc_crcSize;
 338         LMC_XINFO               lmc_xinfo;
 339         char                    lmc_yel, lmc_blue, lmc_red; /* for T1 and DS3 */
 340         char                    lmc_timing; /* for HSSI and SSI */
 341         int                     got_irq;
 342
 343         char                    last_led_err[4];
 344
 345         u32                     last_int;
 346         u32                     num_int;
 347
 348         spinlock_t              lmc_lock;
 349         u16                     if_type;       /* HDLC/PPP or NET */
 350
 351         /* Failure cases */
 352         u8                      failed_ring;
 353         u8                      failed_recv_alloc;
 354
 355         /* Structure check */
 356         u32                     check;
 357 };
 358
 359 #define LMC_PCI_TIME 1
 360 #define LMC_EXT_TIME 0
 361
 362 #define PKT_BUF_SZ              1542  /* was 1536 */
 363
 364 /* CSR5 settings */
 365 #define TIMER_INT     0x00000800
 366 #define TP_LINK_FAIL  0x00001000
 367 #define TP_LINK_PASS  0x00000010
 368 #define NORMAL_INT    0x00010000
 369 #define ABNORMAL_INT  0x00008000
 370 #define RX_JABBER_INT 0x00000200
 371 #define RX_DIED       0x00000100
 372 #define RX_NOBUFF     0x00000080
 373 #define RX_INT        0x00000040
 374 #define TX_FIFO_UNDER 0x00000020
 375 #define TX_JABBER     0x00000008
 376 #define TX_NOBUFF     0x00000004
 377 #define TX_DIED       0x00000002
 378 #define TX_INT        0x00000001
 379
 380 /* CSR6 settings */
 381 #define OPERATION_MODE  0x00000200 /* Full Duplex      */
 382 #define PROMISC_MODE    0x00000040 /* Promiscuous Mode */
 383 #define RECIEVE_ALL     0x40000000 /* Recieve All      */
 384 #define PASS_BAD_FRAMES 0x00000008 /* Pass Bad Frames  */
 385
 386 /* Dec control registers  CSR6 as well */
 387 #define LMC_DEC_ST 0x00002000
 388 #define LMC_DEC_SR 0x00000002
 389
 390 /* CSR15 settings */
 391 #define RECV_WATCHDOG_DISABLE 0x00000010
 392 #define JABBER_DISABLE        0x00000001
 393
 394 /* More settings */
 395 /*
 396  * aSR6 -- Command (Operation Mode) Register
 397  */
 398 #define TULIP_CMD_RECEIVEALL    0x40000000L /* (RW)  Receivel all frames? */
 399 #define TULIP_CMD_MUSTBEONE     0x02000000L /* (RW)  Must Be One (21140) */
 400 #define TULIP_CMD_TXTHRSHLDCTL  0x00400000L /* (RW)  Transmit Threshold Mode (21140) */
 401 #define TULIP_CMD_STOREFWD      0x00200000L /* (RW)  Store and Foward (21140) */
 402 #define TULIP_CMD_NOHEARTBEAT   0x00080000L /* (RW)  No Heartbeat (21140) */
 403 #define TULIP_CMD_PORTSELECT    0x00040000L /* (RW)  Post Select (100Mb) (21140) */
 404 #define TULIP_CMD_FULLDUPLEX    0x00000200L /* (RW)  Full Duplex Mode */
 405 #define TULIP_CMD_OPERMODE      0x00000C00L /* (RW)  Operating Mode */
 406 #define TULIP_CMD_PROMISCUOUS   0x00000041L /* (RW)  Promiscuous Mode */
 407 #define TULIP_CMD_PASSBADPKT    0x00000008L /* (RW)  Pass Bad Frames */
 408 #define TULIP_CMD_THRESHOLDCTL  0x0000C000L /* (RW)  Threshold Control */
 409
 410 #define TULIP_GP_PINSET         0x00000100L
 411 #define TULIP_BUSMODE_SWRESET   0x00000001L
 412 #define TULIP_WATCHDOG_TXDISABLE 0x00000001L
 413 #define TULIP_WATCHDOG_RXDISABLE 0x00000010L
 414
 415 #define TULIP_STS_NORMALINTR    0x00010000L /* (RW)  Normal Interrupt */
 416 #define TULIP_STS_ABNRMLINTR    0x00008000L /* (RW)  Abnormal Interrupt */
 417 #define TULIP_STS_ERI           0x00004000L /* (RW)  Early Receive Interrupt */
 418 #define TULIP_STS_SYSERROR      0x00002000L /* (RW)  System Error */
 419 #define TULIP_STS_GTE           0x00000800L /* (RW)  General Pupose Timer Exp */
 420 #define TULIP_STS_ETI           0x00000400L /* (RW)  Early Transmit Interrupt */
 421 #define TULIP_STS_RXWT          0x00000200L /* (RW)  Receiver Watchdog Timeout */
 422 #define TULIP_STS_RXSTOPPED     0x00000100L /* (RW)  Receiver Process Stopped */
 423 #define TULIP_STS_RXNOBUF       0x00000080L /* (RW)  Receive Buf Unavail */
 424 #define TULIP_STS_RXINTR        0x00000040L /* (RW)  Receive Interrupt */
 425 #define TULIP_STS_TXUNDERFLOW   0x00000020L /* (RW)  Transmit Underflow */
 426 #define TULIP_STS_TXJABER       0x00000008L /* (RW)  Jabber timeout */
 427 #define TULIP_STS_TXNOBUF       0x00000004L
 428 #define TULIP_STS_TXSTOPPED     0x00000002L /* (RW)  Transmit Process Stopped */
 429 #define TULIP_STS_TXINTR        0x00000001L /* (RW)  Transmit Interrupt */
 430
 431 #define TULIP_STS_RXS_STOPPED   0x00000000L /*        000 - Stopped */
 432
 433 #define TULIP_STS_RXSTOPPED     0x00000100L             /* (RW)  Receive Process Stopped */
 434 #define TULIP_STS_RXNOBUF       0x00000080L
 435
 436 #define TULIP_CMD_TXRUN         0x00002000L /* (RW)  Start/Stop Transmitter */
 437 #define TULIP_CMD_RXRUN         0x00000002L /* (RW)  Start/Stop Receive Filtering */
 438 #define TULIP_DSTS_TxDEFERRED   0x00000001      /* Initially Deferred */
 439 #define TULIP_DSTS_OWNER        0x80000000      /* Owner (1 = 21040) */
 440 #define TULIP_DSTS_RxMIIERR     0x00000008
 441 #define LMC_DSTS_ERRSUM         (TULIP_DSTS_RxMIIERR)
 442
 443 #define TULIP_DEFAULT_INTR_MASK  (TULIP_STS_NORMALINTR \
 444   | TULIP_STS_RXINTR       \
 445   | TULIP_STS_TXINTR     \
 446   | TULIP_STS_ABNRMLINTR \
 447   | TULIP_STS_SYSERROR   \
 448   | TULIP_STS_TXSTOPPED  \
 449   | TULIP_STS_TXUNDERFLOW\
 450   | TULIP_STS_RXSTOPPED )
 451
 452 #define DESC_OWNED_BY_SYSTEM   ((u32)(0x00000000))
 453 #define DESC_OWNED_BY_DC21X4   ((u32)(0x80000000))
 454
 455 #ifndef TULIP_CMD_RECEIVEALL
 456 #define TULIP_CMD_RECEIVEALL 0x40000000L
 457 #endif
 458
 459 /* Adapter module number */
 460 #define LMC_ADAP_HSSI           2
 461 #define LMC_ADAP_DS3            3
 462 #define LMC_ADAP_SSI            4
 463 #define LMC_ADAP_T1             5
 464
 465 #define LMC_MTU 1500
 466
 467 #define LMC_CRC_LEN_16 2  /* 16-bit CRC */
 468 #define LMC_CRC_LEN_32 4
 469
 470 #endif /* _LMC_VAR_H_ */