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mac80211: small rate control changes
[linux/fpc-iii.git] / drivers / net / mv643xx_eth.c
blob0a18b9e96da152db6c55eaa0026cc578863226eb
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
37
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/in.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
53 #include <asm/io.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
56
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
59
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
63
64 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
65 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66 #else
67 #define MAX_DESCS_PER_SKB 1
68 #endif
69
70 /*
71 * Registers shared between all ports.
72 */
73 #define PHY_ADDR 0x0000
74 #define SMI_REG 0x0004
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
80
81 /*
82 * Per-port registers.
83 */
84 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TX_IN_PROGRESS 0x00000080
94 #define PORT_SPEED_MASK 0x00000030
95 #define PORT_SPEED_1000 0x00000010
96 #define PORT_SPEED_100 0x00000020
97 #define PORT_SPEED_10 0x00000000
98 #define FLOW_CONTROL_ENABLED 0x00000008
99 #define FULL_DUPLEX 0x00000004
100 #define LINK_UP 0x00000002
101 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
102 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
103 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
104 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
105 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
106 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
107 #define INT_TX_END_0 0x00080000
108 #define INT_TX_END 0x07f80000
109 #define INT_RX 0x0007fbfc
110 #define INT_EXT 0x00000002
111 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
112 #define INT_EXT_LINK 0x00100000
113 #define INT_EXT_PHY 0x00010000
114 #define INT_EXT_TX_ERROR_0 0x00000100
115 #define INT_EXT_TX_0 0x00000001
116 #define INT_EXT_TX 0x0000ffff
117 #define INT_MASK(p) (0x0468 + ((p) << 10))
118 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
119 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
120 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
121 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
122 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
123 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
124 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
125 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
126 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
127 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
128 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
129 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
130 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
134
135
136 /*
137 * SDMA configuration register.
138 */
139 #define RX_BURST_SIZE_16_64BIT (4 << 1)
140 #define BLM_RX_NO_SWAP (1 << 4)
141 #define BLM_TX_NO_SWAP (1 << 5)
142 #define TX_BURST_SIZE_16_64BIT (4 << 22)
143
144 #if defined(__BIG_ENDIAN)
145 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
146 RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT
148 #elif defined(__LITTLE_ENDIAN)
149 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
150 RX_BURST_SIZE_16_64BIT | \
151 BLM_RX_NO_SWAP | \
152 BLM_TX_NO_SWAP | \
153 TX_BURST_SIZE_16_64BIT
154 #else
155 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
156 #endif
157
158
159 /*
160 * Port serial control register.
161 */
162 #define SET_MII_SPEED_TO_100 (1 << 24)
163 #define SET_GMII_SPEED_TO_1000 (1 << 23)
164 #define SET_FULL_DUPLEX_MODE (1 << 21)
165 #define MAX_RX_PACKET_9700BYTE (5 << 17)
166 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
167 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
168 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
169 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
170 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
171 #define FORCE_LINK_PASS (1 << 1)
172 #define SERIAL_PORT_ENABLE (1 << 0)
173
174 #define DEFAULT_RX_QUEUE_SIZE 400
175 #define DEFAULT_TX_QUEUE_SIZE 800
176
177
178 /*
179 * RX/TX descriptors.
180 */
181 #if defined(__BIG_ENDIAN)
182 struct rx_desc {
183 u16 byte_cnt; /* Descriptor buffer byte count */
184 u16 buf_size; /* Buffer size */
185 u32 cmd_sts; /* Descriptor command status */
186 u32 next_desc_ptr; /* Next descriptor pointer */
187 u32 buf_ptr; /* Descriptor buffer pointer */
188 };
189
190 struct tx_desc {
191 u16 byte_cnt; /* buffer byte count */
192 u16 l4i_chk; /* CPU provided TCP checksum */
193 u32 cmd_sts; /* Command/status field */
194 u32 next_desc_ptr; /* Pointer to next descriptor */
195 u32 buf_ptr; /* pointer to buffer for this descriptor*/
196 };
197 #elif defined(__LITTLE_ENDIAN)
198 struct rx_desc {
199 u32 cmd_sts; /* Descriptor command status */
200 u16 buf_size; /* Buffer size */
201 u16 byte_cnt; /* Descriptor buffer byte count */
202 u32 buf_ptr; /* Descriptor buffer pointer */
203 u32 next_desc_ptr; /* Next descriptor pointer */
204 };
205
206 struct tx_desc {
207 u32 cmd_sts; /* Command/status field */
208 u16 l4i_chk; /* CPU provided TCP checksum */
209 u16 byte_cnt; /* buffer byte count */
210 u32 buf_ptr; /* pointer to buffer for this descriptor*/
211 u32 next_desc_ptr; /* Pointer to next descriptor */
212 };
213 #else
214 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
215 #endif
216
217 /* RX & TX descriptor command */
218 #define BUFFER_OWNED_BY_DMA 0x80000000
219
220 /* RX & TX descriptor status */
221 #define ERROR_SUMMARY 0x00000001
222
223 /* RX descriptor status */
224 #define LAYER_4_CHECKSUM_OK 0x40000000
225 #define RX_ENABLE_INTERRUPT 0x20000000
226 #define RX_FIRST_DESC 0x08000000
227 #define RX_LAST_DESC 0x04000000
228
229 /* TX descriptor command */
230 #define TX_ENABLE_INTERRUPT 0x00800000
231 #define GEN_CRC 0x00400000
232 #define TX_FIRST_DESC 0x00200000
233 #define TX_LAST_DESC 0x00100000
234 #define ZERO_PADDING 0x00080000
235 #define GEN_IP_V4_CHECKSUM 0x00040000
236 #define GEN_TCP_UDP_CHECKSUM 0x00020000
237 #define UDP_FRAME 0x00010000
238 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
239 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
240
241 #define TX_IHL_SHIFT 11
242
243
244 /* global *******************************************************************/
245 struct mv643xx_eth_shared_private {
246 /*
247 * Ethernet controller base address.
248 */
249 void __iomem *base;
250
251 /*
252 * Protects access to SMI_REG, which is shared between ports.
253 */
254 spinlock_t phy_lock;
255
256 /*
257 * Per-port MBUS window access register value.
258 */
259 u32 win_protect;
260
261 /*
262 * Hardware-specific parameters.
263 */
264 unsigned int t_clk;
265 int extended_rx_coal_limit;
266 int tx_bw_control_moved;
267 };
268
269
270 /* per-port *****************************************************************/
271 struct mib_counters {
272 u64 good_octets_received;
273 u32 bad_octets_received;
274 u32 internal_mac_transmit_err;
275 u32 good_frames_received;
276 u32 bad_frames_received;
277 u32 broadcast_frames_received;
278 u32 multicast_frames_received;
279 u32 frames_64_octets;
280 u32 frames_65_to_127_octets;
281 u32 frames_128_to_255_octets;
282 u32 frames_256_to_511_octets;
283 u32 frames_512_to_1023_octets;
284 u32 frames_1024_to_max_octets;
285 u64 good_octets_sent;
286 u32 good_frames_sent;
287 u32 excessive_collision;
288 u32 multicast_frames_sent;
289 u32 broadcast_frames_sent;
290 u32 unrec_mac_control_received;
291 u32 fc_sent;
292 u32 good_fc_received;
293 u32 bad_fc_received;
294 u32 undersize_received;
295 u32 fragments_received;
296 u32 oversize_received;
297 u32 jabber_received;
298 u32 mac_receive_error;
299 u32 bad_crc_event;
300 u32 collision;
301 u32 late_collision;
302 };
303
304 struct rx_queue {
305 int index;
306
307 int rx_ring_size;
308
309 int rx_desc_count;
310 int rx_curr_desc;
311 int rx_used_desc;
312
313 struct rx_desc *rx_desc_area;
314 dma_addr_t rx_desc_dma;
315 int rx_desc_area_size;
316 struct sk_buff **rx_skb;
317
318 struct timer_list rx_oom;
319 };
320
321 struct tx_queue {
322 int index;
323
324 int tx_ring_size;
325
326 int tx_desc_count;
327 int tx_curr_desc;
328 int tx_used_desc;
329
330 struct tx_desc *tx_desc_area;
331 dma_addr_t tx_desc_dma;
332 int tx_desc_area_size;
333 struct sk_buff **tx_skb;
334 };
335
336 struct mv643xx_eth_private {
337 struct mv643xx_eth_shared_private *shared;
338 int port_num;
339
340 struct net_device *dev;
341
342 struct mv643xx_eth_shared_private *shared_smi;
343 int phy_addr;
344
345 spinlock_t lock;
346
347 struct mib_counters mib_counters;
348 struct work_struct tx_timeout_task;
349 struct mii_if_info mii;
350
351 /*
352 * RX state.
353 */
354 int default_rx_ring_size;
355 unsigned long rx_desc_sram_addr;
356 int rx_desc_sram_size;
357 u8 rxq_mask;
358 int rxq_primary;
359 struct napi_struct napi;
360 struct rx_queue rxq[8];
361
362 /*
363 * TX state.
364 */
365 int default_tx_ring_size;
366 unsigned long tx_desc_sram_addr;
367 int tx_desc_sram_size;
368 u8 txq_mask;
369 int txq_primary;
370 struct tx_queue txq[8];
371 #ifdef MV643XX_ETH_TX_FAST_REFILL
372 int tx_clean_threshold;
373 #endif
374 };
375
376
377 /* port register accessors **************************************************/
378 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
379 {
380 return readl(mp->shared->base + offset);
381 }
382
383 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
384 {
385 writel(data, mp->shared->base + offset);
386 }
387
388
389 /* rxq/txq helper functions *************************************************/
390 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
391 {
392 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
393 }
394
395 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
396 {
397 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
398 }
399
400 static void rxq_enable(struct rx_queue *rxq)
401 {
402 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
403 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
404 }
405
406 static void rxq_disable(struct rx_queue *rxq)
407 {
408 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
409 u8 mask = 1 << rxq->index;
410
411 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
412 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
413 udelay(10);
414 }
415
416 static void txq_reset_hw_ptr(struct tx_queue *txq)
417 {
418 struct mv643xx_eth_private *mp = txq_to_mp(txq);
419 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
420 u32 addr;
421
422 addr = (u32)txq->tx_desc_dma;
423 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
424 wrl(mp, off, addr);
425 }
426
427 static void txq_enable(struct tx_queue *txq)
428 {
429 struct mv643xx_eth_private *mp = txq_to_mp(txq);
430 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
431 }
432
433 static void txq_disable(struct tx_queue *txq)
434 {
435 struct mv643xx_eth_private *mp = txq_to_mp(txq);
436 u8 mask = 1 << txq->index;
437
438 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
439 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
440 udelay(10);
441 }
442
443 static void __txq_maybe_wake(struct tx_queue *txq)
444 {
445 struct mv643xx_eth_private *mp = txq_to_mp(txq);
446
447 /*
448 * netif_{stop,wake}_queue() flow control only applies to
449 * the primary queue.
450 */
451 BUG_ON(txq->index != mp->txq_primary);
452
453 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
454 netif_wake_queue(mp->dev);
455 }
456
457
458 /* rx ***********************************************************************/
459 static void txq_reclaim(struct tx_queue *txq, int force);
460
461 static void rxq_refill(struct rx_queue *rxq)
462 {
463 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
464 unsigned long flags;
465
466 spin_lock_irqsave(&mp->lock, flags);
467
468 while (rxq->rx_desc_count < rxq->rx_ring_size) {
469 int skb_size;
470 struct sk_buff *skb;
471 int unaligned;
472 int rx;
473
474 /*
475 * Reserve 2+14 bytes for an ethernet header (the
476 * hardware automatically prepends 2 bytes of dummy
477 * data to each received packet), 16 bytes for up to
478 * four VLAN tags, and 4 bytes for the trailing FCS
479 * -- 36 bytes total.
480 */
481 skb_size = mp->dev->mtu + 36;
482
483 /*
484 * Make sure that the skb size is a multiple of 8
485 * bytes, as the lower three bits of the receive
486 * descriptor's buffer size field are ignored by
487 * the hardware.
488 */
489 skb_size = (skb_size + 7) & ~7;
490
491 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
492 if (skb == NULL)
493 break;
494
495 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
496 if (unaligned)
497 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
498
499 rxq->rx_desc_count++;
500 rx = rxq->rx_used_desc;
501 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
502
503 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
504 skb_size, DMA_FROM_DEVICE);
505 rxq->rx_desc_area[rx].buf_size = skb_size;
506 rxq->rx_skb[rx] = skb;
507 wmb();
508 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
509 RX_ENABLE_INTERRUPT;
510 wmb();
511
512 /*
513 * The hardware automatically prepends 2 bytes of
514 * dummy data to each received packet, so that the
515 * IP header ends up 16-byte aligned.
516 */
517 skb_reserve(skb, 2);
518 }
519
520 if (rxq->rx_desc_count != rxq->rx_ring_size)
521 mod_timer(&rxq->rx_oom, jiffies + (HZ / 10));
522
523 spin_unlock_irqrestore(&mp->lock, flags);
524 }
525
526 static inline void rxq_refill_timer_wrapper(unsigned long data)
527 {
528 rxq_refill((struct rx_queue *)data);
529 }
530
531 static int rxq_process(struct rx_queue *rxq, int budget)
532 {
533 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
534 struct net_device_stats *stats = &mp->dev->stats;
535 int rx;
536
537 rx = 0;
538 while (rx < budget && rxq->rx_desc_count) {
539 struct rx_desc *rx_desc;
540 unsigned int cmd_sts;
541 struct sk_buff *skb;
542 unsigned long flags;
543
544 spin_lock_irqsave(&mp->lock, flags);
545
546 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
547
548 cmd_sts = rx_desc->cmd_sts;
549 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
550 spin_unlock_irqrestore(&mp->lock, flags);
551 break;
552 }
553 rmb();
554
555 skb = rxq->rx_skb[rxq->rx_curr_desc];
556 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
557
558 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
559
560 spin_unlock_irqrestore(&mp->lock, flags);
561
562 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
563 rx_desc->buf_size, DMA_FROM_DEVICE);
564 rxq->rx_desc_count--;
565 rx++;
566
567 /*
568 * Update statistics.
569 *
570 * Note that the descriptor byte count includes 2 dummy
571 * bytes automatically inserted by the hardware at the
572 * start of the packet (which we don't count), and a 4
573 * byte CRC at the end of the packet (which we do count).
574 */
575 stats->rx_packets++;
576 stats->rx_bytes += rx_desc->byte_cnt - 2;
577
578 /*
579 * In case we received a packet without first / last bits
580 * on, or the error summary bit is set, the packet needs
581 * to be dropped.
582 */
583 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
584 (RX_FIRST_DESC | RX_LAST_DESC))
585 || (cmd_sts & ERROR_SUMMARY)) {
586 stats->rx_dropped++;
587
588 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
589 (RX_FIRST_DESC | RX_LAST_DESC)) {
590 if (net_ratelimit())
591 dev_printk(KERN_ERR, &mp->dev->dev,
592 "received packet spanning "
593 "multiple descriptors\n");
594 }
595
596 if (cmd_sts & ERROR_SUMMARY)
597 stats->rx_errors++;
598
599 dev_kfree_skb_irq(skb);
600 } else {
601 /*
602 * The -4 is for the CRC in the trailer of the
603 * received packet
604 */
605 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
606
607 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
608 skb->ip_summed = CHECKSUM_UNNECESSARY;
609 skb->csum = htons(
610 (cmd_sts & 0x0007fff8) >> 3);
611 }
612 skb->protocol = eth_type_trans(skb, mp->dev);
613 #ifdef MV643XX_ETH_NAPI
614 netif_receive_skb(skb);
615 #else
616 netif_rx(skb);
617 #endif
618 }
619
620 mp->dev->last_rx = jiffies;
621 }
622
623 rxq_refill(rxq);
624
625 return rx;
626 }
627
628 #ifdef MV643XX_ETH_NAPI
629 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
630 {
631 struct mv643xx_eth_private *mp;
632 int rx;
633 int i;
634
635 mp = container_of(napi, struct mv643xx_eth_private, napi);
636
637 #ifdef MV643XX_ETH_TX_FAST_REFILL
638 if (++mp->tx_clean_threshold > 5) {
639 mp->tx_clean_threshold = 0;
640 for (i = 0; i < 8; i++)
641 if (mp->txq_mask & (1 << i))
642 txq_reclaim(mp->txq + i, 0);
643
644 if (netif_carrier_ok(mp->dev)) {
645 spin_lock_irq(&mp->lock);
646 __txq_maybe_wake(mp->txq + mp->txq_primary);
647 spin_unlock_irq(&mp->lock);
648 }
649 }
650 #endif
651
652 rx = 0;
653 for (i = 7; rx < budget && i >= 0; i--)
654 if (mp->rxq_mask & (1 << i))
655 rx += rxq_process(mp->rxq + i, budget - rx);
656
657 if (rx < budget) {
658 netif_rx_complete(mp->dev, napi);
659 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
660 }
661
662 return rx;
663 }
664 #endif
665
666
667 /* tx ***********************************************************************/
668 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
669 {
670 int frag;
671
672 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
673 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
674 if (fragp->size <= 8 && fragp->page_offset & 7)
675 return 1;
676 }
677
678 return 0;
679 }
680
681 static int txq_alloc_desc_index(struct tx_queue *txq)
682 {
683 int tx_desc_curr;
684
685 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
686
687 tx_desc_curr = txq->tx_curr_desc;
688 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
689
690 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
691
692 return tx_desc_curr;
693 }
694
695 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
696 {
697 int nr_frags = skb_shinfo(skb)->nr_frags;
698 int frag;
699
700 for (frag = 0; frag < nr_frags; frag++) {
701 skb_frag_t *this_frag;
702 int tx_index;
703 struct tx_desc *desc;
704
705 this_frag = &skb_shinfo(skb)->frags[frag];
706 tx_index = txq_alloc_desc_index(txq);
707 desc = &txq->tx_desc_area[tx_index];
708
709 /*
710 * The last fragment will generate an interrupt
711 * which will free the skb on TX completion.
712 */
713 if (frag == nr_frags - 1) {
714 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
715 ZERO_PADDING | TX_LAST_DESC |
716 TX_ENABLE_INTERRUPT;
717 txq->tx_skb[tx_index] = skb;
718 } else {
719 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
720 txq->tx_skb[tx_index] = NULL;
721 }
722
723 desc->l4i_chk = 0;
724 desc->byte_cnt = this_frag->size;
725 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
726 this_frag->page_offset,
727 this_frag->size,
728 DMA_TO_DEVICE);
729 }
730 }
731
732 static inline __be16 sum16_as_be(__sum16 sum)
733 {
734 return (__force __be16)sum;
735 }
736
737 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
738 {
739 struct mv643xx_eth_private *mp = txq_to_mp(txq);
740 int nr_frags = skb_shinfo(skb)->nr_frags;
741 int tx_index;
742 struct tx_desc *desc;
743 u32 cmd_sts;
744 int length;
745
746 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
747
748 tx_index = txq_alloc_desc_index(txq);
749 desc = &txq->tx_desc_area[tx_index];
750
751 if (nr_frags) {
752 txq_submit_frag_skb(txq, skb);
753
754 length = skb_headlen(skb);
755 txq->tx_skb[tx_index] = NULL;
756 } else {
757 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
758 length = skb->len;
759 txq->tx_skb[tx_index] = skb;
760 }
761
762 desc->byte_cnt = length;
763 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
764
765 if (skb->ip_summed == CHECKSUM_PARTIAL) {
766 int mac_hdr_len;
767
768 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
769 skb->protocol != htons(ETH_P_8021Q));
770
771 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
772 GEN_IP_V4_CHECKSUM |
773 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
774
775 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
776 switch (mac_hdr_len - ETH_HLEN) {
777 case 0:
778 break;
779 case 4:
780 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
781 break;
782 case 8:
783 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
784 break;
785 case 12:
786 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
787 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
788 break;
789 default:
790 if (net_ratelimit())
791 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
792 "mac header length is %d?!\n", mac_hdr_len);
793 break;
794 }
795
796 switch (ip_hdr(skb)->protocol) {
797 case IPPROTO_UDP:
798 cmd_sts |= UDP_FRAME;
799 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
800 break;
801 case IPPROTO_TCP:
802 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
803 break;
804 default:
805 BUG();
806 }
807 } else {
808 /* Errata BTS #50, IHL must be 5 if no HW checksum */
809 cmd_sts |= 5 << TX_IHL_SHIFT;
810 desc->l4i_chk = 0;
811 }
812
813 /* ensure all other descriptors are written before first cmd_sts */
814 wmb();
815 desc->cmd_sts = cmd_sts;
816
817 /* clear TX_END interrupt status */
818 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
819 rdl(mp, INT_CAUSE(mp->port_num));
820
821 /* ensure all descriptors are written before poking hardware */
822 wmb();
823 txq_enable(txq);
824
825 txq->tx_desc_count += nr_frags + 1;
826 }
827
828 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
829 {
830 struct mv643xx_eth_private *mp = netdev_priv(dev);
831 struct net_device_stats *stats = &dev->stats;
832 struct tx_queue *txq;
833 unsigned long flags;
834
835 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
836 stats->tx_dropped++;
837 dev_printk(KERN_DEBUG, &dev->dev,
838 "failed to linearize skb with tiny "
839 "unaligned fragment\n");
840 return NETDEV_TX_BUSY;
841 }
842
843 spin_lock_irqsave(&mp->lock, flags);
844
845 txq = mp->txq + mp->txq_primary;
846
847 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
848 spin_unlock_irqrestore(&mp->lock, flags);
849 if (txq->index == mp->txq_primary && net_ratelimit())
850 dev_printk(KERN_ERR, &dev->dev,
851 "primary tx queue full?!\n");
852 kfree_skb(skb);
853 return NETDEV_TX_OK;
854 }
855
856 txq_submit_skb(txq, skb);
857 stats->tx_bytes += skb->len;
858 stats->tx_packets++;
859 dev->trans_start = jiffies;
860
861 if (txq->index == mp->txq_primary) {
862 int entries_left;
863
864 entries_left = txq->tx_ring_size - txq->tx_desc_count;
865 if (entries_left < MAX_DESCS_PER_SKB)
866 netif_stop_queue(dev);
867 }
868
869 spin_unlock_irqrestore(&mp->lock, flags);
870
871 return NETDEV_TX_OK;
872 }
873
874
875 /* tx rate control **********************************************************/
876 /*
877 * Set total maximum TX rate (shared by all TX queues for this port)
878 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
879 */
880 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
881 {
882 int token_rate;
883 int mtu;
884 int bucket_size;
885
886 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
887 if (token_rate > 1023)
888 token_rate = 1023;
889
890 mtu = (mp->dev->mtu + 255) >> 8;
891 if (mtu > 63)
892 mtu = 63;
893
894 bucket_size = (burst + 255) >> 8;
895 if (bucket_size > 65535)
896 bucket_size = 65535;
897
898 if (mp->shared->tx_bw_control_moved) {
899 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
900 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
901 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
902 } else {
903 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
904 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
905 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
906 }
907 }
908
909 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
910 {
911 struct mv643xx_eth_private *mp = txq_to_mp(txq);
912 int token_rate;
913 int bucket_size;
914
915 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
916 if (token_rate > 1023)
917 token_rate = 1023;
918
919 bucket_size = (burst + 255) >> 8;
920 if (bucket_size > 65535)
921 bucket_size = 65535;
922
923 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
924 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
925 (bucket_size << 10) | token_rate);
926 }
927
928 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
929 {
930 struct mv643xx_eth_private *mp = txq_to_mp(txq);
931 int off;
932 u32 val;
933
934 /*
935 * Turn on fixed priority mode.
936 */
937 if (mp->shared->tx_bw_control_moved)
938 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
939 else
940 off = TXQ_FIX_PRIO_CONF(mp->port_num);
941
942 val = rdl(mp, off);
943 val |= 1 << txq->index;
944 wrl(mp, off, val);
945 }
946
947 static void txq_set_wrr(struct tx_queue *txq, int weight)
948 {
949 struct mv643xx_eth_private *mp = txq_to_mp(txq);
950 int off;
951 u32 val;
952
953 /*
954 * Turn off fixed priority mode.
955 */
956 if (mp->shared->tx_bw_control_moved)
957 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
958 else
959 off = TXQ_FIX_PRIO_CONF(mp->port_num);
960
961 val = rdl(mp, off);
962 val &= ~(1 << txq->index);
963 wrl(mp, off, val);
964
965 /*
966 * Configure WRR weight for this queue.
967 */
968 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
969
970 val = rdl(mp, off);
971 val = (val & ~0xff) | (weight & 0xff);
972 wrl(mp, off, val);
973 }
974
975
976 /* mii management interface *************************************************/
977 #define SMI_BUSY 0x10000000
978 #define SMI_READ_VALID 0x08000000
979 #define SMI_OPCODE_READ 0x04000000
980 #define SMI_OPCODE_WRITE 0x00000000
981
982 static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
983 unsigned int reg, unsigned int *value)
984 {
985 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
986 unsigned long flags;
987 int i;
988
989 /* the SMI register is a shared resource */
990 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
991
992 /* wait for the SMI register to become available */
993 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
994 if (i == 1000) {
995 printk("%s: PHY busy timeout\n", mp->dev->name);
996 goto out;
997 }
998 udelay(10);
999 }
1000
1001 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1002
1003 /* now wait for the data to be valid */
1004 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
1005 if (i == 1000) {
1006 printk("%s: PHY read timeout\n", mp->dev->name);
1007 goto out;
1008 }
1009 udelay(10);
1010 }
1011
1012 *value = readl(smi_reg) & 0xffff;
1013 out:
1014 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1015 }
1016
1017 static void smi_reg_write(struct mv643xx_eth_private *mp,
1018 unsigned int addr,
1019 unsigned int reg, unsigned int value)
1020 {
1021 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
1022 unsigned long flags;
1023 int i;
1024
1025 /* the SMI register is a shared resource */
1026 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1027
1028 /* wait for the SMI register to become available */
1029 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
1030 if (i == 1000) {
1031 printk("%s: PHY busy timeout\n", mp->dev->name);
1032 goto out;
1033 }
1034 udelay(10);
1035 }
1036
1037 writel(SMI_OPCODE_WRITE | (reg << 21) |
1038 (addr << 16) | (value & 0xffff), smi_reg);
1039 out:
1040 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1041 }
1042
1043
1044 /* mib counters *************************************************************/
1045 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1046 {
1047 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1048 }
1049
1050 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1051 {
1052 int i;
1053
1054 for (i = 0; i < 0x80; i += 4)
1055 mib_read(mp, i);
1056 }
1057
1058 static void mib_counters_update(struct mv643xx_eth_private *mp)
1059 {
1060 struct mib_counters *p = &mp->mib_counters;
1061
1062 p->good_octets_received += mib_read(mp, 0x00);
1063 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1064 p->bad_octets_received += mib_read(mp, 0x08);
1065 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1066 p->good_frames_received += mib_read(mp, 0x10);
1067 p->bad_frames_received += mib_read(mp, 0x14);
1068 p->broadcast_frames_received += mib_read(mp, 0x18);
1069 p->multicast_frames_received += mib_read(mp, 0x1c);
1070 p->frames_64_octets += mib_read(mp, 0x20);
1071 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1072 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1073 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1074 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1075 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1076 p->good_octets_sent += mib_read(mp, 0x38);
1077 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1078 p->good_frames_sent += mib_read(mp, 0x40);
1079 p->excessive_collision += mib_read(mp, 0x44);
1080 p->multicast_frames_sent += mib_read(mp, 0x48);
1081 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1082 p->unrec_mac_control_received += mib_read(mp, 0x50);
1083 p->fc_sent += mib_read(mp, 0x54);
1084 p->good_fc_received += mib_read(mp, 0x58);
1085 p->bad_fc_received += mib_read(mp, 0x5c);
1086 p->undersize_received += mib_read(mp, 0x60);
1087 p->fragments_received += mib_read(mp, 0x64);
1088 p->oversize_received += mib_read(mp, 0x68);
1089 p->jabber_received += mib_read(mp, 0x6c);
1090 p->mac_receive_error += mib_read(mp, 0x70);
1091 p->bad_crc_event += mib_read(mp, 0x74);
1092 p->collision += mib_read(mp, 0x78);
1093 p->late_collision += mib_read(mp, 0x7c);
1094 }
1095
1096
1097 /* ethtool ******************************************************************/
1098 struct mv643xx_eth_stats {
1099 char stat_string[ETH_GSTRING_LEN];
1100 int sizeof_stat;
1101 int netdev_off;
1102 int mp_off;
1103 };
1104
1105 #define SSTAT(m) \
1106 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1107 offsetof(struct net_device, stats.m), -1 }
1108
1109 #define MIBSTAT(m) \
1110 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1111 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1112
1113 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1114 SSTAT(rx_packets),
1115 SSTAT(tx_packets),
1116 SSTAT(rx_bytes),
1117 SSTAT(tx_bytes),
1118 SSTAT(rx_errors),
1119 SSTAT(tx_errors),
1120 SSTAT(rx_dropped),
1121 SSTAT(tx_dropped),
1122 MIBSTAT(good_octets_received),
1123 MIBSTAT(bad_octets_received),
1124 MIBSTAT(internal_mac_transmit_err),
1125 MIBSTAT(good_frames_received),
1126 MIBSTAT(bad_frames_received),
1127 MIBSTAT(broadcast_frames_received),
1128 MIBSTAT(multicast_frames_received),
1129 MIBSTAT(frames_64_octets),
1130 MIBSTAT(frames_65_to_127_octets),
1131 MIBSTAT(frames_128_to_255_octets),
1132 MIBSTAT(frames_256_to_511_octets),
1133 MIBSTAT(frames_512_to_1023_octets),
1134 MIBSTAT(frames_1024_to_max_octets),
1135 MIBSTAT(good_octets_sent),
1136 MIBSTAT(good_frames_sent),
1137 MIBSTAT(excessive_collision),
1138 MIBSTAT(multicast_frames_sent),
1139 MIBSTAT(broadcast_frames_sent),
1140 MIBSTAT(unrec_mac_control_received),
1141 MIBSTAT(fc_sent),
1142 MIBSTAT(good_fc_received),
1143 MIBSTAT(bad_fc_received),
1144 MIBSTAT(undersize_received),
1145 MIBSTAT(fragments_received),
1146 MIBSTAT(oversize_received),
1147 MIBSTAT(jabber_received),
1148 MIBSTAT(mac_receive_error),
1149 MIBSTAT(bad_crc_event),
1150 MIBSTAT(collision),
1151 MIBSTAT(late_collision),
1152 };
1153
1154 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1155 {
1156 struct mv643xx_eth_private *mp = netdev_priv(dev);
1157 int err;
1158
1159 spin_lock_irq(&mp->lock);
1160 err = mii_ethtool_gset(&mp->mii, cmd);
1161 spin_unlock_irq(&mp->lock);
1162
1163 /*
1164 * The MAC does not support 1000baseT_Half.
1165 */
1166 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1167 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1168
1169 return err;
1170 }
1171
1172 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1173 {
1174 struct mv643xx_eth_private *mp = netdev_priv(dev);
1175 u32 port_status;
1176
1177 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1178
1179 cmd->supported = SUPPORTED_MII;
1180 cmd->advertising = ADVERTISED_MII;
1181 switch (port_status & PORT_SPEED_MASK) {
1182 case PORT_SPEED_10:
1183 cmd->speed = SPEED_10;
1184 break;
1185 case PORT_SPEED_100:
1186 cmd->speed = SPEED_100;
1187 break;
1188 case PORT_SPEED_1000:
1189 cmd->speed = SPEED_1000;
1190 break;
1191 default:
1192 cmd->speed = -1;
1193 break;
1194 }
1195 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1196 cmd->port = PORT_MII;
1197 cmd->phy_address = 0;
1198 cmd->transceiver = XCVR_INTERNAL;
1199 cmd->autoneg = AUTONEG_DISABLE;
1200 cmd->maxtxpkt = 1;
1201 cmd->maxrxpkt = 1;
1202
1203 return 0;
1204 }
1205
1206 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1207 {
1208 struct mv643xx_eth_private *mp = netdev_priv(dev);
1209 int err;
1210
1211 /*
1212 * The MAC does not support 1000baseT_Half.
1213 */
1214 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1215
1216 spin_lock_irq(&mp->lock);
1217 err = mii_ethtool_sset(&mp->mii, cmd);
1218 spin_unlock_irq(&mp->lock);
1219
1220 return err;
1221 }
1222
1223 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1224 {
1225 return -EINVAL;
1226 }
1227
1228 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1229 struct ethtool_drvinfo *drvinfo)
1230 {
1231 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1232 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1233 strncpy(drvinfo->fw_version, "N/A", 32);
1234 strncpy(drvinfo->bus_info, "platform", 32);
1235 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1236 }
1237
1238 static int mv643xx_eth_nway_reset(struct net_device *dev)
1239 {
1240 struct mv643xx_eth_private *mp = netdev_priv(dev);
1241
1242 return mii_nway_restart(&mp->mii);
1243 }
1244
1245 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1246 {
1247 return -EINVAL;
1248 }
1249
1250 static u32 mv643xx_eth_get_link(struct net_device *dev)
1251 {
1252 struct mv643xx_eth_private *mp = netdev_priv(dev);
1253
1254 return mii_link_ok(&mp->mii);
1255 }
1256
1257 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1258 {
1259 return 1;
1260 }
1261
1262 static void mv643xx_eth_get_strings(struct net_device *dev,
1263 uint32_t stringset, uint8_t *data)
1264 {
1265 int i;
1266
1267 if (stringset == ETH_SS_STATS) {
1268 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1269 memcpy(data + i * ETH_GSTRING_LEN,
1270 mv643xx_eth_stats[i].stat_string,
1271 ETH_GSTRING_LEN);
1272 }
1273 }
1274 }
1275
1276 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1277 struct ethtool_stats *stats,
1278 uint64_t *data)
1279 {
1280 struct mv643xx_eth_private *mp = dev->priv;
1281 int i;
1282
1283 mib_counters_update(mp);
1284
1285 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1286 const struct mv643xx_eth_stats *stat;
1287 void *p;
1288
1289 stat = mv643xx_eth_stats + i;
1290
1291 if (stat->netdev_off >= 0)
1292 p = ((void *)mp->dev) + stat->netdev_off;
1293 else
1294 p = ((void *)mp) + stat->mp_off;
1295
1296 data[i] = (stat->sizeof_stat == 8) ?
1297 *(uint64_t *)p : *(uint32_t *)p;
1298 }
1299 }
1300
1301 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1302 {
1303 if (sset == ETH_SS_STATS)
1304 return ARRAY_SIZE(mv643xx_eth_stats);
1305
1306 return -EOPNOTSUPP;
1307 }
1308
1309 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1310 .get_settings = mv643xx_eth_get_settings,
1311 .set_settings = mv643xx_eth_set_settings,
1312 .get_drvinfo = mv643xx_eth_get_drvinfo,
1313 .nway_reset = mv643xx_eth_nway_reset,
1314 .get_link = mv643xx_eth_get_link,
1315 .set_sg = ethtool_op_set_sg,
1316 .get_strings = mv643xx_eth_get_strings,
1317 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1318 .get_sset_count = mv643xx_eth_get_sset_count,
1319 };
1320
1321 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1322 .get_settings = mv643xx_eth_get_settings_phyless,
1323 .set_settings = mv643xx_eth_set_settings_phyless,
1324 .get_drvinfo = mv643xx_eth_get_drvinfo,
1325 .nway_reset = mv643xx_eth_nway_reset_phyless,
1326 .get_link = mv643xx_eth_get_link_phyless,
1327 .set_sg = ethtool_op_set_sg,
1328 .get_strings = mv643xx_eth_get_strings,
1329 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1330 .get_sset_count = mv643xx_eth_get_sset_count,
1331 };
1332
1333
1334 /* address handling *********************************************************/
1335 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1336 {
1337 unsigned int mac_h;
1338 unsigned int mac_l;
1339
1340 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1341 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1342
1343 addr[0] = (mac_h >> 24) & 0xff;
1344 addr[1] = (mac_h >> 16) & 0xff;
1345 addr[2] = (mac_h >> 8) & 0xff;
1346 addr[3] = mac_h & 0xff;
1347 addr[4] = (mac_l >> 8) & 0xff;
1348 addr[5] = mac_l & 0xff;
1349 }
1350
1351 static void init_mac_tables(struct mv643xx_eth_private *mp)
1352 {
1353 int i;
1354
1355 for (i = 0; i < 0x100; i += 4) {
1356 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1357 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1358 }
1359
1360 for (i = 0; i < 0x10; i += 4)
1361 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1362 }
1363
1364 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1365 int table, unsigned char entry)
1366 {
1367 unsigned int table_reg;
1368
1369 /* Set "accepts frame bit" at specified table entry */
1370 table_reg = rdl(mp, table + (entry & 0xfc));
1371 table_reg |= 0x01 << (8 * (entry & 3));
1372 wrl(mp, table + (entry & 0xfc), table_reg);
1373 }
1374
1375 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1376 {
1377 unsigned int mac_h;
1378 unsigned int mac_l;
1379 int table;
1380
1381 mac_l = (addr[4] << 8) | addr[5];
1382 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1383
1384 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1385 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1386
1387 table = UNICAST_TABLE(mp->port_num);
1388 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1389 }
1390
1391 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1392 {
1393 struct mv643xx_eth_private *mp = netdev_priv(dev);
1394
1395 /* +2 is for the offset of the HW addr type */
1396 memcpy(dev->dev_addr, addr + 2, 6);
1397
1398 init_mac_tables(mp);
1399 uc_addr_set(mp, dev->dev_addr);
1400
1401 return 0;
1402 }
1403
1404 static int addr_crc(unsigned char *addr)
1405 {
1406 int crc = 0;
1407 int i;
1408
1409 for (i = 0; i < 6; i++) {
1410 int j;
1411
1412 crc = (crc ^ addr[i]) << 8;
1413 for (j = 7; j >= 0; j--) {
1414 if (crc & (0x100 << j))
1415 crc ^= 0x107 << j;
1416 }
1417 }
1418
1419 return crc;
1420 }
1421
1422 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1423 {
1424 struct mv643xx_eth_private *mp = netdev_priv(dev);
1425 u32 port_config;
1426 struct dev_addr_list *addr;
1427 int i;
1428
1429 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1430 if (dev->flags & IFF_PROMISC)
1431 port_config |= UNICAST_PROMISCUOUS_MODE;
1432 else
1433 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1434 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1435
1436 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1437 int port_num = mp->port_num;
1438 u32 accept = 0x01010101;
1439
1440 for (i = 0; i < 0x100; i += 4) {
1441 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1442 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1443 }
1444 return;
1445 }
1446
1447 for (i = 0; i < 0x100; i += 4) {
1448 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1449 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1450 }
1451
1452 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1453 u8 *a = addr->da_addr;
1454 int table;
1455
1456 if (addr->da_addrlen != 6)
1457 continue;
1458
1459 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1460 table = SPECIAL_MCAST_TABLE(mp->port_num);
1461 set_filter_table_entry(mp, table, a[5]);
1462 } else {
1463 int crc = addr_crc(a);
1464
1465 table = OTHER_MCAST_TABLE(mp->port_num);
1466 set_filter_table_entry(mp, table, crc);
1467 }
1468 }
1469 }
1470
1471
1472 /* rx/tx queue initialisation ***********************************************/
1473 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1474 {
1475 struct rx_queue *rxq = mp->rxq + index;
1476 struct rx_desc *rx_desc;
1477 int size;
1478 int i;
1479
1480 rxq->index = index;
1481
1482 rxq->rx_ring_size = mp->default_rx_ring_size;
1483
1484 rxq->rx_desc_count = 0;
1485 rxq->rx_curr_desc = 0;
1486 rxq->rx_used_desc = 0;
1487
1488 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1489
1490 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1491 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1492 mp->rx_desc_sram_size);
1493 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1494 } else {
1495 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1496 &rxq->rx_desc_dma,
1497 GFP_KERNEL);
1498 }
1499
1500 if (rxq->rx_desc_area == NULL) {
1501 dev_printk(KERN_ERR, &mp->dev->dev,
1502 "can't allocate rx ring (%d bytes)\n", size);
1503 goto out;
1504 }
1505 memset(rxq->rx_desc_area, 0, size);
1506
1507 rxq->rx_desc_area_size = size;
1508 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1509 GFP_KERNEL);
1510 if (rxq->rx_skb == NULL) {
1511 dev_printk(KERN_ERR, &mp->dev->dev,
1512 "can't allocate rx skb ring\n");
1513 goto out_free;
1514 }
1515
1516 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1517 for (i = 0; i < rxq->rx_ring_size; i++) {
1518 int nexti = (i + 1) % rxq->rx_ring_size;
1519 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1520 nexti * sizeof(struct rx_desc);
1521 }
1522
1523 init_timer(&rxq->rx_oom);
1524 rxq->rx_oom.data = (unsigned long)rxq;
1525 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1526
1527 return 0;
1528
1529
1530 out_free:
1531 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1532 iounmap(rxq->rx_desc_area);
1533 else
1534 dma_free_coherent(NULL, size,
1535 rxq->rx_desc_area,
1536 rxq->rx_desc_dma);
1537
1538 out:
1539 return -ENOMEM;
1540 }
1541
1542 static void rxq_deinit(struct rx_queue *rxq)
1543 {
1544 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1545 int i;
1546
1547 rxq_disable(rxq);
1548
1549 del_timer_sync(&rxq->rx_oom);
1550
1551 for (i = 0; i < rxq->rx_ring_size; i++) {
1552 if (rxq->rx_skb[i]) {
1553 dev_kfree_skb(rxq->rx_skb[i]);
1554 rxq->rx_desc_count--;
1555 }
1556 }
1557
1558 if (rxq->rx_desc_count) {
1559 dev_printk(KERN_ERR, &mp->dev->dev,
1560 "error freeing rx ring -- %d skbs stuck\n",
1561 rxq->rx_desc_count);
1562 }
1563
1564 if (rxq->index == mp->rxq_primary &&
1565 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1566 iounmap(rxq->rx_desc_area);
1567 else
1568 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1569 rxq->rx_desc_area, rxq->rx_desc_dma);
1570
1571 kfree(rxq->rx_skb);
1572 }
1573
1574 static int txq_init(struct mv643xx_eth_private *mp, int index)
1575 {
1576 struct tx_queue *txq = mp->txq + index;
1577 struct tx_desc *tx_desc;
1578 int size;
1579 int i;
1580
1581 txq->index = index;
1582
1583 txq->tx_ring_size = mp->default_tx_ring_size;
1584
1585 txq->tx_desc_count = 0;
1586 txq->tx_curr_desc = 0;
1587 txq->tx_used_desc = 0;
1588
1589 size = txq->tx_ring_size * sizeof(struct tx_desc);
1590
1591 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1592 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1593 mp->tx_desc_sram_size);
1594 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1595 } else {
1596 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1597 &txq->tx_desc_dma,
1598 GFP_KERNEL);
1599 }
1600
1601 if (txq->tx_desc_area == NULL) {
1602 dev_printk(KERN_ERR, &mp->dev->dev,
1603 "can't allocate tx ring (%d bytes)\n", size);
1604 goto out;
1605 }
1606 memset(txq->tx_desc_area, 0, size);
1607
1608 txq->tx_desc_area_size = size;
1609 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1610 GFP_KERNEL);
1611 if (txq->tx_skb == NULL) {
1612 dev_printk(KERN_ERR, &mp->dev->dev,
1613 "can't allocate tx skb ring\n");
1614 goto out_free;
1615 }
1616
1617 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1618 for (i = 0; i < txq->tx_ring_size; i++) {
1619 struct tx_desc *txd = tx_desc + i;
1620 int nexti = (i + 1) % txq->tx_ring_size;
1621
1622 txd->cmd_sts = 0;
1623 txd->next_desc_ptr = txq->tx_desc_dma +
1624 nexti * sizeof(struct tx_desc);
1625 }
1626
1627 return 0;
1628
1629
1630 out_free:
1631 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1632 iounmap(txq->tx_desc_area);
1633 else
1634 dma_free_coherent(NULL, size,
1635 txq->tx_desc_area,
1636 txq->tx_desc_dma);
1637
1638 out:
1639 return -ENOMEM;
1640 }
1641
1642 static void txq_reclaim(struct tx_queue *txq, int force)
1643 {
1644 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1645 unsigned long flags;
1646
1647 spin_lock_irqsave(&mp->lock, flags);
1648 while (txq->tx_desc_count > 0) {
1649 int tx_index;
1650 struct tx_desc *desc;
1651 u32 cmd_sts;
1652 struct sk_buff *skb;
1653 dma_addr_t addr;
1654 int count;
1655
1656 tx_index = txq->tx_used_desc;
1657 desc = &txq->tx_desc_area[tx_index];
1658 cmd_sts = desc->cmd_sts;
1659
1660 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1661 if (!force)
1662 break;
1663 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1664 }
1665
1666 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1667 txq->tx_desc_count--;
1668
1669 addr = desc->buf_ptr;
1670 count = desc->byte_cnt;
1671 skb = txq->tx_skb[tx_index];
1672 txq->tx_skb[tx_index] = NULL;
1673
1674 if (cmd_sts & ERROR_SUMMARY) {
1675 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1676 mp->dev->stats.tx_errors++;
1677 }
1678
1679 /*
1680 * Drop mp->lock while we free the skb.
1681 */
1682 spin_unlock_irqrestore(&mp->lock, flags);
1683
1684 if (cmd_sts & TX_FIRST_DESC)
1685 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1686 else
1687 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1688
1689 if (skb)
1690 dev_kfree_skb_irq(skb);
1691
1692 spin_lock_irqsave(&mp->lock, flags);
1693 }
1694 spin_unlock_irqrestore(&mp->lock, flags);
1695 }
1696
1697 static void txq_deinit(struct tx_queue *txq)
1698 {
1699 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1700
1701 txq_disable(txq);
1702 txq_reclaim(txq, 1);
1703
1704 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1705
1706 if (txq->index == mp->txq_primary &&
1707 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1708 iounmap(txq->tx_desc_area);
1709 else
1710 dma_free_coherent(NULL, txq->tx_desc_area_size,
1711 txq->tx_desc_area, txq->tx_desc_dma);
1712
1713 kfree(txq->tx_skb);
1714 }
1715
1716
1717 /* netdev ops and related ***************************************************/
1718 static void handle_link_event(struct mv643xx_eth_private *mp)
1719 {
1720 struct net_device *dev = mp->dev;
1721 u32 port_status;
1722 int speed;
1723 int duplex;
1724 int fc;
1725
1726 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1727 if (!(port_status & LINK_UP)) {
1728 if (netif_carrier_ok(dev)) {
1729 int i;
1730
1731 printk(KERN_INFO "%s: link down\n", dev->name);
1732
1733 netif_carrier_off(dev);
1734 netif_stop_queue(dev);
1735
1736 for (i = 0; i < 8; i++) {
1737 struct tx_queue *txq = mp->txq + i;
1738
1739 if (mp->txq_mask & (1 << i)) {
1740 txq_reclaim(txq, 1);
1741 txq_reset_hw_ptr(txq);
1742 }
1743 }
1744 }
1745 return;
1746 }
1747
1748 switch (port_status & PORT_SPEED_MASK) {
1749 case PORT_SPEED_10:
1750 speed = 10;
1751 break;
1752 case PORT_SPEED_100:
1753 speed = 100;
1754 break;
1755 case PORT_SPEED_1000:
1756 speed = 1000;
1757 break;
1758 default:
1759 speed = -1;
1760 break;
1761 }
1762 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1763 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1764
1765 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1766 "flow control %sabled\n", dev->name,
1767 speed, duplex ? "full" : "half",
1768 fc ? "en" : "dis");
1769
1770 if (!netif_carrier_ok(dev)) {
1771 netif_carrier_on(dev);
1772 netif_wake_queue(dev);
1773 }
1774 }
1775
1776 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1777 {
1778 struct net_device *dev = (struct net_device *)dev_id;
1779 struct mv643xx_eth_private *mp = netdev_priv(dev);
1780 u32 int_cause;
1781 u32 int_cause_ext;
1782
1783 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1784 (INT_TX_END | INT_RX | INT_EXT);
1785 if (int_cause == 0)
1786 return IRQ_NONE;
1787
1788 int_cause_ext = 0;
1789 if (int_cause & INT_EXT) {
1790 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1791 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1792 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1793 }
1794
1795 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK))
1796 handle_link_event(mp);
1797
1798 /*
1799 * RxBuffer or RxError set for any of the 8 queues?
1800 */
1801 #ifdef MV643XX_ETH_NAPI
1802 if (int_cause & INT_RX) {
1803 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_RX));
1804 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1805 rdl(mp, INT_MASK(mp->port_num));
1806
1807 netif_rx_schedule(dev, &mp->napi);
1808 }
1809 #else
1810 if (int_cause & INT_RX) {
1811 int i;
1812
1813 for (i = 7; i >= 0; i--)
1814 if (mp->rxq_mask & (1 << i))
1815 rxq_process(mp->rxq + i, INT_MAX);
1816 }
1817 #endif
1818
1819 /*
1820 * TxBuffer or TxError set for any of the 8 queues?
1821 */
1822 if (int_cause_ext & INT_EXT_TX) {
1823 int i;
1824
1825 for (i = 0; i < 8; i++)
1826 if (mp->txq_mask & (1 << i))
1827 txq_reclaim(mp->txq + i, 0);
1828
1829 /*
1830 * Enough space again in the primary TX queue for a
1831 * full packet?
1832 */
1833 if (netif_carrier_ok(dev)) {
1834 spin_lock(&mp->lock);
1835 __txq_maybe_wake(mp->txq + mp->txq_primary);
1836 spin_unlock(&mp->lock);
1837 }
1838 }
1839
1840 /*
1841 * Any TxEnd interrupts?
1842 */
1843 if (int_cause & INT_TX_END) {
1844 int i;
1845
1846 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1847
1848 spin_lock(&mp->lock);
1849 for (i = 0; i < 8; i++) {
1850 struct tx_queue *txq = mp->txq + i;
1851 u32 hw_desc_ptr;
1852 u32 expected_ptr;
1853
1854 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1855 continue;
1856
1857 hw_desc_ptr =
1858 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1859 expected_ptr = (u32)txq->tx_desc_dma +
1860 txq->tx_curr_desc * sizeof(struct tx_desc);
1861
1862 if (hw_desc_ptr != expected_ptr)
1863 txq_enable(txq);
1864 }
1865 spin_unlock(&mp->lock);
1866 }
1867
1868 return IRQ_HANDLED;
1869 }
1870
1871 static void phy_reset(struct mv643xx_eth_private *mp)
1872 {
1873 unsigned int data;
1874
1875 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1876 data |= BMCR_RESET;
1877 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1878
1879 do {
1880 udelay(1);
1881 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1882 } while (data & BMCR_RESET);
1883 }
1884
1885 static void port_start(struct mv643xx_eth_private *mp)
1886 {
1887 u32 pscr;
1888 int i;
1889
1890 /*
1891 * Perform PHY reset, if there is a PHY.
1892 */
1893 if (mp->phy_addr != -1) {
1894 struct ethtool_cmd cmd;
1895
1896 mv643xx_eth_get_settings(mp->dev, &cmd);
1897 phy_reset(mp);
1898 mv643xx_eth_set_settings(mp->dev, &cmd);
1899 }
1900
1901 /*
1902 * Configure basic link parameters.
1903 */
1904 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1905
1906 pscr |= SERIAL_PORT_ENABLE;
1907 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1908
1909 pscr |= DO_NOT_FORCE_LINK_FAIL;
1910 if (mp->phy_addr == -1)
1911 pscr |= FORCE_LINK_PASS;
1912 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1913
1914 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1915
1916 /*
1917 * Configure TX path and queues.
1918 */
1919 tx_set_rate(mp, 1000000000, 16777216);
1920 for (i = 0; i < 8; i++) {
1921 struct tx_queue *txq = mp->txq + i;
1922
1923 if ((mp->txq_mask & (1 << i)) == 0)
1924 continue;
1925
1926 txq_reset_hw_ptr(txq);
1927 txq_set_rate(txq, 1000000000, 16777216);
1928 txq_set_fixed_prio_mode(txq);
1929 }
1930
1931 /*
1932 * Add configured unicast address to address filter table.
1933 */
1934 uc_addr_set(mp, mp->dev->dev_addr);
1935
1936 /*
1937 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1938 * frames to RX queue #0.
1939 */
1940 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1941
1942 /*
1943 * Treat BPDUs as normal multicasts, and disable partition mode.
1944 */
1945 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1946
1947 /*
1948 * Enable the receive queues.
1949 */
1950 for (i = 0; i < 8; i++) {
1951 struct rx_queue *rxq = mp->rxq + i;
1952 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1953 u32 addr;
1954
1955 if ((mp->rxq_mask & (1 << i)) == 0)
1956 continue;
1957
1958 addr = (u32)rxq->rx_desc_dma;
1959 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1960 wrl(mp, off, addr);
1961
1962 rxq_enable(rxq);
1963 }
1964 }
1965
1966 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1967 {
1968 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1969 u32 val;
1970
1971 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1972 if (mp->shared->extended_rx_coal_limit) {
1973 if (coal > 0xffff)
1974 coal = 0xffff;
1975 val &= ~0x023fff80;
1976 val |= (coal & 0x8000) << 10;
1977 val |= (coal & 0x7fff) << 7;
1978 } else {
1979 if (coal > 0x3fff)
1980 coal = 0x3fff;
1981 val &= ~0x003fff00;
1982 val |= (coal & 0x3fff) << 8;
1983 }
1984 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1985 }
1986
1987 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1988 {
1989 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1990
1991 if (coal > 0x3fff)
1992 coal = 0x3fff;
1993 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
1994 }
1995
1996 static int mv643xx_eth_open(struct net_device *dev)
1997 {
1998 struct mv643xx_eth_private *mp = netdev_priv(dev);
1999 int err;
2000 int i;
2001
2002 wrl(mp, INT_CAUSE(mp->port_num), 0);
2003 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2004 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2005
2006 err = request_irq(dev->irq, mv643xx_eth_irq,
2007 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
2008 dev->name, dev);
2009 if (err) {
2010 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2011 return -EAGAIN;
2012 }
2013
2014 init_mac_tables(mp);
2015
2016 for (i = 0; i < 8; i++) {
2017 if ((mp->rxq_mask & (1 << i)) == 0)
2018 continue;
2019
2020 err = rxq_init(mp, i);
2021 if (err) {
2022 while (--i >= 0)
2023 if (mp->rxq_mask & (1 << i))
2024 rxq_deinit(mp->rxq + i);
2025 goto out;
2026 }
2027
2028 rxq_refill(mp->rxq + i);
2029 }
2030
2031 for (i = 0; i < 8; i++) {
2032 if ((mp->txq_mask & (1 << i)) == 0)
2033 continue;
2034
2035 err = txq_init(mp, i);
2036 if (err) {
2037 while (--i >= 0)
2038 if (mp->txq_mask & (1 << i))
2039 txq_deinit(mp->txq + i);
2040 goto out_free;
2041 }
2042 }
2043
2044 #ifdef MV643XX_ETH_NAPI
2045 napi_enable(&mp->napi);
2046 #endif
2047
2048 netif_carrier_off(dev);
2049 netif_stop_queue(dev);
2050
2051 port_start(mp);
2052
2053 set_rx_coal(mp, 0);
2054 set_tx_coal(mp, 0);
2055
2056 wrl(mp, INT_MASK_EXT(mp->port_num),
2057 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2058
2059 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2060
2061 return 0;
2062
2063
2064 out_free:
2065 for (i = 0; i < 8; i++)
2066 if (mp->rxq_mask & (1 << i))
2067 rxq_deinit(mp->rxq + i);
2068 out:
2069 free_irq(dev->irq, dev);
2070
2071 return err;
2072 }
2073
2074 static void port_reset(struct mv643xx_eth_private *mp)
2075 {
2076 unsigned int data;
2077 int i;
2078
2079 for (i = 0; i < 8; i++) {
2080 if (mp->rxq_mask & (1 << i))
2081 rxq_disable(mp->rxq + i);
2082 if (mp->txq_mask & (1 << i))
2083 txq_disable(mp->txq + i);
2084 }
2085
2086 while (1) {
2087 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2088
2089 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2090 break;
2091 udelay(10);
2092 }
2093
2094 /* Reset the Enable bit in the Configuration Register */
2095 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2096 data &= ~(SERIAL_PORT_ENABLE |
2097 DO_NOT_FORCE_LINK_FAIL |
2098 FORCE_LINK_PASS);
2099 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2100 }
2101
2102 static int mv643xx_eth_stop(struct net_device *dev)
2103 {
2104 struct mv643xx_eth_private *mp = netdev_priv(dev);
2105 int i;
2106
2107 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2108 rdl(mp, INT_MASK(mp->port_num));
2109
2110 #ifdef MV643XX_ETH_NAPI
2111 napi_disable(&mp->napi);
2112 #endif
2113 netif_carrier_off(dev);
2114 netif_stop_queue(dev);
2115
2116 free_irq(dev->irq, dev);
2117
2118 port_reset(mp);
2119 mib_counters_update(mp);
2120
2121 for (i = 0; i < 8; i++) {
2122 if (mp->rxq_mask & (1 << i))
2123 rxq_deinit(mp->rxq + i);
2124 if (mp->txq_mask & (1 << i))
2125 txq_deinit(mp->txq + i);
2126 }
2127
2128 return 0;
2129 }
2130
2131 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2132 {
2133 struct mv643xx_eth_private *mp = netdev_priv(dev);
2134
2135 if (mp->phy_addr != -1)
2136 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2137
2138 return -EOPNOTSUPP;
2139 }
2140
2141 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2142 {
2143 struct mv643xx_eth_private *mp = netdev_priv(dev);
2144
2145 if (new_mtu < 64 || new_mtu > 9500)
2146 return -EINVAL;
2147
2148 dev->mtu = new_mtu;
2149 tx_set_rate(mp, 1000000000, 16777216);
2150
2151 if (!netif_running(dev))
2152 return 0;
2153
2154 /*
2155 * Stop and then re-open the interface. This will allocate RX
2156 * skbs of the new MTU.
2157 * There is a possible danger that the open will not succeed,
2158 * due to memory being full.
2159 */
2160 mv643xx_eth_stop(dev);
2161 if (mv643xx_eth_open(dev)) {
2162 dev_printk(KERN_ERR, &dev->dev,
2163 "fatal error on re-opening device after "
2164 "MTU change\n");
2165 }
2166
2167 return 0;
2168 }
2169
2170 static void tx_timeout_task(struct work_struct *ugly)
2171 {
2172 struct mv643xx_eth_private *mp;
2173
2174 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2175 if (netif_running(mp->dev)) {
2176 netif_stop_queue(mp->dev);
2177
2178 port_reset(mp);
2179 port_start(mp);
2180
2181 __txq_maybe_wake(mp->txq + mp->txq_primary);
2182 }
2183 }
2184
2185 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2186 {
2187 struct mv643xx_eth_private *mp = netdev_priv(dev);
2188
2189 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2190
2191 schedule_work(&mp->tx_timeout_task);
2192 }
2193
2194 #ifdef CONFIG_NET_POLL_CONTROLLER
2195 static void mv643xx_eth_netpoll(struct net_device *dev)
2196 {
2197 struct mv643xx_eth_private *mp = netdev_priv(dev);
2198
2199 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2200 rdl(mp, INT_MASK(mp->port_num));
2201
2202 mv643xx_eth_irq(dev->irq, dev);
2203
2204 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2205 }
2206 #endif
2207
2208 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2209 {
2210 struct mv643xx_eth_private *mp = netdev_priv(dev);
2211 int val;
2212
2213 smi_reg_read(mp, addr, reg, &val);
2214
2215 return val;
2216 }
2217
2218 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2219 {
2220 struct mv643xx_eth_private *mp = netdev_priv(dev);
2221 smi_reg_write(mp, addr, reg, val);
2222 }
2223
2224
2225 /* platform glue ************************************************************/
2226 static void
2227 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2228 struct mbus_dram_target_info *dram)
2229 {
2230 void __iomem *base = msp->base;
2231 u32 win_enable;
2232 u32 win_protect;
2233 int i;
2234
2235 for (i = 0; i < 6; i++) {
2236 writel(0, base + WINDOW_BASE(i));
2237 writel(0, base + WINDOW_SIZE(i));
2238 if (i < 4)
2239 writel(0, base + WINDOW_REMAP_HIGH(i));
2240 }
2241
2242 win_enable = 0x3f;
2243 win_protect = 0;
2244
2245 for (i = 0; i < dram->num_cs; i++) {
2246 struct mbus_dram_window *cs = dram->cs + i;
2247
2248 writel((cs->base & 0xffff0000) |
2249 (cs->mbus_attr << 8) |
2250 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2251 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2252
2253 win_enable &= ~(1 << i);
2254 win_protect |= 3 << (2 * i);
2255 }
2256
2257 writel(win_enable, base + WINDOW_BAR_ENABLE);
2258 msp->win_protect = win_protect;
2259 }
2260
2261 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2262 {
2263 /*
2264 * Check whether we have a 14-bit coal limit field in bits
2265 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2266 * SDMA config register.
2267 */
2268 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2269 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2270 msp->extended_rx_coal_limit = 1;
2271 else
2272 msp->extended_rx_coal_limit = 0;
2273
2274 /*
2275 * Check whether the TX rate control registers are in the
2276 * old or the new place.
2277 */
2278 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2279 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2280 msp->tx_bw_control_moved = 1;
2281 else
2282 msp->tx_bw_control_moved = 0;
2283 }
2284
2285 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2286 {
2287 static int mv643xx_eth_version_printed = 0;
2288 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2289 struct mv643xx_eth_shared_private *msp;
2290 struct resource *res;
2291 int ret;
2292
2293 if (!mv643xx_eth_version_printed++)
2294 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2295 "driver version %s\n", mv643xx_eth_driver_version);
2296
2297 ret = -EINVAL;
2298 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2299 if (res == NULL)
2300 goto out;
2301
2302 ret = -ENOMEM;
2303 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2304 if (msp == NULL)
2305 goto out;
2306 memset(msp, 0, sizeof(*msp));
2307
2308 msp->base = ioremap(res->start, res->end - res->start + 1);
2309 if (msp->base == NULL)
2310 goto out_free;
2311
2312 spin_lock_init(&msp->phy_lock);
2313
2314 /*
2315 * (Re-)program MBUS remapping windows if we are asked to.
2316 */
2317 if (pd != NULL && pd->dram != NULL)
2318 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2319
2320 /*
2321 * Detect hardware parameters.
2322 */
2323 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2324 infer_hw_params(msp);
2325
2326 platform_set_drvdata(pdev, msp);
2327
2328 return 0;
2329
2330 out_free:
2331 kfree(msp);
2332 out:
2333 return ret;
2334 }
2335
2336 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2337 {
2338 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2339
2340 iounmap(msp->base);
2341 kfree(msp);
2342
2343 return 0;
2344 }
2345
2346 static struct platform_driver mv643xx_eth_shared_driver = {
2347 .probe = mv643xx_eth_shared_probe,
2348 .remove = mv643xx_eth_shared_remove,
2349 .driver = {
2350 .name = MV643XX_ETH_SHARED_NAME,
2351 .owner = THIS_MODULE,
2352 },
2353 };
2354
2355 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2356 {
2357 int addr_shift = 5 * mp->port_num;
2358 u32 data;
2359
2360 data = rdl(mp, PHY_ADDR);
2361 data &= ~(0x1f << addr_shift);
2362 data |= (phy_addr & 0x1f) << addr_shift;
2363 wrl(mp, PHY_ADDR, data);
2364 }
2365
2366 static int phy_addr_get(struct mv643xx_eth_private *mp)
2367 {
2368 unsigned int data;
2369
2370 data = rdl(mp, PHY_ADDR);
2371
2372 return (data >> (5 * mp->port_num)) & 0x1f;
2373 }
2374
2375 static void set_params(struct mv643xx_eth_private *mp,
2376 struct mv643xx_eth_platform_data *pd)
2377 {
2378 struct net_device *dev = mp->dev;
2379
2380 if (is_valid_ether_addr(pd->mac_addr))
2381 memcpy(dev->dev_addr, pd->mac_addr, 6);
2382 else
2383 uc_addr_get(mp, dev->dev_addr);
2384
2385 if (pd->phy_addr == -1) {
2386 mp->shared_smi = NULL;
2387 mp->phy_addr = -1;
2388 } else {
2389 mp->shared_smi = mp->shared;
2390 if (pd->shared_smi != NULL)
2391 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2392
2393 if (pd->force_phy_addr || pd->phy_addr) {
2394 mp->phy_addr = pd->phy_addr & 0x3f;
2395 phy_addr_set(mp, mp->phy_addr);
2396 } else {
2397 mp->phy_addr = phy_addr_get(mp);
2398 }
2399 }
2400
2401 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2402 if (pd->rx_queue_size)
2403 mp->default_rx_ring_size = pd->rx_queue_size;
2404 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2405 mp->rx_desc_sram_size = pd->rx_sram_size;
2406
2407 if (pd->rx_queue_mask)
2408 mp->rxq_mask = pd->rx_queue_mask;
2409 else
2410 mp->rxq_mask = 0x01;
2411 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2412
2413 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2414 if (pd->tx_queue_size)
2415 mp->default_tx_ring_size = pd->tx_queue_size;
2416 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2417 mp->tx_desc_sram_size = pd->tx_sram_size;
2418
2419 if (pd->tx_queue_mask)
2420 mp->txq_mask = pd->tx_queue_mask;
2421 else
2422 mp->txq_mask = 0x01;
2423 mp->txq_primary = fls(mp->txq_mask) - 1;
2424 }
2425
2426 static int phy_detect(struct mv643xx_eth_private *mp)
2427 {
2428 unsigned int data;
2429 unsigned int data2;
2430
2431 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
2432 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE);
2433
2434 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data2);
2435 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2436 return -ENODEV;
2437
2438 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2439
2440 return 0;
2441 }
2442
2443 static int phy_init(struct mv643xx_eth_private *mp,
2444 struct mv643xx_eth_platform_data *pd)
2445 {
2446 struct ethtool_cmd cmd;
2447 int err;
2448
2449 err = phy_detect(mp);
2450 if (err) {
2451 dev_printk(KERN_INFO, &mp->dev->dev,
2452 "no PHY detected at addr %d\n", mp->phy_addr);
2453 return err;
2454 }
2455 phy_reset(mp);
2456
2457 mp->mii.phy_id = mp->phy_addr;
2458 mp->mii.phy_id_mask = 0x3f;
2459 mp->mii.reg_num_mask = 0x1f;
2460 mp->mii.dev = mp->dev;
2461 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2462 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2463
2464 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2465
2466 memset(&cmd, 0, sizeof(cmd));
2467
2468 cmd.port = PORT_MII;
2469 cmd.transceiver = XCVR_INTERNAL;
2470 cmd.phy_address = mp->phy_addr;
2471 if (pd->speed == 0) {
2472 cmd.autoneg = AUTONEG_ENABLE;
2473 cmd.speed = SPEED_100;
2474 cmd.advertising = ADVERTISED_10baseT_Half |
2475 ADVERTISED_10baseT_Full |
2476 ADVERTISED_100baseT_Half |
2477 ADVERTISED_100baseT_Full;
2478 if (mp->mii.supports_gmii)
2479 cmd.advertising |= ADVERTISED_1000baseT_Full;
2480 } else {
2481 cmd.autoneg = AUTONEG_DISABLE;
2482 cmd.speed = pd->speed;
2483 cmd.duplex = pd->duplex;
2484 }
2485
2486 mv643xx_eth_set_settings(mp->dev, &cmd);
2487
2488 return 0;
2489 }
2490
2491 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2492 {
2493 u32 pscr;
2494
2495 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2496 if (pscr & SERIAL_PORT_ENABLE) {
2497 pscr &= ~SERIAL_PORT_ENABLE;
2498 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2499 }
2500
2501 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2502 if (mp->phy_addr == -1) {
2503 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2504 if (speed == SPEED_1000)
2505 pscr |= SET_GMII_SPEED_TO_1000;
2506 else if (speed == SPEED_100)
2507 pscr |= SET_MII_SPEED_TO_100;
2508
2509 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2510
2511 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2512 if (duplex == DUPLEX_FULL)
2513 pscr |= SET_FULL_DUPLEX_MODE;
2514 }
2515
2516 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2517 }
2518
2519 static int mv643xx_eth_probe(struct platform_device *pdev)
2520 {
2521 struct mv643xx_eth_platform_data *pd;
2522 struct mv643xx_eth_private *mp;
2523 struct net_device *dev;
2524 struct resource *res;
2525 DECLARE_MAC_BUF(mac);
2526 int err;
2527
2528 pd = pdev->dev.platform_data;
2529 if (pd == NULL) {
2530 dev_printk(KERN_ERR, &pdev->dev,
2531 "no mv643xx_eth_platform_data\n");
2532 return -ENODEV;
2533 }
2534
2535 if (pd->shared == NULL) {
2536 dev_printk(KERN_ERR, &pdev->dev,
2537 "no mv643xx_eth_platform_data->shared\n");
2538 return -ENODEV;
2539 }
2540
2541 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2542 if (!dev)
2543 return -ENOMEM;
2544
2545 mp = netdev_priv(dev);
2546 platform_set_drvdata(pdev, mp);
2547
2548 mp->shared = platform_get_drvdata(pd->shared);
2549 mp->port_num = pd->port_number;
2550
2551 mp->dev = dev;
2552 #ifdef MV643XX_ETH_NAPI
2553 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2554 #endif
2555
2556 set_params(mp, pd);
2557
2558 spin_lock_init(&mp->lock);
2559
2560 mib_counters_clear(mp);
2561 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2562
2563 if (mp->phy_addr != -1) {
2564 err = phy_init(mp, pd);
2565 if (err)
2566 goto out;
2567
2568 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2569 } else {
2570 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2571 }
2572 init_pscr(mp, pd->speed, pd->duplex);
2573
2574
2575 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2576 BUG_ON(!res);
2577 dev->irq = res->start;
2578
2579 dev->hard_start_xmit = mv643xx_eth_xmit;
2580 dev->open = mv643xx_eth_open;
2581 dev->stop = mv643xx_eth_stop;
2582 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2583 dev->set_mac_address = mv643xx_eth_set_mac_address;
2584 dev->do_ioctl = mv643xx_eth_ioctl;
2585 dev->change_mtu = mv643xx_eth_change_mtu;
2586 dev->tx_timeout = mv643xx_eth_tx_timeout;
2587 #ifdef CONFIG_NET_POLL_CONTROLLER
2588 dev->poll_controller = mv643xx_eth_netpoll;
2589 #endif
2590 dev->watchdog_timeo = 2 * HZ;
2591 dev->base_addr = 0;
2592
2593 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2594 /*
2595 * Zero copy can only work if we use Discovery II memory. Else, we will
2596 * have to map the buffers to ISA memory which is only 16 MB
2597 */
2598 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2599 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2600 #endif
2601
2602 SET_NETDEV_DEV(dev, &pdev->dev);
2603
2604 if (mp->shared->win_protect)
2605 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2606
2607 err = register_netdev(dev);
2608 if (err)
2609 goto out;
2610
2611 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2612 mp->port_num, print_mac(mac, dev->dev_addr));
2613
2614 if (dev->features & NETIF_F_SG)
2615 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2616
2617 if (dev->features & NETIF_F_IP_CSUM)
2618 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2619
2620 #ifdef MV643XX_ETH_NAPI
2621 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2622 #endif
2623
2624 if (mp->tx_desc_sram_size > 0)
2625 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2626
2627 return 0;
2628
2629 out:
2630 free_netdev(dev);
2631
2632 return err;
2633 }
2634
2635 static int mv643xx_eth_remove(struct platform_device *pdev)
2636 {
2637 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2638
2639 unregister_netdev(mp->dev);
2640 flush_scheduled_work();
2641 free_netdev(mp->dev);
2642
2643 platform_set_drvdata(pdev, NULL);
2644
2645 return 0;
2646 }
2647
2648 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2649 {
2650 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2651
2652 /* Mask all interrupts on ethernet port */
2653 wrl(mp, INT_MASK(mp->port_num), 0);
2654 rdl(mp, INT_MASK(mp->port_num));
2655
2656 if (netif_running(mp->dev))
2657 port_reset(mp);
2658 }
2659
2660 static struct platform_driver mv643xx_eth_driver = {
2661 .probe = mv643xx_eth_probe,
2662 .remove = mv643xx_eth_remove,
2663 .shutdown = mv643xx_eth_shutdown,
2664 .driver = {
2665 .name = MV643XX_ETH_NAME,
2666 .owner = THIS_MODULE,
2667 },
2668 };
2669
2670 static int __init mv643xx_eth_init_module(void)
2671 {
2672 int rc;
2673
2674 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2675 if (!rc) {
2676 rc = platform_driver_register(&mv643xx_eth_driver);
2677 if (rc)
2678 platform_driver_unregister(&mv643xx_eth_shared_driver);
2679 }
2680
2681 return rc;
2682 }
2683 module_init(mv643xx_eth_init_module);
2684
2685 static void __exit mv643xx_eth_cleanup_module(void)
2686 {
2687 platform_driver_unregister(&mv643xx_eth_driver);
2688 platform_driver_unregister(&mv643xx_eth_shared_driver);
2689 }
2690 module_exit(mv643xx_eth_cleanup_module);
2691
2692 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2693 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2694 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2695 MODULE_LICENSE("GPL");
2696 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2697 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux with added FPC-III support