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jme: Fix device PM wakeup API usage
[linux/fpc-iii.git] / sound / soc / codecs / rt5651.c
blobea4b1c652a26cecdd29ec95920840008544510c8
1 /*
2 * rt5651.c -- RT5651 ALSA SoC audio codec driver
3 *
4 * Copyright 2014 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <linux/regmap.h>
19 #include <linux/platform_device.h>
20 #include <linux/spi/spi.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28
29 #include "rl6231.h"
30 #include "rt5651.h"
31
32 #define RT5651_DEVICE_ID_VALUE 0x6281
33
34 #define RT5651_PR_RANGE_BASE (0xff + 1)
35 #define RT5651_PR_SPACING 0x100
36
37 #define RT5651_PR_BASE (RT5651_PR_RANGE_BASE + (0 * RT5651_PR_SPACING))
38
39 static const struct regmap_range_cfg rt5651_ranges[] = {
40 { .name = "PR", .range_min = RT5651_PR_BASE,
41 .range_max = RT5651_PR_BASE + 0xb4,
42 .selector_reg = RT5651_PRIV_INDEX,
43 .selector_mask = 0xff,
44 .selector_shift = 0x0,
45 .window_start = RT5651_PRIV_DATA,
46 .window_len = 0x1, },
47 };
48
49 static struct reg_default init_list[] = {
50 {RT5651_PR_BASE + 0x3d, 0x3e00},
51 };
52
53 static const struct reg_default rt5651_reg[] = {
54 { 0x00, 0x0000 },
55 { 0x02, 0xc8c8 },
56 { 0x03, 0xc8c8 },
57 { 0x05, 0x0000 },
58 { 0x0d, 0x0000 },
59 { 0x0e, 0x0000 },
60 { 0x0f, 0x0808 },
61 { 0x10, 0x0808 },
62 { 0x19, 0xafaf },
63 { 0x1a, 0xafaf },
64 { 0x1b, 0x0c00 },
65 { 0x1c, 0x2f2f },
66 { 0x1d, 0x2f2f },
67 { 0x1e, 0x0000 },
68 { 0x27, 0x7860 },
69 { 0x28, 0x7070 },
70 { 0x29, 0x8080 },
71 { 0x2a, 0x5252 },
72 { 0x2b, 0x5454 },
73 { 0x2f, 0x0000 },
74 { 0x30, 0x5000 },
75 { 0x3b, 0x0000 },
76 { 0x3c, 0x006f },
77 { 0x3d, 0x0000 },
78 { 0x3e, 0x006f },
79 { 0x45, 0x6000 },
80 { 0x4d, 0x0000 },
81 { 0x4e, 0x0000 },
82 { 0x4f, 0x0279 },
83 { 0x50, 0x0000 },
84 { 0x51, 0x0000 },
85 { 0x52, 0x0279 },
86 { 0x53, 0xf000 },
87 { 0x61, 0x0000 },
88 { 0x62, 0x0000 },
89 { 0x63, 0x00c0 },
90 { 0x64, 0x0000 },
91 { 0x65, 0x0000 },
92 { 0x66, 0x0000 },
93 { 0x70, 0x8000 },
94 { 0x71, 0x8000 },
95 { 0x73, 0x1104 },
96 { 0x74, 0x0c00 },
97 { 0x75, 0x1400 },
98 { 0x77, 0x0c00 },
99 { 0x78, 0x4000 },
100 { 0x79, 0x0123 },
101 { 0x80, 0x0000 },
102 { 0x81, 0x0000 },
103 { 0x82, 0x0000 },
104 { 0x83, 0x0800 },
105 { 0x84, 0x0000 },
106 { 0x85, 0x0008 },
107 { 0x89, 0x0000 },
108 { 0x8e, 0x0004 },
109 { 0x8f, 0x1100 },
110 { 0x90, 0x0000 },
111 { 0x93, 0x2000 },
112 { 0x94, 0x0200 },
113 { 0xb0, 0x2080 },
114 { 0xb1, 0x0000 },
115 { 0xb4, 0x2206 },
116 { 0xb5, 0x1f00 },
117 { 0xb6, 0x0000 },
118 { 0xbb, 0x0000 },
119 { 0xbc, 0x0000 },
120 { 0xbd, 0x0000 },
121 { 0xbe, 0x0000 },
122 { 0xbf, 0x0000 },
123 { 0xc0, 0x0400 },
124 { 0xc1, 0x0000 },
125 { 0xc2, 0x0000 },
126 { 0xcf, 0x0013 },
127 { 0xd0, 0x0680 },
128 { 0xd1, 0x1c17 },
129 { 0xd3, 0xb320 },
130 { 0xd9, 0x0809 },
131 { 0xfa, 0x0010 },
132 { 0xfe, 0x10ec },
133 { 0xff, 0x6281 },
134 };
135
136 static bool rt5651_volatile_register(struct device *dev, unsigned int reg)
137 {
138 int i;
139
140 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
141 if ((reg >= rt5651_ranges[i].window_start &&
142 reg <= rt5651_ranges[i].window_start +
143 rt5651_ranges[i].window_len) ||
144 (reg >= rt5651_ranges[i].range_min &&
145 reg <= rt5651_ranges[i].range_max)) {
146 return true;
147 }
148 }
149
150 switch (reg) {
151 case RT5651_RESET:
152 case RT5651_PRIV_DATA:
153 case RT5651_EQ_CTRL1:
154 case RT5651_ALC_1:
155 case RT5651_IRQ_CTRL2:
156 case RT5651_INT_IRQ_ST:
157 case RT5651_PGM_REG_ARR1:
158 case RT5651_PGM_REG_ARR3:
159 case RT5651_VENDOR_ID:
160 case RT5651_DEVICE_ID:
161 return true;
162 default:
163 return false;
164 }
165 }
166
167 static bool rt5651_readable_register(struct device *dev, unsigned int reg)
168 {
169 int i;
170
171 for (i = 0; i < ARRAY_SIZE(rt5651_ranges); i++) {
172 if ((reg >= rt5651_ranges[i].window_start &&
173 reg <= rt5651_ranges[i].window_start +
174 rt5651_ranges[i].window_len) ||
175 (reg >= rt5651_ranges[i].range_min &&
176 reg <= rt5651_ranges[i].range_max)) {
177 return true;
178 }
179 }
180
181 switch (reg) {
182 case RT5651_RESET:
183 case RT5651_VERSION_ID:
184 case RT5651_VENDOR_ID:
185 case RT5651_DEVICE_ID:
186 case RT5651_HP_VOL:
187 case RT5651_LOUT_CTRL1:
188 case RT5651_LOUT_CTRL2:
189 case RT5651_IN1_IN2:
190 case RT5651_IN3:
191 case RT5651_INL1_INR1_VOL:
192 case RT5651_INL2_INR2_VOL:
193 case RT5651_DAC1_DIG_VOL:
194 case RT5651_DAC2_DIG_VOL:
195 case RT5651_DAC2_CTRL:
196 case RT5651_ADC_DIG_VOL:
197 case RT5651_ADC_DATA:
198 case RT5651_ADC_BST_VOL:
199 case RT5651_STO1_ADC_MIXER:
200 case RT5651_STO2_ADC_MIXER:
201 case RT5651_AD_DA_MIXER:
202 case RT5651_STO_DAC_MIXER:
203 case RT5651_DD_MIXER:
204 case RT5651_DIG_INF_DATA:
205 case RT5651_PDM_CTL:
206 case RT5651_REC_L1_MIXER:
207 case RT5651_REC_L2_MIXER:
208 case RT5651_REC_R1_MIXER:
209 case RT5651_REC_R2_MIXER:
210 case RT5651_HPO_MIXER:
211 case RT5651_OUT_L1_MIXER:
212 case RT5651_OUT_L2_MIXER:
213 case RT5651_OUT_L3_MIXER:
214 case RT5651_OUT_R1_MIXER:
215 case RT5651_OUT_R2_MIXER:
216 case RT5651_OUT_R3_MIXER:
217 case RT5651_LOUT_MIXER:
218 case RT5651_PWR_DIG1:
219 case RT5651_PWR_DIG2:
220 case RT5651_PWR_ANLG1:
221 case RT5651_PWR_ANLG2:
222 case RT5651_PWR_MIXER:
223 case RT5651_PWR_VOL:
224 case RT5651_PRIV_INDEX:
225 case RT5651_PRIV_DATA:
226 case RT5651_I2S1_SDP:
227 case RT5651_I2S2_SDP:
228 case RT5651_ADDA_CLK1:
229 case RT5651_ADDA_CLK2:
230 case RT5651_DMIC:
231 case RT5651_TDM_CTL_1:
232 case RT5651_TDM_CTL_2:
233 case RT5651_TDM_CTL_3:
234 case RT5651_GLB_CLK:
235 case RT5651_PLL_CTRL1:
236 case RT5651_PLL_CTRL2:
237 case RT5651_PLL_MODE_1:
238 case RT5651_PLL_MODE_2:
239 case RT5651_PLL_MODE_3:
240 case RT5651_PLL_MODE_4:
241 case RT5651_PLL_MODE_5:
242 case RT5651_PLL_MODE_6:
243 case RT5651_PLL_MODE_7:
244 case RT5651_DEPOP_M1:
245 case RT5651_DEPOP_M2:
246 case RT5651_DEPOP_M3:
247 case RT5651_CHARGE_PUMP:
248 case RT5651_MICBIAS:
249 case RT5651_A_JD_CTL1:
250 case RT5651_EQ_CTRL1:
251 case RT5651_EQ_CTRL2:
252 case RT5651_ALC_1:
253 case RT5651_ALC_2:
254 case RT5651_ALC_3:
255 case RT5651_JD_CTRL1:
256 case RT5651_JD_CTRL2:
257 case RT5651_IRQ_CTRL1:
258 case RT5651_IRQ_CTRL2:
259 case RT5651_INT_IRQ_ST:
260 case RT5651_GPIO_CTRL1:
261 case RT5651_GPIO_CTRL2:
262 case RT5651_GPIO_CTRL3:
263 case RT5651_PGM_REG_ARR1:
264 case RT5651_PGM_REG_ARR2:
265 case RT5651_PGM_REG_ARR3:
266 case RT5651_PGM_REG_ARR4:
267 case RT5651_PGM_REG_ARR5:
268 case RT5651_SCB_FUNC:
269 case RT5651_SCB_CTRL:
270 case RT5651_BASE_BACK:
271 case RT5651_MP3_PLUS1:
272 case RT5651_MP3_PLUS2:
273 case RT5651_ADJ_HPF_CTRL1:
274 case RT5651_ADJ_HPF_CTRL2:
275 case RT5651_HP_CALIB_AMP_DET:
276 case RT5651_HP_CALIB2:
277 case RT5651_SV_ZCD1:
278 case RT5651_SV_ZCD2:
279 case RT5651_D_MISC:
280 case RT5651_DUMMY2:
281 case RT5651_DUMMY3:
282 return true;
283 default:
284 return false;
285 }
286 }
287
288 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
289 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
290 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
291 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
292 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
293
294 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
295 static unsigned int bst_tlv[] = {
296 TLV_DB_RANGE_HEAD(7),
297 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
298 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
299 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
300 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
301 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
302 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
303 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
304 };
305
306 /* Interface data select */
307 static const char * const rt5651_data_select[] = {
308 "Normal", "Swap", "left copy to right", "right copy to left"};
309
310 static SOC_ENUM_SINGLE_DECL(rt5651_if2_dac_enum, RT5651_DIG_INF_DATA,
311 RT5651_IF2_DAC_SEL_SFT, rt5651_data_select);
312
313 static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_enum, RT5651_DIG_INF_DATA,
314 RT5651_IF2_ADC_SEL_SFT, rt5651_data_select);
315
316 static const struct snd_kcontrol_new rt5651_snd_controls[] = {
317 /* Headphone Output Volume */
318 SOC_DOUBLE_TLV("HP Playback Volume", RT5651_HP_VOL,
319 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
320 /* OUTPUT Control */
321 SOC_DOUBLE_TLV("OUT Playback Volume", RT5651_LOUT_CTRL1,
322 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT, 39, 1, out_vol_tlv),
323
324 /* DAC Digital Volume */
325 SOC_DOUBLE("DAC2 Playback Switch", RT5651_DAC2_CTRL,
326 RT5651_M_DAC_L2_VOL_SFT, RT5651_M_DAC_R2_VOL_SFT, 1, 1),
327 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5651_DAC1_DIG_VOL,
328 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
329 175, 0, dac_vol_tlv),
330 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5651_DAC2_DIG_VOL,
331 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
332 175, 0, dac_vol_tlv),
333 /* IN1/IN2 Control */
334 SOC_SINGLE_TLV("IN1 Boost", RT5651_IN1_IN2,
335 RT5651_BST_SFT1, 8, 0, bst_tlv),
336 SOC_SINGLE_TLV("IN2 Boost", RT5651_IN1_IN2,
337 RT5651_BST_SFT2, 8, 0, bst_tlv),
338 /* INL/INR Volume Control */
339 SOC_DOUBLE_TLV("IN Capture Volume", RT5651_INL1_INR1_VOL,
340 RT5651_INL_VOL_SFT, RT5651_INR_VOL_SFT,
341 31, 1, in_vol_tlv),
342 /* ADC Digital Volume Control */
343 SOC_DOUBLE("ADC Capture Switch", RT5651_ADC_DIG_VOL,
344 RT5651_L_MUTE_SFT, RT5651_R_MUTE_SFT, 1, 1),
345 SOC_DOUBLE_TLV("ADC Capture Volume", RT5651_ADC_DIG_VOL,
346 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
347 127, 0, adc_vol_tlv),
348 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5651_ADC_DATA,
349 RT5651_L_VOL_SFT, RT5651_R_VOL_SFT,
350 127, 0, adc_vol_tlv),
351 /* ADC Boost Volume Control */
352 SOC_DOUBLE_TLV("ADC Boost Gain", RT5651_ADC_BST_VOL,
353 RT5651_ADC_L_BST_SFT, RT5651_ADC_R_BST_SFT,
354 3, 0, adc_bst_tlv),
355
356 /* ASRC */
357 SOC_SINGLE("IF1 ASRC Switch", RT5651_PLL_MODE_1,
358 RT5651_STO1_T_SFT, 1, 0),
359 SOC_SINGLE("IF2 ASRC Switch", RT5651_PLL_MODE_1,
360 RT5651_STO2_T_SFT, 1, 0),
361 SOC_SINGLE("DMIC ASRC Switch", RT5651_PLL_MODE_1,
362 RT5651_DMIC_1_M_SFT, 1, 0),
363
364 SOC_ENUM("ADC IF2 Data Switch", rt5651_if2_adc_enum),
365 SOC_ENUM("DAC IF2 Data Switch", rt5651_if2_dac_enum),
366 };
367
368 /**
369 * set_dmic_clk - Set parameter of dmic.
370 *
371 * @w: DAPM widget.
372 * @kcontrol: The kcontrol of this widget.
373 * @event: Event id.
374 *
375 */
376 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
377 struct snd_kcontrol *kcontrol, int event)
378 {
379 struct snd_soc_codec *codec = w->codec;
380 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
381 int idx = -EINVAL;
382
383 idx = rl6231_calc_dmic_clk(rt5651->sysclk);
384
385 if (idx < 0)
386 dev_err(codec->dev, "Failed to set DMIC clock\n");
387 else
388 snd_soc_update_bits(codec, RT5651_DMIC, RT5651_DMIC_CLK_MASK,
389 idx << RT5651_DMIC_CLK_SFT);
390
391 return idx;
392 }
393
394 static int is_sysclk_from_pll(struct snd_soc_dapm_widget *source,
395 struct snd_soc_dapm_widget *sink)
396 {
397 unsigned int val;
398
399 val = snd_soc_read(source->codec, RT5651_GLB_CLK);
400 val &= RT5651_SCLK_SRC_MASK;
401 if (val == RT5651_SCLK_SRC_PLL1)
402 return 1;
403 else
404 return 0;
405 }
406
407 /* Digital Mixer */
408 static const struct snd_kcontrol_new rt5651_sto1_adc_l_mix[] = {
409 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
410 RT5651_M_STO1_ADC_L1_SFT, 1, 1),
411 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
412 RT5651_M_STO1_ADC_L2_SFT, 1, 1),
413 };
414
415 static const struct snd_kcontrol_new rt5651_sto1_adc_r_mix[] = {
416 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO1_ADC_MIXER,
417 RT5651_M_STO1_ADC_R1_SFT, 1, 1),
418 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO1_ADC_MIXER,
419 RT5651_M_STO1_ADC_R2_SFT, 1, 1),
420 };
421
422 static const struct snd_kcontrol_new rt5651_sto2_adc_l_mix[] = {
423 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
424 RT5651_M_STO2_ADC_L1_SFT, 1, 1),
425 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
426 RT5651_M_STO2_ADC_L2_SFT, 1, 1),
427 };
428
429 static const struct snd_kcontrol_new rt5651_sto2_adc_r_mix[] = {
430 SOC_DAPM_SINGLE("ADC1 Switch", RT5651_STO2_ADC_MIXER,
431 RT5651_M_STO2_ADC_R1_SFT, 1, 1),
432 SOC_DAPM_SINGLE("ADC2 Switch", RT5651_STO2_ADC_MIXER,
433 RT5651_M_STO2_ADC_R2_SFT, 1, 1),
434 };
435
436 static const struct snd_kcontrol_new rt5651_dac_l_mix[] = {
437 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
438 RT5651_M_ADCMIX_L_SFT, 1, 1),
439 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
440 RT5651_M_IF1_DAC_L_SFT, 1, 1),
441 };
442
443 static const struct snd_kcontrol_new rt5651_dac_r_mix[] = {
444 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5651_AD_DA_MIXER,
445 RT5651_M_ADCMIX_R_SFT, 1, 1),
446 SOC_DAPM_SINGLE("INF1 Switch", RT5651_AD_DA_MIXER,
447 RT5651_M_IF1_DAC_R_SFT, 1, 1),
448 };
449
450 static const struct snd_kcontrol_new rt5651_sto_dac_l_mix[] = {
451 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
452 RT5651_M_DAC_L1_MIXL_SFT, 1, 1),
453 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_STO_DAC_MIXER,
454 RT5651_M_DAC_L2_MIXL_SFT, 1, 1),
455 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
456 RT5651_M_DAC_R1_MIXL_SFT, 1, 1),
457 };
458
459 static const struct snd_kcontrol_new rt5651_sto_dac_r_mix[] = {
460 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_STO_DAC_MIXER,
461 RT5651_M_DAC_R1_MIXR_SFT, 1, 1),
462 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER,
463 RT5651_M_DAC_R2_MIXR_SFT, 1, 1),
464 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_STO_DAC_MIXER,
465 RT5651_M_DAC_L1_MIXR_SFT, 1, 1),
466 };
467
468 static const struct snd_kcontrol_new rt5651_dd_dac_l_mix[] = {
469 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_DD_MIXER,
470 RT5651_M_STO_DD_L1_SFT, 1, 1),
471 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
472 RT5651_M_STO_DD_L2_SFT, 1, 1),
473 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
474 RT5651_M_STO_DD_R2_L_SFT, 1, 1),
475 };
476
477 static const struct snd_kcontrol_new rt5651_dd_dac_r_mix[] = {
478 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_DD_MIXER,
479 RT5651_M_STO_DD_R1_SFT, 1, 1),
480 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
481 RT5651_M_STO_DD_R2_SFT, 1, 1),
482 SOC_DAPM_SINGLE("DAC L2 Switch", RT5651_DD_MIXER,
483 RT5651_M_STO_DD_L2_R_SFT, 1, 1),
484 };
485
486 /* Analog Input Mixer */
487 static const struct snd_kcontrol_new rt5651_rec_l_mix[] = {
488 SOC_DAPM_SINGLE("INL1 Switch", RT5651_REC_L2_MIXER,
489 RT5651_M_IN1_L_RM_L_SFT, 1, 1),
490 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_L2_MIXER,
491 RT5651_M_BST3_RM_L_SFT, 1, 1),
492 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_L2_MIXER,
493 RT5651_M_BST2_RM_L_SFT, 1, 1),
494 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_L2_MIXER,
495 RT5651_M_BST1_RM_L_SFT, 1, 1),
496 };
497
498 static const struct snd_kcontrol_new rt5651_rec_r_mix[] = {
499 SOC_DAPM_SINGLE("INR1 Switch", RT5651_REC_R2_MIXER,
500 RT5651_M_IN1_R_RM_R_SFT, 1, 1),
501 SOC_DAPM_SINGLE("BST3 Switch", RT5651_REC_R2_MIXER,
502 RT5651_M_BST3_RM_R_SFT, 1, 1),
503 SOC_DAPM_SINGLE("BST2 Switch", RT5651_REC_R2_MIXER,
504 RT5651_M_BST2_RM_R_SFT, 1, 1),
505 SOC_DAPM_SINGLE("BST1 Switch", RT5651_REC_R2_MIXER,
506 RT5651_M_BST1_RM_R_SFT, 1, 1),
507 };
508
509 /* Analog Output Mixer */
510
511 static const struct snd_kcontrol_new rt5651_out_l_mix[] = {
512 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_L3_MIXER,
513 RT5651_M_BST1_OM_L_SFT, 1, 1),
514 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_L3_MIXER,
515 RT5651_M_BST2_OM_L_SFT, 1, 1),
516 SOC_DAPM_SINGLE("INL1 Switch", RT5651_OUT_L3_MIXER,
517 RT5651_M_IN1_L_OM_L_SFT, 1, 1),
518 SOC_DAPM_SINGLE("REC MIXL Switch", RT5651_OUT_L3_MIXER,
519 RT5651_M_RM_L_OM_L_SFT, 1, 1),
520 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_OUT_L3_MIXER,
521 RT5651_M_DAC_L1_OM_L_SFT, 1, 1),
522 };
523
524 static const struct snd_kcontrol_new rt5651_out_r_mix[] = {
525 SOC_DAPM_SINGLE("BST2 Switch", RT5651_OUT_R3_MIXER,
526 RT5651_M_BST2_OM_R_SFT, 1, 1),
527 SOC_DAPM_SINGLE("BST1 Switch", RT5651_OUT_R3_MIXER,
528 RT5651_M_BST1_OM_R_SFT, 1, 1),
529 SOC_DAPM_SINGLE("INR1 Switch", RT5651_OUT_R3_MIXER,
530 RT5651_M_IN1_R_OM_R_SFT, 1, 1),
531 SOC_DAPM_SINGLE("REC MIXR Switch", RT5651_OUT_R3_MIXER,
532 RT5651_M_RM_R_OM_R_SFT, 1, 1),
533 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_OUT_R3_MIXER,
534 RT5651_M_DAC_R1_OM_R_SFT, 1, 1),
535 };
536
537 static const struct snd_kcontrol_new rt5651_hpo_mix[] = {
538 SOC_DAPM_SINGLE("HPO MIX DAC1 Switch", RT5651_HPO_MIXER,
539 RT5651_M_DAC1_HM_SFT, 1, 1),
540 SOC_DAPM_SINGLE("HPO MIX HPVOL Switch", RT5651_HPO_MIXER,
541 RT5651_M_HPVOL_HM_SFT, 1, 1),
542 };
543
544 static const struct snd_kcontrol_new rt5651_lout_mix[] = {
545 SOC_DAPM_SINGLE("DAC L1 Switch", RT5651_LOUT_MIXER,
546 RT5651_M_DAC_L1_LM_SFT, 1, 1),
547 SOC_DAPM_SINGLE("DAC R1 Switch", RT5651_LOUT_MIXER,
548 RT5651_M_DAC_R1_LM_SFT, 1, 1),
549 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5651_LOUT_MIXER,
550 RT5651_M_OV_L_LM_SFT, 1, 1),
551 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5651_LOUT_MIXER,
552 RT5651_M_OV_R_LM_SFT, 1, 1),
553 };
554
555 static const struct snd_kcontrol_new outvol_l_control =
556 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
557 RT5651_VOL_L_SFT, 1, 1);
558
559 static const struct snd_kcontrol_new outvol_r_control =
560 SOC_DAPM_SINGLE("Switch", RT5651_LOUT_CTRL1,
561 RT5651_VOL_R_SFT, 1, 1);
562
563 static const struct snd_kcontrol_new lout_l_mute_control =
564 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
565 RT5651_L_MUTE_SFT, 1, 1);
566
567 static const struct snd_kcontrol_new lout_r_mute_control =
568 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_LOUT_CTRL1,
569 RT5651_R_MUTE_SFT, 1, 1);
570
571 static const struct snd_kcontrol_new hpovol_l_control =
572 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
573 RT5651_VOL_L_SFT, 1, 1);
574
575 static const struct snd_kcontrol_new hpovol_r_control =
576 SOC_DAPM_SINGLE("Switch", RT5651_HP_VOL,
577 RT5651_VOL_R_SFT, 1, 1);
578
579 static const struct snd_kcontrol_new hpo_l_mute_control =
580 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
581 RT5651_L_MUTE_SFT, 1, 1);
582
583 static const struct snd_kcontrol_new hpo_r_mute_control =
584 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5651_HP_VOL,
585 RT5651_R_MUTE_SFT, 1, 1);
586
587 /* INL/R source */
588 static const char * const rt5651_inl_src[] = {"IN2P", "HPOVOLLP"};
589
590 static SOC_ENUM_SINGLE_DECL(
591 rt5651_inl_enum, RT5651_INL1_INR1_VOL,
592 RT5651_INL_SEL_SFT, rt5651_inl_src);
593
594 static const struct snd_kcontrol_new rt5651_inl1_mux =
595 SOC_DAPM_ENUM("INL1 source", rt5651_inl_enum);
596
597 static const char * const rt5651_inr1_src[] = {"IN2N", "HPOVOLRP"};
598
599 static SOC_ENUM_SINGLE_DECL(
600 rt5651_inr1_enum, RT5651_INL1_INR1_VOL,
601 RT5651_INR_SEL_SFT, rt5651_inr1_src);
602
603 static const struct snd_kcontrol_new rt5651_inr1_mux =
604 SOC_DAPM_ENUM("INR1 source", rt5651_inr1_enum);
605
606 static const char * const rt5651_inl2_src[] = {"IN3P", "OUTVOLLP"};
607
608 static SOC_ENUM_SINGLE_DECL(
609 rt5651_inl2_enum, RT5651_INL2_INR2_VOL,
610 RT5651_INL_SEL_SFT, rt5651_inl2_src);
611
612 static const struct snd_kcontrol_new rt5651_inl2_mux =
613 SOC_DAPM_ENUM("INL2 source", rt5651_inl2_enum);
614
615 static const char * const rt5651_inr2_src[] = {"IN3N", "OUTVOLRP"};
616
617 static SOC_ENUM_SINGLE_DECL(
618 rt5651_inr2_enum, RT5651_INL2_INR2_VOL,
619 RT5651_INR_SEL_SFT, rt5651_inr2_src);
620
621 static const struct snd_kcontrol_new rt5651_inr2_mux =
622 SOC_DAPM_ENUM("INR2 source", rt5651_inr2_enum);
623
624
625 /* Stereo ADC source */
626 static const char * const rt5651_stereo1_adc1_src[] = {"DD MIX", "ADC"};
627
628 static SOC_ENUM_SINGLE_DECL(
629 rt5651_stereo1_adc1_enum, RT5651_STO1_ADC_MIXER,
630 RT5651_STO1_ADC_1_SRC_SFT, rt5651_stereo1_adc1_src);
631
632 static const struct snd_kcontrol_new rt5651_sto1_adc_l1_mux =
633 SOC_DAPM_ENUM("Stereo1 ADC L1 source", rt5651_stereo1_adc1_enum);
634
635 static const struct snd_kcontrol_new rt5651_sto1_adc_r1_mux =
636 SOC_DAPM_ENUM("Stereo1 ADC R1 source", rt5651_stereo1_adc1_enum);
637
638 static const char * const rt5651_stereo1_adc2_src[] = {"DMIC", "DD MIX"};
639
640 static SOC_ENUM_SINGLE_DECL(
641 rt5651_stereo1_adc2_enum, RT5651_STO1_ADC_MIXER,
642 RT5651_STO1_ADC_2_SRC_SFT, rt5651_stereo1_adc2_src);
643
644 static const struct snd_kcontrol_new rt5651_sto1_adc_l2_mux =
645 SOC_DAPM_ENUM("Stereo1 ADC L2 source", rt5651_stereo1_adc2_enum);
646
647 static const struct snd_kcontrol_new rt5651_sto1_adc_r2_mux =
648 SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum);
649
650 /* Mono ADC source */
651 static const char * const rt5651_sto2_adc_l1_src[] = {"DD MIXL", "ADCL"};
652
653 static SOC_ENUM_SINGLE_DECL(
654 rt5651_sto2_adc_l1_enum, RT5651_STO1_ADC_MIXER,
655 RT5651_STO2_ADC_L1_SRC_SFT, rt5651_sto2_adc_l1_src);
656
657 static const struct snd_kcontrol_new rt5651_sto2_adc_l1_mux =
658 SOC_DAPM_ENUM("Stereo2 ADC1 left source", rt5651_sto2_adc_l1_enum);
659
660 static const char * const rt5651_sto2_adc_l2_src[] = {"DMIC L", "DD MIXL"};
661
662 static SOC_ENUM_SINGLE_DECL(
663 rt5651_sto2_adc_l2_enum, RT5651_STO1_ADC_MIXER,
664 RT5651_STO2_ADC_L2_SRC_SFT, rt5651_sto2_adc_l2_src);
665
666 static const struct snd_kcontrol_new rt5651_sto2_adc_l2_mux =
667 SOC_DAPM_ENUM("Stereo2 ADC2 left source", rt5651_sto2_adc_l2_enum);
668
669 static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"};
670
671 static SOC_ENUM_SINGLE_DECL(
672 rt5651_sto2_adc_r1_enum, RT5651_STO1_ADC_MIXER,
673 RT5651_STO2_ADC_R1_SRC_SFT, rt5651_sto2_adc_r1_src);
674
675 static const struct snd_kcontrol_new rt5651_sto2_adc_r1_mux =
676 SOC_DAPM_ENUM("Stereo2 ADC1 right source", rt5651_sto2_adc_r1_enum);
677
678 static const char * const rt5651_sto2_adc_r2_src[] = {"DMIC R", "DD MIXR"};
679
680 static SOC_ENUM_SINGLE_DECL(
681 rt5651_sto2_adc_r2_enum, RT5651_STO1_ADC_MIXER,
682 RT5651_STO2_ADC_R2_SRC_SFT, rt5651_sto2_adc_r2_src);
683
684 static const struct snd_kcontrol_new rt5651_sto2_adc_r2_mux =
685 SOC_DAPM_ENUM("Stereo2 ADC2 right source", rt5651_sto2_adc_r2_enum);
686
687 /* DAC2 channel source */
688
689 static const char * const rt5651_dac_src[] = {"IF1", "IF2"};
690
691 static SOC_ENUM_SINGLE_DECL(rt5651_dac_l2_enum, RT5651_DAC2_CTRL,
692 RT5651_SEL_DAC_L2_SFT, rt5651_dac_src);
693
694 static const struct snd_kcontrol_new rt5651_dac_l2_mux =
695 SOC_DAPM_ENUM("DAC2 left channel source", rt5651_dac_l2_enum);
696
697 static SOC_ENUM_SINGLE_DECL(
698 rt5651_dac_r2_enum, RT5651_DAC2_CTRL,
699 RT5651_SEL_DAC_R2_SFT, rt5651_dac_src);
700
701 static const struct snd_kcontrol_new rt5651_dac_r2_mux =
702 SOC_DAPM_ENUM("DAC2 right channel source", rt5651_dac_r2_enum);
703
704 /* IF2_ADC channel source */
705
706 static const char * const rt5651_adc_src[] = {"IF1 ADC1", "IF1 ADC2"};
707
708 static SOC_ENUM_SINGLE_DECL(rt5651_if2_adc_src_enum, RT5651_DIG_INF_DATA,
709 RT5651_IF2_ADC_SRC_SFT, rt5651_adc_src);
710
711 static const struct snd_kcontrol_new rt5651_if2_adc_src_mux =
712 SOC_DAPM_ENUM("IF2 ADC channel source", rt5651_if2_adc_src_enum);
713
714 /* PDM select */
715 static const char * const rt5651_pdm_sel[] = {"DD MIX", "Stereo DAC MIX"};
716
717 static SOC_ENUM_SINGLE_DECL(
718 rt5651_pdm_l_sel_enum, RT5651_PDM_CTL,
719 RT5651_PDM_L_SEL_SFT, rt5651_pdm_sel);
720
721 static SOC_ENUM_SINGLE_DECL(
722 rt5651_pdm_r_sel_enum, RT5651_PDM_CTL,
723 RT5651_PDM_R_SEL_SFT, rt5651_pdm_sel);
724
725 static const struct snd_kcontrol_new rt5651_pdm_l_mux =
726 SOC_DAPM_ENUM("PDM L select", rt5651_pdm_l_sel_enum);
727
728 static const struct snd_kcontrol_new rt5651_pdm_r_mux =
729 SOC_DAPM_ENUM("PDM R select", rt5651_pdm_r_sel_enum);
730
731 static int rt5651_amp_power_event(struct snd_soc_dapm_widget *w,
732 struct snd_kcontrol *kcontrol, int event)
733 {
734 struct snd_soc_codec *codec = w->codec;
735 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
736
737 switch (event) {
738 case SND_SOC_DAPM_POST_PMU:
739 /* depop parameters */
740 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
741 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0200);
742 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
743 RT5651_DEPOP_MASK, RT5651_DEPOP_MAN);
744 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
745 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK |
746 RT5651_HP_CB_MASK, RT5651_HP_CP_PU |
747 RT5651_HP_SG_DIS | RT5651_HP_CB_PU);
748 regmap_write(rt5651->regmap, RT5651_PR_BASE +
749 RT5651_HP_DCC_INT1, 0x9f00);
750 /* headphone amp power on */
751 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
752 RT5651_PWR_FV1 | RT5651_PWR_FV2, 0);
753 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
754 RT5651_PWR_HA,
755 RT5651_PWR_HA);
756 usleep_range(10000, 15000);
757 regmap_update_bits(rt5651->regmap, RT5651_PWR_ANLG1,
758 RT5651_PWR_FV1 | RT5651_PWR_FV2 ,
759 RT5651_PWR_FV1 | RT5651_PWR_FV2);
760 break;
761
762 default:
763 return 0;
764 }
765
766 return 0;
767 }
768
769 static int rt5651_hp_event(struct snd_soc_dapm_widget *w,
770 struct snd_kcontrol *kcontrol, int event)
771 {
772 struct snd_soc_codec *codec = w->codec;
773 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
774
775 switch (event) {
776 case SND_SOC_DAPM_POST_PMU:
777 /* headphone unmute sequence */
778 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M2,
779 RT5651_DEPOP_MASK | RT5651_DIG_DP_MASK,
780 RT5651_DEPOP_AUTO | RT5651_DIG_DP_EN);
781 regmap_update_bits(rt5651->regmap, RT5651_CHARGE_PUMP,
782 RT5651_PM_HP_MASK, RT5651_PM_HP_HV);
783
784 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M3,
785 RT5651_CP_FQ1_MASK | RT5651_CP_FQ2_MASK |
786 RT5651_CP_FQ3_MASK,
787 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ1_SFT) |
788 (RT5651_CP_FQ_12_KHZ << RT5651_CP_FQ2_SFT) |
789 (RT5651_CP_FQ_192_KHZ << RT5651_CP_FQ3_SFT));
790
791 regmap_write(rt5651->regmap, RT5651_PR_BASE +
792 RT5651_MAMP_INT_REG2, 0x1c00);
793 regmap_update_bits(rt5651->regmap, RT5651_DEPOP_M1,
794 RT5651_HP_CP_MASK | RT5651_HP_SG_MASK,
795 RT5651_HP_CP_PD | RT5651_HP_SG_EN);
796 regmap_update_bits(rt5651->regmap, RT5651_PR_BASE +
797 RT5651_CHPUMP_INT_REG1, 0x0700, 0x0400);
798 rt5651->hp_mute = 0;
799 break;
800
801 case SND_SOC_DAPM_PRE_PMD:
802 rt5651->hp_mute = 1;
803 usleep_range(70000, 75000);
804 break;
805
806 default:
807 return 0;
808 }
809
810 return 0;
811 }
812
813 static int rt5651_hp_post_event(struct snd_soc_dapm_widget *w,
814 struct snd_kcontrol *kcontrol, int event)
815 {
816 struct snd_soc_codec *codec = w->codec;
817 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
818
819 switch (event) {
820 case SND_SOC_DAPM_POST_PMU:
821 if (!rt5651->hp_mute)
822 usleep_range(80000, 85000);
823
824 break;
825
826 default:
827 return 0;
828 }
829
830 return 0;
831 }
832
833 static int rt5651_bst1_event(struct snd_soc_dapm_widget *w,
834 struct snd_kcontrol *kcontrol, int event)
835 {
836 struct snd_soc_codec *codec = w->codec;
837
838 switch (event) {
839 case SND_SOC_DAPM_POST_PMU:
840 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
841 RT5651_PWR_BST1_OP2, RT5651_PWR_BST1_OP2);
842 break;
843
844 case SND_SOC_DAPM_PRE_PMD:
845 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
846 RT5651_PWR_BST1_OP2, 0);
847 break;
848
849 default:
850 return 0;
851 }
852
853 return 0;
854 }
855
856 static int rt5651_bst2_event(struct snd_soc_dapm_widget *w,
857 struct snd_kcontrol *kcontrol, int event)
858 {
859 struct snd_soc_codec *codec = w->codec;
860
861 switch (event) {
862 case SND_SOC_DAPM_POST_PMU:
863 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
864 RT5651_PWR_BST2_OP2, RT5651_PWR_BST2_OP2);
865 break;
866
867 case SND_SOC_DAPM_PRE_PMD:
868 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
869 RT5651_PWR_BST2_OP2, 0);
870 break;
871
872 default:
873 return 0;
874 }
875
876 return 0;
877 }
878
879 static int rt5651_bst3_event(struct snd_soc_dapm_widget *w,
880 struct snd_kcontrol *kcontrol, int event)
881 {
882 struct snd_soc_codec *codec = w->codec;
883
884 switch (event) {
885 case SND_SOC_DAPM_POST_PMU:
886 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
887 RT5651_PWR_BST3_OP2, RT5651_PWR_BST3_OP2);
888 break;
889
890 case SND_SOC_DAPM_PRE_PMD:
891 snd_soc_update_bits(codec, RT5651_PWR_ANLG2,
892 RT5651_PWR_BST3_OP2, 0);
893 break;
894
895 default:
896 return 0;
897 }
898
899 return 0;
900 }
901
902 static const struct snd_soc_dapm_widget rt5651_dapm_widgets[] = {
903 /* ASRC */
904 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5651_PLL_MODE_2,
905 15, 0, NULL, 0),
906 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5651_PLL_MODE_2,
907 14, 0, NULL, 0),
908 SND_SOC_DAPM_SUPPLY_S("STO1 DAC ASRC", 1, RT5651_PLL_MODE_2,
909 13, 0, NULL, 0),
910 SND_SOC_DAPM_SUPPLY_S("STO2 DAC ASRC", 1, RT5651_PLL_MODE_2,
911 12, 0, NULL, 0),
912 SND_SOC_DAPM_SUPPLY_S("ADC ASRC", 1, RT5651_PLL_MODE_2,
913 11, 0, NULL, 0),
914
915 SND_SOC_DAPM_SUPPLY("PLL1", RT5651_PWR_ANLG2,
916 RT5651_PWR_PLL_BIT, 0, NULL, 0),
917 /* Input Side */
918 /* micbias */
919 SND_SOC_DAPM_SUPPLY("LDO", RT5651_PWR_ANLG1,
920 RT5651_PWR_LDO_BIT, 0, NULL, 0),
921 SND_SOC_DAPM_MICBIAS("micbias1", RT5651_PWR_ANLG2,
922 RT5651_PWR_MB1_BIT, 0),
923 /* Input Lines */
924 SND_SOC_DAPM_INPUT("MIC1"),
925 SND_SOC_DAPM_INPUT("MIC2"),
926 SND_SOC_DAPM_INPUT("MIC3"),
927
928 SND_SOC_DAPM_INPUT("IN1P"),
929 SND_SOC_DAPM_INPUT("IN2P"),
930 SND_SOC_DAPM_INPUT("IN2N"),
931 SND_SOC_DAPM_INPUT("IN3P"),
932 SND_SOC_DAPM_INPUT("DMIC L1"),
933 SND_SOC_DAPM_INPUT("DMIC R1"),
934 SND_SOC_DAPM_SUPPLY("DMIC CLK", RT5651_DMIC, RT5651_DMIC_1_EN_SFT,
935 0, set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
936 /* Boost */
937 SND_SOC_DAPM_PGA_E("BST1", RT5651_PWR_ANLG2,
938 RT5651_PWR_BST1_BIT, 0, NULL, 0, rt5651_bst1_event,
939 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
940 SND_SOC_DAPM_PGA_E("BST2", RT5651_PWR_ANLG2,
941 RT5651_PWR_BST2_BIT, 0, NULL, 0, rt5651_bst2_event,
942 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
943 SND_SOC_DAPM_PGA_E("BST3", RT5651_PWR_ANLG2,
944 RT5651_PWR_BST3_BIT, 0, NULL, 0, rt5651_bst3_event,
945 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
946 /* Input Volume */
947 SND_SOC_DAPM_PGA("INL1 VOL", RT5651_PWR_VOL,
948 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
949 SND_SOC_DAPM_PGA("INR1 VOL", RT5651_PWR_VOL,
950 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
951 SND_SOC_DAPM_PGA("INL2 VOL", RT5651_PWR_VOL,
952 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
953 SND_SOC_DAPM_PGA("INR2 VOL", RT5651_PWR_VOL,
954 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
955 /* IN Mux */
956 SND_SOC_DAPM_MUX("INL1 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inl1_mux),
957 SND_SOC_DAPM_MUX("INR1 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inr1_mux),
958 SND_SOC_DAPM_MUX("INL2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inl2_mux),
959 SND_SOC_DAPM_MUX("INR2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_inr2_mux),
960 /* REC Mixer */
961 SND_SOC_DAPM_MIXER("RECMIXL", RT5651_PWR_MIXER, RT5651_PWR_RM_L_BIT, 0,
962 rt5651_rec_l_mix, ARRAY_SIZE(rt5651_rec_l_mix)),
963 SND_SOC_DAPM_MIXER("RECMIXR", RT5651_PWR_MIXER, RT5651_PWR_RM_R_BIT, 0,
964 rt5651_rec_r_mix, ARRAY_SIZE(rt5651_rec_r_mix)),
965 /* ADCs */
966 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
967 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
968 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5651_PWR_DIG1,
969 RT5651_PWR_ADC_L_BIT, 0, NULL, 0),
970 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5651_PWR_DIG1,
971 RT5651_PWR_ADC_R_BIT, 0, NULL, 0),
972 /* ADC Mux */
973 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
974 &rt5651_sto1_adc_l2_mux),
975 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
976 &rt5651_sto1_adc_r2_mux),
977 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
978 &rt5651_sto1_adc_l1_mux),
979 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
980 &rt5651_sto1_adc_r1_mux),
981 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
982 &rt5651_sto2_adc_l2_mux),
983 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
984 &rt5651_sto2_adc_l1_mux),
985 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
986 &rt5651_sto2_adc_r1_mux),
987 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
988 &rt5651_sto2_adc_r2_mux),
989 /* ADC Mixer */
990 SND_SOC_DAPM_SUPPLY("Stereo1 Filter", RT5651_PWR_DIG2,
991 RT5651_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
992 SND_SOC_DAPM_SUPPLY("Stereo2 Filter", RT5651_PWR_DIG2,
993 RT5651_PWR_ADC_STO2_F_BIT, 0, NULL, 0),
994 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
995 rt5651_sto1_adc_l_mix,
996 ARRAY_SIZE(rt5651_sto1_adc_l_mix)),
997 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
998 rt5651_sto1_adc_r_mix,
999 ARRAY_SIZE(rt5651_sto1_adc_r_mix)),
1000 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1001 rt5651_sto2_adc_l_mix,
1002 ARRAY_SIZE(rt5651_sto2_adc_l_mix)),
1003 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1004 rt5651_sto2_adc_r_mix,
1005 ARRAY_SIZE(rt5651_sto2_adc_r_mix)),
1006
1007 /* Digital Interface */
1008 SND_SOC_DAPM_SUPPLY("I2S1", RT5651_PWR_DIG1,
1009 RT5651_PWR_I2S1_BIT, 0, NULL, 0),
1010 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1011 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1012 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1013 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1014 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1015 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1016 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1017 SND_SOC_DAPM_SUPPLY("I2S2", RT5651_PWR_DIG1,
1018 RT5651_PWR_I2S2_BIT, 0, NULL, 0),
1019 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1020 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1021 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1022 SND_SOC_DAPM_MUX("IF2 ADC", SND_SOC_NOPM, 0, 0,
1023 &rt5651_if2_adc_src_mux),
1024
1025 /* Digital Interface Select */
1026
1027 SND_SOC_DAPM_MUX("PDM L Mux", RT5651_PDM_CTL,
1028 RT5651_M_PDM_L_SFT, 1, &rt5651_pdm_l_mux),
1029 SND_SOC_DAPM_MUX("PDM R Mux", RT5651_PDM_CTL,
1030 RT5651_M_PDM_R_SFT, 1, &rt5651_pdm_r_mux),
1031 /* Audio Interface */
1032 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1033 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1034 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1035 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1036
1037 /* Audio DSP */
1038 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
1039
1040 /* Output Side */
1041 /* DAC mixer before sound effect */
1042 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1043 rt5651_dac_l_mix, ARRAY_SIZE(rt5651_dac_l_mix)),
1044 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1045 rt5651_dac_r_mix, ARRAY_SIZE(rt5651_dac_r_mix)),
1046
1047 /* DAC2 channel Mux */
1048 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_l2_mux),
1049 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux),
1050 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1051 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1052
1053 SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5651_PWR_DIG2,
1054 RT5651_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
1055 SND_SOC_DAPM_SUPPLY("Stero2 DAC Power", RT5651_PWR_DIG2,
1056 RT5651_PWR_DAC_STO2_F_BIT, 0, NULL, 0),
1057 /* DAC Mixer */
1058 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1059 rt5651_sto_dac_l_mix,
1060 ARRAY_SIZE(rt5651_sto_dac_l_mix)),
1061 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1062 rt5651_sto_dac_r_mix,
1063 ARRAY_SIZE(rt5651_sto_dac_r_mix)),
1064 SND_SOC_DAPM_MIXER("DD MIXL", SND_SOC_NOPM, 0, 0,
1065 rt5651_dd_dac_l_mix,
1066 ARRAY_SIZE(rt5651_dd_dac_l_mix)),
1067 SND_SOC_DAPM_MIXER("DD MIXR", SND_SOC_NOPM, 0, 0,
1068 rt5651_dd_dac_r_mix,
1069 ARRAY_SIZE(rt5651_dd_dac_r_mix)),
1070
1071 /* DACs */
1072 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
1073 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
1074 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT5651_PWR_DIG1,
1075 RT5651_PWR_DAC_L1_BIT, 0, NULL, 0),
1076 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT5651_PWR_DIG1,
1077 RT5651_PWR_DAC_R1_BIT, 0, NULL, 0),
1078 /* OUT Mixer */
1079 SND_SOC_DAPM_MIXER("OUT MIXL", RT5651_PWR_MIXER, RT5651_PWR_OM_L_BIT,
1080 0, rt5651_out_l_mix, ARRAY_SIZE(rt5651_out_l_mix)),
1081 SND_SOC_DAPM_MIXER("OUT MIXR", RT5651_PWR_MIXER, RT5651_PWR_OM_R_BIT,
1082 0, rt5651_out_r_mix, ARRAY_SIZE(rt5651_out_r_mix)),
1083 /* Ouput Volume */
1084 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5651_PWR_VOL,
1085 RT5651_PWR_OV_L_BIT, 0, &outvol_l_control),
1086 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5651_PWR_VOL,
1087 RT5651_PWR_OV_R_BIT, 0, &outvol_r_control),
1088 SND_SOC_DAPM_SWITCH("HPOVOL L", RT5651_PWR_VOL,
1089 RT5651_PWR_HV_L_BIT, 0, &hpovol_l_control),
1090 SND_SOC_DAPM_SWITCH("HPOVOL R", RT5651_PWR_VOL,
1091 RT5651_PWR_HV_R_BIT, 0, &hpovol_r_control),
1092 SND_SOC_DAPM_PGA("INL1", RT5651_PWR_VOL,
1093 RT5651_PWR_IN1_L_BIT, 0, NULL, 0),
1094 SND_SOC_DAPM_PGA("INR1", RT5651_PWR_VOL,
1095 RT5651_PWR_IN1_R_BIT, 0, NULL, 0),
1096 SND_SOC_DAPM_PGA("INL2", RT5651_PWR_VOL,
1097 RT5651_PWR_IN2_L_BIT, 0, NULL, 0),
1098 SND_SOC_DAPM_PGA("INR2", RT5651_PWR_VOL,
1099 RT5651_PWR_IN2_R_BIT, 0, NULL, 0),
1100 /* HPO/LOUT/Mono Mixer */
1101 SND_SOC_DAPM_MIXER("HPOL MIX", SND_SOC_NOPM, 0, 0,
1102 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1103 SND_SOC_DAPM_MIXER("HPOR MIX", SND_SOC_NOPM, 0, 0,
1104 rt5651_hpo_mix, ARRAY_SIZE(rt5651_hpo_mix)),
1105 SND_SOC_DAPM_SUPPLY("HP L Amp", RT5651_PWR_ANLG1,
1106 RT5651_PWR_HP_L_BIT, 0, NULL, 0),
1107 SND_SOC_DAPM_SUPPLY("HP R Amp", RT5651_PWR_ANLG1,
1108 RT5651_PWR_HP_R_BIT, 0, NULL, 0),
1109 SND_SOC_DAPM_MIXER("LOUT MIX", RT5651_PWR_ANLG1, RT5651_PWR_LM_BIT, 0,
1110 rt5651_lout_mix, ARRAY_SIZE(rt5651_lout_mix)),
1111
1112 SND_SOC_DAPM_SUPPLY("Amp Power", RT5651_PWR_ANLG1,
1113 RT5651_PWR_HA_BIT, 0, rt5651_amp_power_event,
1114 SND_SOC_DAPM_POST_PMU),
1115 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5651_hp_event,
1116 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1117 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
1118 &hpo_l_mute_control),
1119 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
1120 &hpo_r_mute_control),
1121 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
1122 &lout_l_mute_control),
1123 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
1124 &lout_r_mute_control),
1125 SND_SOC_DAPM_POST("HP Post", rt5651_hp_post_event),
1126
1127 /* Output Lines */
1128 SND_SOC_DAPM_OUTPUT("HPOL"),
1129 SND_SOC_DAPM_OUTPUT("HPOR"),
1130 SND_SOC_DAPM_OUTPUT("LOUTL"),
1131 SND_SOC_DAPM_OUTPUT("LOUTR"),
1132 SND_SOC_DAPM_OUTPUT("PDML"),
1133 SND_SOC_DAPM_OUTPUT("PDMR"),
1134 };
1135
1136 static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
1137 {"Stero1 DAC Power", NULL, "STO1 DAC ASRC"},
1138 {"Stero2 DAC Power", NULL, "STO2 DAC ASRC"},
1139 {"I2S1", NULL, "I2S1 ASRC"},
1140 {"I2S2", NULL, "I2S2 ASRC"},
1141
1142 {"IN1P", NULL, "LDO"},
1143 {"IN2P", NULL, "LDO"},
1144 {"IN3P", NULL, "LDO"},
1145
1146 {"IN1P", NULL, "MIC1"},
1147 {"IN2P", NULL, "MIC2"},
1148 {"IN2N", NULL, "MIC2"},
1149 {"IN3P", NULL, "MIC3"},
1150
1151 {"BST1", NULL, "IN1P"},
1152 {"BST2", NULL, "IN2P"},
1153 {"BST2", NULL, "IN2N"},
1154 {"BST3", NULL, "IN3P"},
1155
1156 {"INL1 VOL", NULL, "IN2P"},
1157 {"INR1 VOL", NULL, "IN2N"},
1158
1159 {"RECMIXL", "INL1 Switch", "INL1 VOL"},
1160 {"RECMIXL", "BST3 Switch", "BST3"},
1161 {"RECMIXL", "BST2 Switch", "BST2"},
1162 {"RECMIXL", "BST1 Switch", "BST1"},
1163
1164 {"RECMIXR", "INR1 Switch", "INR1 VOL"},
1165 {"RECMIXR", "BST3 Switch", "BST3"},
1166 {"RECMIXR", "BST2 Switch", "BST2"},
1167 {"RECMIXR", "BST1 Switch", "BST1"},
1168
1169 {"ADC L", NULL, "RECMIXL"},
1170 {"ADC L", NULL, "ADC L Power"},
1171 {"ADC R", NULL, "RECMIXR"},
1172 {"ADC R", NULL, "ADC R Power"},
1173
1174 {"DMIC L1", NULL, "DMIC CLK"},
1175 {"DMIC R1", NULL, "DMIC CLK"},
1176
1177 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1178 {"Stereo1 ADC L2 Mux", "DD MIX", "DD MIXL"},
1179 {"Stereo1 ADC L1 Mux", "ADC", "ADC L"},
1180 {"Stereo1 ADC L1 Mux", "DD MIX", "DD MIXL"},
1181
1182 {"Stereo1 ADC R1 Mux", "ADC", "ADC R"},
1183 {"Stereo1 ADC R1 Mux", "DD MIX", "DD MIXR"},
1184 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1185 {"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"},
1186
1187 {"Stereo2 ADC L2 Mux", "DMIC L", "DMIC L1"},
1188 {"Stereo2 ADC L2 Mux", "DD MIXL", "DD MIXL"},
1189 {"Stereo2 ADC L1 Mux", "DD MIXL", "DD MIXL"},
1190 {"Stereo2 ADC L1 Mux", "ADCL", "ADC L"},
1191
1192 {"Stereo2 ADC R1 Mux", "DD MIXR", "DD MIXR"},
1193 {"Stereo2 ADC R1 Mux", "ADCR", "ADC R"},
1194 {"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"},
1195 {"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"},
1196
1197 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1198 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1199 {"Stereo1 ADC MIXL", NULL, "Stereo1 Filter"},
1200 {"Stereo1 Filter", NULL, "PLL1", is_sysclk_from_pll},
1201 {"Stereo1 Filter", NULL, "ADC ASRC"},
1202
1203 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1204 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1205 {"Stereo1 ADC MIXR", NULL, "Stereo1 Filter"},
1206
1207 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
1208 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
1209 {"Stereo2 ADC MIXL", NULL, "Stereo2 Filter"},
1210 {"Stereo2 Filter", NULL, "PLL1", is_sysclk_from_pll},
1211 {"Stereo2 Filter", NULL, "ADC ASRC"},
1212
1213 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
1214 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
1215 {"Stereo2 ADC MIXR", NULL, "Stereo2 Filter"},
1216
1217 {"IF1 ADC2", NULL, "Stereo2 ADC MIXL"},
1218 {"IF1 ADC2", NULL, "Stereo2 ADC MIXR"},
1219 {"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
1220 {"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
1221
1222 {"IF1 ADC1", NULL, "I2S1"},
1223
1224 {"IF2 ADC", "IF1 ADC1", "IF1 ADC1"},
1225 {"IF2 ADC", "IF1 ADC2", "IF1 ADC2"},
1226 {"IF2 ADC", NULL, "I2S2"},
1227
1228 {"AIF1TX", NULL, "IF1 ADC1"},
1229 {"AIF1TX", NULL, "IF1 ADC2"},
1230 {"AIF2TX", NULL, "IF2 ADC"},
1231
1232 {"IF1 DAC", NULL, "AIF1RX"},
1233 {"IF1 DAC", NULL, "I2S1"},
1234 {"IF2 DAC", NULL, "AIF2RX"},
1235 {"IF2 DAC", NULL, "I2S2"},
1236
1237 {"IF1 DAC1 L", NULL, "IF1 DAC"},
1238 {"IF1 DAC1 R", NULL, "IF1 DAC"},
1239 {"IF1 DAC2 L", NULL, "IF1 DAC"},
1240 {"IF1 DAC2 R", NULL, "IF1 DAC"},
1241 {"IF2 DAC L", NULL, "IF2 DAC"},
1242 {"IF2 DAC R", NULL, "IF2 DAC"},
1243
1244 {"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1245 {"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
1246 {"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1247 {"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
1248
1249 {"Audio DSP", NULL, "DAC MIXL"},
1250 {"Audio DSP", NULL, "DAC MIXR"},
1251
1252 {"DAC L2 Mux", "IF1", "IF1 DAC2 L"},
1253 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
1254 {"DAC L2 Volume", NULL, "DAC L2 Mux"},
1255
1256 {"DAC R2 Mux", "IF1", "IF1 DAC2 R"},
1257 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1258 {"DAC R2 Volume", NULL, "DAC R2 Mux"},
1259
1260 {"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
1261 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1262 {"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
1263 {"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
1264 {"Stereo DAC MIXL", NULL, "Stero2 DAC Power"},
1265 {"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
1266 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1267 {"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
1268 {"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
1269 {"Stereo DAC MIXR", NULL, "Stero2 DAC Power"},
1270
1271 {"PDM L Mux", "Stereo DAC MIX", "Stereo DAC MIXL"},
1272 {"PDM L Mux", "DD MIX", "DAC MIXL"},
1273 {"PDM R Mux", "Stereo DAC MIX", "Stereo DAC MIXR"},
1274 {"PDM R Mux", "DD MIX", "DAC MIXR"},
1275
1276 {"DAC L1", NULL, "Stereo DAC MIXL"},
1277 {"DAC L1", NULL, "PLL1", is_sysclk_from_pll},
1278 {"DAC L1", NULL, "DAC L1 Power"},
1279 {"DAC R1", NULL, "Stereo DAC MIXR"},
1280 {"DAC R1", NULL, "PLL1", is_sysclk_from_pll},
1281 {"DAC R1", NULL, "DAC R1 Power"},
1282
1283 {"DD MIXL", "DAC L1 Switch", "DAC MIXL"},
1284 {"DD MIXL", "DAC L2 Switch", "DAC L2 Volume"},
1285 {"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"},
1286 {"DD MIXL", NULL, "Stero2 DAC Power"},
1287
1288 {"DD MIXR", "DAC R1 Switch", "DAC MIXR"},
1289 {"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1290 {"DD MIXR", "DAC L2 Switch", "DAC L2 Volume"},
1291 {"DD MIXR", NULL, "Stero2 DAC Power"},
1292
1293 {"OUT MIXL", "BST1 Switch", "BST1"},
1294 {"OUT MIXL", "BST2 Switch", "BST2"},
1295 {"OUT MIXL", "INL1 Switch", "INL1 VOL"},
1296 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
1297 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
1298
1299 {"OUT MIXR", "BST2 Switch", "BST2"},
1300 {"OUT MIXR", "BST1 Switch", "BST1"},
1301 {"OUT MIXR", "INR1 Switch", "INR1 VOL"},
1302 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
1303 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
1304
1305 {"HPOVOL L", "Switch", "OUT MIXL"},
1306 {"HPOVOL R", "Switch", "OUT MIXR"},
1307 {"OUTVOL L", "Switch", "OUT MIXL"},
1308 {"OUTVOL R", "Switch", "OUT MIXR"},
1309
1310 {"HPOL MIX", "HPO MIX DAC1 Switch", "DAC L1"},
1311 {"HPOL MIX", "HPO MIX HPVOL Switch", "HPOVOL L"},
1312 {"HPOL MIX", NULL, "HP L Amp"},
1313 {"HPOR MIX", "HPO MIX DAC1 Switch", "DAC R1"},
1314 {"HPOR MIX", "HPO MIX HPVOL Switch", "HPOVOL R"},
1315 {"HPOR MIX", NULL, "HP R Amp"},
1316
1317 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
1318 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
1319 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
1320 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
1321
1322 {"HP Amp", NULL, "HPOL MIX"},
1323 {"HP Amp", NULL, "HPOR MIX"},
1324 {"HP Amp", NULL, "Amp Power"},
1325 {"HPO L Playback", "Switch", "HP Amp"},
1326 {"HPO R Playback", "Switch", "HP Amp"},
1327 {"HPOL", NULL, "HPO L Playback"},
1328 {"HPOR", NULL, "HPO R Playback"},
1329
1330 {"LOUT L Playback", "Switch", "LOUT MIX"},
1331 {"LOUT R Playback", "Switch", "LOUT MIX"},
1332 {"LOUTL", NULL, "LOUT L Playback"},
1333 {"LOUTL", NULL, "Amp Power"},
1334 {"LOUTR", NULL, "LOUT R Playback"},
1335 {"LOUTR", NULL, "Amp Power"},
1336
1337 {"PDML", NULL, "PDM L Mux"},
1338 {"PDMR", NULL, "PDM R Mux"},
1339 };
1340
1341 static int rt5651_hw_params(struct snd_pcm_substream *substream,
1342 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1343 {
1344 struct snd_soc_codec *codec = dai->codec;
1345 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1346 unsigned int val_len = 0, val_clk, mask_clk;
1347 int pre_div, bclk_ms, frame_size;
1348
1349 rt5651->lrck[dai->id] = params_rate(params);
1350 pre_div = rl6231_get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]);
1351
1352 if (pre_div < 0) {
1353 dev_err(codec->dev, "Unsupported clock setting\n");
1354 return -EINVAL;
1355 }
1356 frame_size = snd_soc_params_to_frame_size(params);
1357 if (frame_size < 0) {
1358 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
1359 return -EINVAL;
1360 }
1361 bclk_ms = frame_size > 32 ? 1 : 0;
1362 rt5651->bclk[dai->id] = rt5651->lrck[dai->id] * (32 << bclk_ms);
1363
1364 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1365 rt5651->bclk[dai->id], rt5651->lrck[dai->id]);
1366 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1367 bclk_ms, pre_div, dai->id);
1368
1369 switch (params_format(params)) {
1370 case SNDRV_PCM_FORMAT_S16_LE:
1371 break;
1372 case SNDRV_PCM_FORMAT_S20_3LE:
1373 val_len |= RT5651_I2S_DL_20;
1374 break;
1375 case SNDRV_PCM_FORMAT_S24_LE:
1376 val_len |= RT5651_I2S_DL_24;
1377 break;
1378 case SNDRV_PCM_FORMAT_S8:
1379 val_len |= RT5651_I2S_DL_8;
1380 break;
1381 default:
1382 return -EINVAL;
1383 }
1384
1385 switch (dai->id) {
1386 case RT5651_AIF1:
1387 mask_clk = RT5651_I2S_PD1_MASK;
1388 val_clk = pre_div << RT5651_I2S_PD1_SFT;
1389 snd_soc_update_bits(codec, RT5651_I2S1_SDP,
1390 RT5651_I2S_DL_MASK, val_len);
1391 snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk);
1392 break;
1393 case RT5651_AIF2:
1394 mask_clk = RT5651_I2S_BCLK_MS2_MASK | RT5651_I2S_PD2_MASK;
1395 val_clk = pre_div << RT5651_I2S_PD2_SFT;
1396 snd_soc_update_bits(codec, RT5651_I2S2_SDP,
1397 RT5651_I2S_DL_MASK, val_len);
1398 snd_soc_update_bits(codec, RT5651_ADDA_CLK1, mask_clk, val_clk);
1399 break;
1400 default:
1401 dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id);
1402 return -EINVAL;
1403 }
1404
1405 return 0;
1406 }
1407
1408 static int rt5651_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1409 {
1410 struct snd_soc_codec *codec = dai->codec;
1411 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1412 unsigned int reg_val = 0;
1413
1414 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1415 case SND_SOC_DAIFMT_CBM_CFM:
1416 rt5651->master[dai->id] = 1;
1417 break;
1418 case SND_SOC_DAIFMT_CBS_CFS:
1419 reg_val |= RT5651_I2S_MS_S;
1420 rt5651->master[dai->id] = 0;
1421 break;
1422 default:
1423 return -EINVAL;
1424 }
1425
1426 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1427 case SND_SOC_DAIFMT_NB_NF:
1428 break;
1429 case SND_SOC_DAIFMT_IB_NF:
1430 reg_val |= RT5651_I2S_BP_INV;
1431 break;
1432 default:
1433 return -EINVAL;
1434 }
1435
1436 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1437 case SND_SOC_DAIFMT_I2S:
1438 break;
1439 case SND_SOC_DAIFMT_LEFT_J:
1440 reg_val |= RT5651_I2S_DF_LEFT;
1441 break;
1442 case SND_SOC_DAIFMT_DSP_A:
1443 reg_val |= RT5651_I2S_DF_PCM_A;
1444 break;
1445 case SND_SOC_DAIFMT_DSP_B:
1446 reg_val |= RT5651_I2S_DF_PCM_B;
1447 break;
1448 default:
1449 return -EINVAL;
1450 }
1451
1452 switch (dai->id) {
1453 case RT5651_AIF1:
1454 snd_soc_update_bits(codec, RT5651_I2S1_SDP,
1455 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1456 RT5651_I2S_DF_MASK, reg_val);
1457 break;
1458 case RT5651_AIF2:
1459 snd_soc_update_bits(codec, RT5651_I2S2_SDP,
1460 RT5651_I2S_MS_MASK | RT5651_I2S_BP_MASK |
1461 RT5651_I2S_DF_MASK, reg_val);
1462 break;
1463 default:
1464 dev_err(codec->dev, "Wrong dai->id: %d\n", dai->id);
1465 return -EINVAL;
1466 }
1467 return 0;
1468 }
1469
1470 static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
1471 int clk_id, unsigned int freq, int dir)
1472 {
1473 struct snd_soc_codec *codec = dai->codec;
1474 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1475 unsigned int reg_val = 0;
1476
1477 if (freq == rt5651->sysclk && clk_id == rt5651->sysclk_src)
1478 return 0;
1479
1480 switch (clk_id) {
1481 case RT5651_SCLK_S_MCLK:
1482 reg_val |= RT5651_SCLK_SRC_MCLK;
1483 break;
1484 case RT5651_SCLK_S_PLL1:
1485 reg_val |= RT5651_SCLK_SRC_PLL1;
1486 break;
1487 case RT5651_SCLK_S_RCCLK:
1488 reg_val |= RT5651_SCLK_SRC_RCCLK;
1489 break;
1490 default:
1491 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
1492 return -EINVAL;
1493 }
1494 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1495 RT5651_SCLK_SRC_MASK, reg_val);
1496 rt5651->sysclk = freq;
1497 rt5651->sysclk_src = clk_id;
1498
1499 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1500
1501 return 0;
1502 }
1503
1504 static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1505 unsigned int freq_in, unsigned int freq_out)
1506 {
1507 struct snd_soc_codec *codec = dai->codec;
1508 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1509 struct rl6231_pll_code pll_code;
1510 int ret;
1511
1512 if (source == rt5651->pll_src && freq_in == rt5651->pll_in &&
1513 freq_out == rt5651->pll_out)
1514 return 0;
1515
1516 if (!freq_in || !freq_out) {
1517 dev_dbg(codec->dev, "PLL disabled\n");
1518
1519 rt5651->pll_in = 0;
1520 rt5651->pll_out = 0;
1521 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1522 RT5651_SCLK_SRC_MASK, RT5651_SCLK_SRC_MCLK);
1523 return 0;
1524 }
1525
1526 switch (source) {
1527 case RT5651_PLL1_S_MCLK:
1528 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1529 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_MCLK);
1530 break;
1531 case RT5651_PLL1_S_BCLK1:
1532 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1533 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK1);
1534 break;
1535 case RT5651_PLL1_S_BCLK2:
1536 snd_soc_update_bits(codec, RT5651_GLB_CLK,
1537 RT5651_PLL1_SRC_MASK, RT5651_PLL1_SRC_BCLK2);
1538 break;
1539 default:
1540 dev_err(codec->dev, "Unknown PLL source %d\n", source);
1541 return -EINVAL;
1542 }
1543
1544 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1545 if (ret < 0) {
1546 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
1547 return ret;
1548 }
1549
1550 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
1551 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1552 pll_code.n_code, pll_code.k_code);
1553
1554 snd_soc_write(codec, RT5651_PLL_CTRL1,
1555 pll_code.n_code << RT5651_PLL_N_SFT | pll_code.k_code);
1556 snd_soc_write(codec, RT5651_PLL_CTRL2,
1557 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5651_PLL_M_SFT |
1558 pll_code.m_bp << RT5651_PLL_M_BP_SFT);
1559
1560 rt5651->pll_in = freq_in;
1561 rt5651->pll_out = freq_out;
1562 rt5651->pll_src = source;
1563
1564 return 0;
1565 }
1566
1567 static int rt5651_set_bias_level(struct snd_soc_codec *codec,
1568 enum snd_soc_bias_level level)
1569 {
1570 switch (level) {
1571 case SND_SOC_BIAS_PREPARE:
1572 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
1573 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1574 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1575 RT5651_PWR_BG | RT5651_PWR_VREF2,
1576 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1577 RT5651_PWR_BG | RT5651_PWR_VREF2);
1578 usleep_range(10000, 15000);
1579 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1580 RT5651_PWR_FV1 | RT5651_PWR_FV2,
1581 RT5651_PWR_FV1 | RT5651_PWR_FV2);
1582 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1583 RT5651_PWR_LDO_DVO_MASK,
1584 RT5651_PWR_LDO_DVO_1_2V);
1585 snd_soc_update_bits(codec, RT5651_D_MISC, 0x1, 0x1);
1586 if (snd_soc_read(codec, RT5651_PLL_MODE_1) & 0x9200)
1587 snd_soc_update_bits(codec, RT5651_D_MISC,
1588 0xc00, 0xc00);
1589 }
1590 break;
1591
1592 case SND_SOC_BIAS_STANDBY:
1593 snd_soc_write(codec, RT5651_D_MISC, 0x0010);
1594 snd_soc_write(codec, RT5651_PWR_DIG1, 0x0000);
1595 snd_soc_write(codec, RT5651_PWR_DIG2, 0x0000);
1596 snd_soc_write(codec, RT5651_PWR_VOL, 0x0000);
1597 snd_soc_write(codec, RT5651_PWR_MIXER, 0x0000);
1598 snd_soc_write(codec, RT5651_PWR_ANLG1, 0x0000);
1599 snd_soc_write(codec, RT5651_PWR_ANLG2, 0x0000);
1600 break;
1601
1602 default:
1603 break;
1604 }
1605 codec->dapm.bias_level = level;
1606
1607 return 0;
1608 }
1609
1610 static int rt5651_probe(struct snd_soc_codec *codec)
1611 {
1612 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1613
1614 rt5651->codec = codec;
1615
1616 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1617 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1618 RT5651_PWR_BG | RT5651_PWR_VREF2,
1619 RT5651_PWR_VREF1 | RT5651_PWR_MB |
1620 RT5651_PWR_BG | RT5651_PWR_VREF2);
1621 usleep_range(10000, 15000);
1622 snd_soc_update_bits(codec, RT5651_PWR_ANLG1,
1623 RT5651_PWR_FV1 | RT5651_PWR_FV2,
1624 RT5651_PWR_FV1 | RT5651_PWR_FV2);
1625
1626 rt5651_set_bias_level(codec, SND_SOC_BIAS_OFF);
1627
1628 return 0;
1629 }
1630
1631 #ifdef CONFIG_PM
1632 static int rt5651_suspend(struct snd_soc_codec *codec)
1633 {
1634 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1635
1636 regcache_cache_only(rt5651->regmap, true);
1637 regcache_mark_dirty(rt5651->regmap);
1638 return 0;
1639 }
1640
1641 static int rt5651_resume(struct snd_soc_codec *codec)
1642 {
1643 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1644
1645 regcache_cache_only(rt5651->regmap, false);
1646 snd_soc_cache_sync(codec);
1647
1648 return 0;
1649 }
1650 #else
1651 #define rt5651_suspend NULL
1652 #define rt5651_resume NULL
1653 #endif
1654
1655 #define RT5651_STEREO_RATES SNDRV_PCM_RATE_8000_96000
1656 #define RT5651_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1657 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1658
1659 static const struct snd_soc_dai_ops rt5651_aif_dai_ops = {
1660 .hw_params = rt5651_hw_params,
1661 .set_fmt = rt5651_set_dai_fmt,
1662 .set_sysclk = rt5651_set_dai_sysclk,
1663 .set_pll = rt5651_set_dai_pll,
1664 };
1665
1666 static struct snd_soc_dai_driver rt5651_dai[] = {
1667 {
1668 .name = "rt5651-aif1",
1669 .id = RT5651_AIF1,
1670 .playback = {
1671 .stream_name = "AIF1 Playback",
1672 .channels_min = 1,
1673 .channels_max = 2,
1674 .rates = RT5651_STEREO_RATES,
1675 .formats = RT5651_FORMATS,
1676 },
1677 .capture = {
1678 .stream_name = "AIF1 Capture",
1679 .channels_min = 1,
1680 .channels_max = 2,
1681 .rates = RT5651_STEREO_RATES,
1682 .formats = RT5651_FORMATS,
1683 },
1684 .ops = &rt5651_aif_dai_ops,
1685 },
1686 {
1687 .name = "rt5651-aif2",
1688 .id = RT5651_AIF2,
1689 .playback = {
1690 .stream_name = "AIF2 Playback",
1691 .channels_min = 1,
1692 .channels_max = 2,
1693 .rates = RT5651_STEREO_RATES,
1694 .formats = RT5651_FORMATS,
1695 },
1696 .capture = {
1697 .stream_name = "AIF2 Capture",
1698 .channels_min = 1,
1699 .channels_max = 2,
1700 .rates = RT5651_STEREO_RATES,
1701 .formats = RT5651_FORMATS,
1702 },
1703 .ops = &rt5651_aif_dai_ops,
1704 },
1705 };
1706
1707 static struct snd_soc_codec_driver soc_codec_dev_rt5651 = {
1708 .probe = rt5651_probe,
1709 .suspend = rt5651_suspend,
1710 .resume = rt5651_resume,
1711 .set_bias_level = rt5651_set_bias_level,
1712 .idle_bias_off = true,
1713 .controls = rt5651_snd_controls,
1714 .num_controls = ARRAY_SIZE(rt5651_snd_controls),
1715 .dapm_widgets = rt5651_dapm_widgets,
1716 .num_dapm_widgets = ARRAY_SIZE(rt5651_dapm_widgets),
1717 .dapm_routes = rt5651_dapm_routes,
1718 .num_dapm_routes = ARRAY_SIZE(rt5651_dapm_routes),
1719 };
1720
1721 static const struct regmap_config rt5651_regmap = {
1722 .reg_bits = 8,
1723 .val_bits = 16,
1724
1725 .max_register = RT5651_DEVICE_ID + 1 + (ARRAY_SIZE(rt5651_ranges) *
1726 RT5651_PR_SPACING),
1727 .volatile_reg = rt5651_volatile_register,
1728 .readable_reg = rt5651_readable_register,
1729
1730 .cache_type = REGCACHE_RBTREE,
1731 .reg_defaults = rt5651_reg,
1732 .num_reg_defaults = ARRAY_SIZE(rt5651_reg),
1733 .ranges = rt5651_ranges,
1734 .num_ranges = ARRAY_SIZE(rt5651_ranges),
1735 };
1736
1737 static const struct i2c_device_id rt5651_i2c_id[] = {
1738 { "rt5651", 0 },
1739 { }
1740 };
1741 MODULE_DEVICE_TABLE(i2c, rt5651_i2c_id);
1742
1743 static int rt5651_i2c_probe(struct i2c_client *i2c,
1744 const struct i2c_device_id *id)
1745 {
1746 struct rt5651_platform_data *pdata = dev_get_platdata(&i2c->dev);
1747 struct rt5651_priv *rt5651;
1748 int ret;
1749
1750 rt5651 = devm_kzalloc(&i2c->dev, sizeof(*rt5651),
1751 GFP_KERNEL);
1752 if (NULL == rt5651)
1753 return -ENOMEM;
1754
1755 i2c_set_clientdata(i2c, rt5651);
1756
1757 if (pdata)
1758 rt5651->pdata = *pdata;
1759
1760 rt5651->regmap = devm_regmap_init_i2c(i2c, &rt5651_regmap);
1761 if (IS_ERR(rt5651->regmap)) {
1762 ret = PTR_ERR(rt5651->regmap);
1763 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1764 ret);
1765 return ret;
1766 }
1767
1768 regmap_read(rt5651->regmap, RT5651_DEVICE_ID, &ret);
1769 if (ret != RT5651_DEVICE_ID_VALUE) {
1770 dev_err(&i2c->dev,
1771 "Device with ID register %x is not rt5651\n", ret);
1772 return -ENODEV;
1773 }
1774
1775 regmap_write(rt5651->regmap, RT5651_RESET, 0);
1776
1777 ret = regmap_register_patch(rt5651->regmap, init_list,
1778 ARRAY_SIZE(init_list));
1779 if (ret != 0)
1780 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1781
1782 if (rt5651->pdata.in2_diff)
1783 regmap_update_bits(rt5651->regmap, RT5651_IN1_IN2,
1784 RT5651_IN_DF2, RT5651_IN_DF2);
1785
1786 if (rt5651->pdata.dmic_en)
1787 regmap_update_bits(rt5651->regmap, RT5651_GPIO_CTRL1,
1788 RT5651_GP2_PIN_MASK, RT5651_GP2_PIN_DMIC1_SCL);
1789
1790 rt5651->hp_mute = 1;
1791
1792 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5651,
1793 rt5651_dai, ARRAY_SIZE(rt5651_dai));
1794
1795 return ret;
1796 }
1797
1798 static int rt5651_i2c_remove(struct i2c_client *i2c)
1799 {
1800 snd_soc_unregister_codec(&i2c->dev);
1801
1802 return 0;
1803 }
1804
1805 static struct i2c_driver rt5651_i2c_driver = {
1806 .driver = {
1807 .name = "rt5651",
1808 .owner = THIS_MODULE,
1809 },
1810 .probe = rt5651_i2c_probe,
1811 .remove = rt5651_i2c_remove,
1812 .id_table = rt5651_i2c_id,
1813 };
1814 module_i2c_driver(rt5651_i2c_driver);
1815
1816 MODULE_DESCRIPTION("ASoC RT5651 driver");
1817 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1818 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support