?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
jme: Fix device PM wakeup API usage
[linux/fpc-iii.git] / sound / soc / codecs / rt5677.c
blobd48b484ce47e51605b06b34198f95ea9a14f5e8c
1 /*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/fs.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/regmap.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/spi/spi.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29
30 #include "rt5677.h"
31
32 #define RT5677_DEVICE_ID 0x6327
33
34 #define RT5677_PR_RANGE_BASE (0xff + 1)
35 #define RT5677_PR_SPACING 0x100
36
37 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
38
39 static const struct regmap_range_cfg rt5677_ranges[] = {
40 {
41 .name = "PR",
42 .range_min = RT5677_PR_BASE,
43 .range_max = RT5677_PR_BASE + 0xfd,
44 .selector_reg = RT5677_PRIV_INDEX,
45 .selector_mask = 0xff,
46 .selector_shift = 0x0,
47 .window_start = RT5677_PRIV_DATA,
48 .window_len = 0x1,
49 },
50 };
51
52 static const struct reg_default init_list[] = {
53 {RT5677_PR_BASE + 0x3d, 0x364d},
54 {RT5677_PR_BASE + 0x17, 0x4fc0},
55 {RT5677_PR_BASE + 0x13, 0x0312},
56 {RT5677_PR_BASE + 0x1e, 0x0000},
57 {RT5677_PR_BASE + 0x12, 0x0eaa},
58 {RT5677_PR_BASE + 0x14, 0x018a},
59 {RT5677_PR_BASE + 0x15, 0x0490},
60 {RT5677_PR_BASE + 0x38, 0x0f71},
61 {RT5677_PR_BASE + 0x39, 0x0f71},
62 };
63 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
64
65 static const struct reg_default rt5677_reg[] = {
66 {RT5677_RESET , 0x0000},
67 {RT5677_LOUT1 , 0xa800},
68 {RT5677_IN1 , 0x0000},
69 {RT5677_MICBIAS , 0x0000},
70 {RT5677_SLIMBUS_PARAM , 0x0000},
71 {RT5677_SLIMBUS_RX , 0x0000},
72 {RT5677_SLIMBUS_CTRL , 0x0000},
73 {RT5677_SIDETONE_CTRL , 0x000b},
74 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
75 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
76 {RT5677_DAC4_DIG_VOL , 0xafaf},
77 {RT5677_DAC3_DIG_VOL , 0xafaf},
78 {RT5677_DAC1_DIG_VOL , 0xafaf},
79 {RT5677_DAC2_DIG_VOL , 0xafaf},
80 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
81 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
82 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
83 {RT5677_STO1_2_ADC_BST , 0x0000},
84 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_ADC_BST_CTRL2 , 0x0000},
86 {RT5677_STO3_4_ADC_BST , 0x0000},
87 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
89 {RT5677_STO4_ADC_MIXER , 0xd4c0},
90 {RT5677_STO3_ADC_MIXER , 0xd4c0},
91 {RT5677_STO2_ADC_MIXER , 0xd4c0},
92 {RT5677_STO1_ADC_MIXER , 0xd4c0},
93 {RT5677_MONO_ADC_MIXER , 0xd4d1},
94 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
95 {RT5677_STO1_DAC_MIXER , 0xaaaa},
96 {RT5677_MONO_DAC_MIXER , 0xaaaa},
97 {RT5677_DD1_MIXER , 0xaaaa},
98 {RT5677_DD2_MIXER , 0xaaaa},
99 {RT5677_IF3_DATA , 0x0000},
100 {RT5677_IF4_DATA , 0x0000},
101 {RT5677_PDM_OUT_CTRL , 0x8888},
102 {RT5677_PDM_DATA_CTRL1 , 0x0000},
103 {RT5677_PDM_DATA_CTRL2 , 0x0000},
104 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
105 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
106 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
107 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
108 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
109 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
110 {RT5677_TDM1_CTRL1 , 0x0300},
111 {RT5677_TDM1_CTRL2 , 0x0000},
112 {RT5677_TDM1_CTRL3 , 0x4000},
113 {RT5677_TDM1_CTRL4 , 0x0123},
114 {RT5677_TDM1_CTRL5 , 0x4567},
115 {RT5677_TDM2_CTRL1 , 0x0300},
116 {RT5677_TDM2_CTRL2 , 0x0000},
117 {RT5677_TDM2_CTRL3 , 0x4000},
118 {RT5677_TDM2_CTRL4 , 0x0123},
119 {RT5677_TDM2_CTRL5 , 0x4567},
120 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
121 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
122 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
123 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
124 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
128 {RT5677_DMIC_CTRL1 , 0x1505},
129 {RT5677_DMIC_CTRL2 , 0x0055},
130 {RT5677_HAP_GENE_CTRL1 , 0x0111},
131 {RT5677_HAP_GENE_CTRL2 , 0x0064},
132 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
133 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
134 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
135 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
136 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
137 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
138 {RT5677_HAP_GENE_CTRL9 , 0xf000},
139 {RT5677_HAP_GENE_CTRL10 , 0x0000},
140 {RT5677_PWR_DIG1 , 0x0000},
141 {RT5677_PWR_DIG2 , 0x0000},
142 {RT5677_PWR_ANLG1 , 0x0055},
143 {RT5677_PWR_ANLG2 , 0x0000},
144 {RT5677_PWR_DSP1 , 0x0001},
145 {RT5677_PWR_DSP_ST , 0x0000},
146 {RT5677_PWR_DSP2 , 0x0000},
147 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
148 {RT5677_PRIV_INDEX , 0x0000},
149 {RT5677_PRIV_DATA , 0x0000},
150 {RT5677_I2S4_SDP , 0x8000},
151 {RT5677_I2S1_SDP , 0x8000},
152 {RT5677_I2S2_SDP , 0x8000},
153 {RT5677_I2S3_SDP , 0x8000},
154 {RT5677_CLK_TREE_CTRL1 , 0x1111},
155 {RT5677_CLK_TREE_CTRL2 , 0x1111},
156 {RT5677_CLK_TREE_CTRL3 , 0x0000},
157 {RT5677_PLL1_CTRL1 , 0x0000},
158 {RT5677_PLL1_CTRL2 , 0x0000},
159 {RT5677_PLL2_CTRL1 , 0x0c60},
160 {RT5677_PLL2_CTRL2 , 0x2000},
161 {RT5677_GLB_CLK1 , 0x0000},
162 {RT5677_GLB_CLK2 , 0x0000},
163 {RT5677_ASRC_1 , 0x0000},
164 {RT5677_ASRC_2 , 0x0000},
165 {RT5677_ASRC_3 , 0x0000},
166 {RT5677_ASRC_4 , 0x0000},
167 {RT5677_ASRC_5 , 0x0000},
168 {RT5677_ASRC_6 , 0x0000},
169 {RT5677_ASRC_7 , 0x0000},
170 {RT5677_ASRC_8 , 0x0000},
171 {RT5677_ASRC_9 , 0x0000},
172 {RT5677_ASRC_10 , 0x0000},
173 {RT5677_ASRC_11 , 0x0000},
174 {RT5677_ASRC_12 , 0x0008},
175 {RT5677_ASRC_13 , 0x0000},
176 {RT5677_ASRC_14 , 0x0000},
177 {RT5677_ASRC_15 , 0x0000},
178 {RT5677_ASRC_16 , 0x0000},
179 {RT5677_ASRC_17 , 0x0000},
180 {RT5677_ASRC_18 , 0x0000},
181 {RT5677_ASRC_19 , 0x0000},
182 {RT5677_ASRC_20 , 0x0000},
183 {RT5677_ASRC_21 , 0x000c},
184 {RT5677_ASRC_22 , 0x0000},
185 {RT5677_ASRC_23 , 0x0000},
186 {RT5677_VAD_CTRL1 , 0x2184},
187 {RT5677_VAD_CTRL2 , 0x010a},
188 {RT5677_VAD_CTRL3 , 0x0aea},
189 {RT5677_VAD_CTRL4 , 0x000c},
190 {RT5677_VAD_CTRL5 , 0x0000},
191 {RT5677_DSP_INB_CTRL1 , 0x0000},
192 {RT5677_DSP_INB_CTRL2 , 0x0000},
193 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
194 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
195 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
196 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
197 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
198 {RT5677_ADC_EQ_CTRL1 , 0x6000},
199 {RT5677_ADC_EQ_CTRL2 , 0x0000},
200 {RT5677_EQ_CTRL1 , 0xc000},
201 {RT5677_EQ_CTRL2 , 0x0000},
202 {RT5677_EQ_CTRL3 , 0x0000},
203 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
204 {RT5677_JD_CTRL1 , 0x0000},
205 {RT5677_JD_CTRL2 , 0x0000},
206 {RT5677_JD_CTRL3 , 0x0000},
207 {RT5677_IRQ_CTRL1 , 0x0000},
208 {RT5677_IRQ_CTRL2 , 0x0000},
209 {RT5677_GPIO_ST , 0x0000},
210 {RT5677_GPIO_CTRL1 , 0x0000},
211 {RT5677_GPIO_CTRL2 , 0x0000},
212 {RT5677_GPIO_CTRL3 , 0x0000},
213 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
214 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
215 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
216 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
217 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
218 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
219 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
220 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
221 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
222 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
223 {RT5677_MB_DRC_CTRL1 , 0x0f20},
224 {RT5677_DRC1_CTRL1 , 0x001f},
225 {RT5677_DRC1_CTRL2 , 0x020c},
226 {RT5677_DRC1_CTRL3 , 0x1f00},
227 {RT5677_DRC1_CTRL4 , 0x0000},
228 {RT5677_DRC1_CTRL5 , 0x0000},
229 {RT5677_DRC1_CTRL6 , 0x0029},
230 {RT5677_DRC2_CTRL1 , 0x001f},
231 {RT5677_DRC2_CTRL2 , 0x020c},
232 {RT5677_DRC2_CTRL3 , 0x1f00},
233 {RT5677_DRC2_CTRL4 , 0x0000},
234 {RT5677_DRC2_CTRL5 , 0x0000},
235 {RT5677_DRC2_CTRL6 , 0x0029},
236 {RT5677_DRC1_HL_CTRL1 , 0x8000},
237 {RT5677_DRC1_HL_CTRL2 , 0x0200},
238 {RT5677_DRC2_HL_CTRL1 , 0x8000},
239 {RT5677_DRC2_HL_CTRL2 , 0x0200},
240 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
241 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
242 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
243 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
244 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
245 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
246 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
247 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
248 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
249 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
250 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
251 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
252 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
253 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
254 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
255 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
256 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
257 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
258 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
259 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
260 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
261 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
262 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
263 {RT5677_DIG_MISC , 0x0000},
264 {RT5677_GEN_CTRL1 , 0x0000},
265 {RT5677_GEN_CTRL2 , 0x0000},
266 {RT5677_VENDOR_ID , 0x0000},
267 {RT5677_VENDOR_ID1 , 0x10ec},
268 {RT5677_VENDOR_ID2 , 0x6327},
269 };
270
271 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
272 {
273 int i;
274
275 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
276 if (reg >= rt5677_ranges[i].range_min &&
277 reg <= rt5677_ranges[i].range_max) {
278 return true;
279 }
280 }
281
282 switch (reg) {
283 case RT5677_RESET:
284 case RT5677_SLIMBUS_PARAM:
285 case RT5677_PDM_DATA_CTRL1:
286 case RT5677_PDM_DATA_CTRL2:
287 case RT5677_PDM1_DATA_CTRL4:
288 case RT5677_PDM2_DATA_CTRL4:
289 case RT5677_I2C_MASTER_CTRL1:
290 case RT5677_I2C_MASTER_CTRL7:
291 case RT5677_I2C_MASTER_CTRL8:
292 case RT5677_HAP_GENE_CTRL2:
293 case RT5677_PWR_DSP_ST:
294 case RT5677_PRIV_DATA:
295 case RT5677_PLL1_CTRL2:
296 case RT5677_PLL2_CTRL2:
297 case RT5677_ASRC_22:
298 case RT5677_ASRC_23:
299 case RT5677_VAD_CTRL5:
300 case RT5677_ADC_EQ_CTRL1:
301 case RT5677_EQ_CTRL1:
302 case RT5677_IRQ_CTRL1:
303 case RT5677_IRQ_CTRL2:
304 case RT5677_GPIO_ST:
305 case RT5677_DSP_INB1_SRC_CTRL4:
306 case RT5677_DSP_INB2_SRC_CTRL4:
307 case RT5677_DSP_INB3_SRC_CTRL4:
308 case RT5677_DSP_OUTB1_SRC_CTRL4:
309 case RT5677_DSP_OUTB2_SRC_CTRL4:
310 case RT5677_VENDOR_ID:
311 case RT5677_VENDOR_ID1:
312 case RT5677_VENDOR_ID2:
313 return true;
314 default:
315 return false;
316 }
317 }
318
319 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
320 {
321 int i;
322
323 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
324 if (reg >= rt5677_ranges[i].range_min &&
325 reg <= rt5677_ranges[i].range_max) {
326 return true;
327 }
328 }
329
330 switch (reg) {
331 case RT5677_RESET:
332 case RT5677_LOUT1:
333 case RT5677_IN1:
334 case RT5677_MICBIAS:
335 case RT5677_SLIMBUS_PARAM:
336 case RT5677_SLIMBUS_RX:
337 case RT5677_SLIMBUS_CTRL:
338 case RT5677_SIDETONE_CTRL:
339 case RT5677_ANA_DAC1_2_3_SRC:
340 case RT5677_IF_DSP_DAC3_4_MIXER:
341 case RT5677_DAC4_DIG_VOL:
342 case RT5677_DAC3_DIG_VOL:
343 case RT5677_DAC1_DIG_VOL:
344 case RT5677_DAC2_DIG_VOL:
345 case RT5677_IF_DSP_DAC2_MIXER:
346 case RT5677_STO1_ADC_DIG_VOL:
347 case RT5677_MONO_ADC_DIG_VOL:
348 case RT5677_STO1_2_ADC_BST:
349 case RT5677_STO2_ADC_DIG_VOL:
350 case RT5677_ADC_BST_CTRL2:
351 case RT5677_STO3_4_ADC_BST:
352 case RT5677_STO3_ADC_DIG_VOL:
353 case RT5677_STO4_ADC_DIG_VOL:
354 case RT5677_STO4_ADC_MIXER:
355 case RT5677_STO3_ADC_MIXER:
356 case RT5677_STO2_ADC_MIXER:
357 case RT5677_STO1_ADC_MIXER:
358 case RT5677_MONO_ADC_MIXER:
359 case RT5677_ADC_IF_DSP_DAC1_MIXER:
360 case RT5677_STO1_DAC_MIXER:
361 case RT5677_MONO_DAC_MIXER:
362 case RT5677_DD1_MIXER:
363 case RT5677_DD2_MIXER:
364 case RT5677_IF3_DATA:
365 case RT5677_IF4_DATA:
366 case RT5677_PDM_OUT_CTRL:
367 case RT5677_PDM_DATA_CTRL1:
368 case RT5677_PDM_DATA_CTRL2:
369 case RT5677_PDM1_DATA_CTRL2:
370 case RT5677_PDM1_DATA_CTRL3:
371 case RT5677_PDM1_DATA_CTRL4:
372 case RT5677_PDM2_DATA_CTRL2:
373 case RT5677_PDM2_DATA_CTRL3:
374 case RT5677_PDM2_DATA_CTRL4:
375 case RT5677_TDM1_CTRL1:
376 case RT5677_TDM1_CTRL2:
377 case RT5677_TDM1_CTRL3:
378 case RT5677_TDM1_CTRL4:
379 case RT5677_TDM1_CTRL5:
380 case RT5677_TDM2_CTRL1:
381 case RT5677_TDM2_CTRL2:
382 case RT5677_TDM2_CTRL3:
383 case RT5677_TDM2_CTRL4:
384 case RT5677_TDM2_CTRL5:
385 case RT5677_I2C_MASTER_CTRL1:
386 case RT5677_I2C_MASTER_CTRL2:
387 case RT5677_I2C_MASTER_CTRL3:
388 case RT5677_I2C_MASTER_CTRL4:
389 case RT5677_I2C_MASTER_CTRL5:
390 case RT5677_I2C_MASTER_CTRL6:
391 case RT5677_I2C_MASTER_CTRL7:
392 case RT5677_I2C_MASTER_CTRL8:
393 case RT5677_DMIC_CTRL1:
394 case RT5677_DMIC_CTRL2:
395 case RT5677_HAP_GENE_CTRL1:
396 case RT5677_HAP_GENE_CTRL2:
397 case RT5677_HAP_GENE_CTRL3:
398 case RT5677_HAP_GENE_CTRL4:
399 case RT5677_HAP_GENE_CTRL5:
400 case RT5677_HAP_GENE_CTRL6:
401 case RT5677_HAP_GENE_CTRL7:
402 case RT5677_HAP_GENE_CTRL8:
403 case RT5677_HAP_GENE_CTRL9:
404 case RT5677_HAP_GENE_CTRL10:
405 case RT5677_PWR_DIG1:
406 case RT5677_PWR_DIG2:
407 case RT5677_PWR_ANLG1:
408 case RT5677_PWR_ANLG2:
409 case RT5677_PWR_DSP1:
410 case RT5677_PWR_DSP_ST:
411 case RT5677_PWR_DSP2:
412 case RT5677_ADC_DAC_HPF_CTRL1:
413 case RT5677_PRIV_INDEX:
414 case RT5677_PRIV_DATA:
415 case RT5677_I2S4_SDP:
416 case RT5677_I2S1_SDP:
417 case RT5677_I2S2_SDP:
418 case RT5677_I2S3_SDP:
419 case RT5677_CLK_TREE_CTRL1:
420 case RT5677_CLK_TREE_CTRL2:
421 case RT5677_CLK_TREE_CTRL3:
422 case RT5677_PLL1_CTRL1:
423 case RT5677_PLL1_CTRL2:
424 case RT5677_PLL2_CTRL1:
425 case RT5677_PLL2_CTRL2:
426 case RT5677_GLB_CLK1:
427 case RT5677_GLB_CLK2:
428 case RT5677_ASRC_1:
429 case RT5677_ASRC_2:
430 case RT5677_ASRC_3:
431 case RT5677_ASRC_4:
432 case RT5677_ASRC_5:
433 case RT5677_ASRC_6:
434 case RT5677_ASRC_7:
435 case RT5677_ASRC_8:
436 case RT5677_ASRC_9:
437 case RT5677_ASRC_10:
438 case RT5677_ASRC_11:
439 case RT5677_ASRC_12:
440 case RT5677_ASRC_13:
441 case RT5677_ASRC_14:
442 case RT5677_ASRC_15:
443 case RT5677_ASRC_16:
444 case RT5677_ASRC_17:
445 case RT5677_ASRC_18:
446 case RT5677_ASRC_19:
447 case RT5677_ASRC_20:
448 case RT5677_ASRC_21:
449 case RT5677_ASRC_22:
450 case RT5677_ASRC_23:
451 case RT5677_VAD_CTRL1:
452 case RT5677_VAD_CTRL2:
453 case RT5677_VAD_CTRL3:
454 case RT5677_VAD_CTRL4:
455 case RT5677_VAD_CTRL5:
456 case RT5677_DSP_INB_CTRL1:
457 case RT5677_DSP_INB_CTRL2:
458 case RT5677_DSP_IN_OUTB_CTRL:
459 case RT5677_DSP_OUTB0_1_DIG_VOL:
460 case RT5677_DSP_OUTB2_3_DIG_VOL:
461 case RT5677_DSP_OUTB4_5_DIG_VOL:
462 case RT5677_DSP_OUTB6_7_DIG_VOL:
463 case RT5677_ADC_EQ_CTRL1:
464 case RT5677_ADC_EQ_CTRL2:
465 case RT5677_EQ_CTRL1:
466 case RT5677_EQ_CTRL2:
467 case RT5677_EQ_CTRL3:
468 case RT5677_SOFT_VOL_ZERO_CROSS1:
469 case RT5677_JD_CTRL1:
470 case RT5677_JD_CTRL2:
471 case RT5677_JD_CTRL3:
472 case RT5677_IRQ_CTRL1:
473 case RT5677_IRQ_CTRL2:
474 case RT5677_GPIO_ST:
475 case RT5677_GPIO_CTRL1:
476 case RT5677_GPIO_CTRL2:
477 case RT5677_GPIO_CTRL3:
478 case RT5677_STO1_ADC_HI_FILTER1:
479 case RT5677_STO1_ADC_HI_FILTER2:
480 case RT5677_MONO_ADC_HI_FILTER1:
481 case RT5677_MONO_ADC_HI_FILTER2:
482 case RT5677_STO2_ADC_HI_FILTER1:
483 case RT5677_STO2_ADC_HI_FILTER2:
484 case RT5677_STO3_ADC_HI_FILTER1:
485 case RT5677_STO3_ADC_HI_FILTER2:
486 case RT5677_STO4_ADC_HI_FILTER1:
487 case RT5677_STO4_ADC_HI_FILTER2:
488 case RT5677_MB_DRC_CTRL1:
489 case RT5677_DRC1_CTRL1:
490 case RT5677_DRC1_CTRL2:
491 case RT5677_DRC1_CTRL3:
492 case RT5677_DRC1_CTRL4:
493 case RT5677_DRC1_CTRL5:
494 case RT5677_DRC1_CTRL6:
495 case RT5677_DRC2_CTRL1:
496 case RT5677_DRC2_CTRL2:
497 case RT5677_DRC2_CTRL3:
498 case RT5677_DRC2_CTRL4:
499 case RT5677_DRC2_CTRL5:
500 case RT5677_DRC2_CTRL6:
501 case RT5677_DRC1_HL_CTRL1:
502 case RT5677_DRC1_HL_CTRL2:
503 case RT5677_DRC2_HL_CTRL1:
504 case RT5677_DRC2_HL_CTRL2:
505 case RT5677_DSP_INB1_SRC_CTRL1:
506 case RT5677_DSP_INB1_SRC_CTRL2:
507 case RT5677_DSP_INB1_SRC_CTRL3:
508 case RT5677_DSP_INB1_SRC_CTRL4:
509 case RT5677_DSP_INB2_SRC_CTRL1:
510 case RT5677_DSP_INB2_SRC_CTRL2:
511 case RT5677_DSP_INB2_SRC_CTRL3:
512 case RT5677_DSP_INB2_SRC_CTRL4:
513 case RT5677_DSP_INB3_SRC_CTRL1:
514 case RT5677_DSP_INB3_SRC_CTRL2:
515 case RT5677_DSP_INB3_SRC_CTRL3:
516 case RT5677_DSP_INB3_SRC_CTRL4:
517 case RT5677_DSP_OUTB1_SRC_CTRL1:
518 case RT5677_DSP_OUTB1_SRC_CTRL2:
519 case RT5677_DSP_OUTB1_SRC_CTRL3:
520 case RT5677_DSP_OUTB1_SRC_CTRL4:
521 case RT5677_DSP_OUTB2_SRC_CTRL1:
522 case RT5677_DSP_OUTB2_SRC_CTRL2:
523 case RT5677_DSP_OUTB2_SRC_CTRL3:
524 case RT5677_DSP_OUTB2_SRC_CTRL4:
525 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
526 case RT5677_DSP_OUTB_45_MIXER_CTRL:
527 case RT5677_DSP_OUTB_67_MIXER_CTRL:
528 case RT5677_DIG_MISC:
529 case RT5677_GEN_CTRL1:
530 case RT5677_GEN_CTRL2:
531 case RT5677_VENDOR_ID:
532 case RT5677_VENDOR_ID1:
533 case RT5677_VENDOR_ID2:
534 return true;
535 default:
536 return false;
537 }
538 }
539
540 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
541 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
542 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
543 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
544 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
545
546 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
547 static unsigned int bst_tlv[] = {
548 TLV_DB_RANGE_HEAD(7),
549 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
550 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
551 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
552 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
553 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
554 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
555 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
556 };
557
558 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
559 /* OUTPUT Control */
560 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
561 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
562 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
563 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
564 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
565 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
566
567 /* DAC Digital Volume */
568 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
569 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
570 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
571 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
572 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
573 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
574 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
575 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
576
577 /* IN1/IN2 Control */
578 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
579 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
580
581 /* ADC Digital Volume Control */
582 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
583 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
584 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
585 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
586 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
587 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
588 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
589 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
590 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
591 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
592
593 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
594 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
595 adc_vol_tlv),
596 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
597 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
598 adc_vol_tlv),
599 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
600 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
601 adc_vol_tlv),
602 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
603 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
604 adc_vol_tlv),
605 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
606 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0,
607 adc_vol_tlv),
608
609 /* ADC Boost Volume Control */
610 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5677_STO1_2_ADC_BST,
611 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
612 adc_bst_tlv),
613 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5677_STO1_2_ADC_BST,
614 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
615 adc_bst_tlv),
616 SOC_DOUBLE_TLV("STO3 ADC Boost Gain", RT5677_STO3_4_ADC_BST,
617 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
618 adc_bst_tlv),
619 SOC_DOUBLE_TLV("STO4 ADC Boost Gain", RT5677_STO3_4_ADC_BST,
620 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
621 adc_bst_tlv),
622 SOC_DOUBLE_TLV("Mono ADC Boost Gain", RT5677_ADC_BST_CTRL2,
623 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
624 adc_bst_tlv),
625 };
626
627 /**
628 * set_dmic_clk - Set parameter of dmic.
629 *
630 * @w: DAPM widget.
631 * @kcontrol: The kcontrol of this widget.
632 * @event: Event id.
633 *
634 * Choose dmic clock between 1MHz and 3MHz.
635 * It is better for clock to approximate 3MHz.
636 */
637 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
638 struct snd_kcontrol *kcontrol, int event)
639 {
640 struct snd_soc_codec *codec = w->codec;
641 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
642 int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL, i;
643 int rate, red, bound, temp;
644
645 rate = rt5677->sysclk;
646 red = 3000000 * 12;
647 for (i = 0; i < ARRAY_SIZE(div); i++) {
648 bound = div[i] * 3000000;
649 if (rate > bound)
650 continue;
651 temp = bound - rate;
652 if (temp < red) {
653 red = temp;
654 idx = i;
655 }
656 }
657
658 if (idx < 0)
659 dev_err(codec->dev, "Failed to set DMIC clock\n");
660 else
661 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
662 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
663 return idx;
664 }
665
666 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
667 struct snd_soc_dapm_widget *sink)
668 {
669 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
670 unsigned int val;
671
672 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
673 val &= RT5677_SCLK_SRC_MASK;
674 if (val == RT5677_SCLK_SRC_PLL1)
675 return 1;
676 else
677 return 0;
678 }
679
680 /* Digital Mixer */
681 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
682 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
683 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
684 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
685 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
686 };
687
688 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
689 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
690 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
691 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
692 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
693 };
694
695 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
696 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
697 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
698 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
699 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
700 };
701
702 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
703 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
704 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
705 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
706 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
707 };
708
709 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
710 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
711 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
712 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
713 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
714 };
715
716 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
717 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
718 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
719 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
720 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
721 };
722
723 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
724 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
725 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
726 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
727 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
728 };
729
730 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
731 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
732 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
733 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
734 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
735 };
736
737 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
738 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
739 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
740 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
741 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
742 };
743
744 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
745 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
746 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
747 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
748 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
749 };
750
751 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
752 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
753 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
754 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
755 RT5677_M_DAC1_L_SFT, 1, 1),
756 };
757
758 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
759 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
760 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
761 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
762 RT5677_M_DAC1_R_SFT, 1, 1),
763 };
764
765 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
766 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
767 RT5677_M_ST_DAC1_L_SFT, 1, 1),
768 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
769 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
770 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
771 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
772 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
773 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
774 };
775
776 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
777 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
778 RT5677_M_ST_DAC1_R_SFT, 1, 1),
779 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
780 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
781 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
782 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
783 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
784 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
785 };
786
787 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
788 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
789 RT5677_M_ST_DAC2_L_SFT, 1, 1),
790 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
791 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
792 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
793 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
794 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
795 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
796 };
797
798 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
799 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
800 RT5677_M_ST_DAC2_R_SFT, 1, 1),
801 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
802 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
803 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
804 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
805 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
806 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
807 };
808
809 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
810 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
811 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
812 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
813 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
814 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
815 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
816 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
817 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
818 };
819
820 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
821 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
822 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
823 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
824 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
825 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
826 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
827 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
828 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
829 };
830
831 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
832 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
833 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
834 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
835 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
836 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
837 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
838 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
839 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
840 };
841
842 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
843 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
844 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
845 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
846 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
847 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
848 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
849 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
850 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
851 };
852
853 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
854 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
855 RT5677_DSP_IB_01_H_SFT, 1, 1),
856 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
857 RT5677_DSP_IB_23_H_SFT, 1, 1),
858 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
859 RT5677_DSP_IB_45_H_SFT, 1, 1),
860 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
861 RT5677_DSP_IB_6_H_SFT, 1, 1),
862 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
863 RT5677_DSP_IB_7_H_SFT, 1, 1),
864 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
865 RT5677_DSP_IB_8_H_SFT, 1, 1),
866 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
867 RT5677_DSP_IB_9_H_SFT, 1, 1),
868 };
869
870 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
871 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
872 RT5677_DSP_IB_01_L_SFT, 1, 1),
873 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
874 RT5677_DSP_IB_23_L_SFT, 1, 1),
875 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
876 RT5677_DSP_IB_45_L_SFT, 1, 1),
877 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
878 RT5677_DSP_IB_6_L_SFT, 1, 1),
879 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
880 RT5677_DSP_IB_7_L_SFT, 1, 1),
881 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
882 RT5677_DSP_IB_8_L_SFT, 1, 1),
883 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
884 RT5677_DSP_IB_9_L_SFT, 1, 1),
885 };
886
887 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
888 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
889 RT5677_DSP_IB_01_H_SFT, 1, 1),
890 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
891 RT5677_DSP_IB_23_H_SFT, 1, 1),
892 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
893 RT5677_DSP_IB_45_H_SFT, 1, 1),
894 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
895 RT5677_DSP_IB_6_H_SFT, 1, 1),
896 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
897 RT5677_DSP_IB_7_H_SFT, 1, 1),
898 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
899 RT5677_DSP_IB_8_H_SFT, 1, 1),
900 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
901 RT5677_DSP_IB_9_H_SFT, 1, 1),
902 };
903
904 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
905 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
906 RT5677_DSP_IB_01_L_SFT, 1, 1),
907 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
908 RT5677_DSP_IB_23_L_SFT, 1, 1),
909 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
910 RT5677_DSP_IB_45_L_SFT, 1, 1),
911 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
912 RT5677_DSP_IB_6_L_SFT, 1, 1),
913 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
914 RT5677_DSP_IB_7_L_SFT, 1, 1),
915 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
916 RT5677_DSP_IB_8_L_SFT, 1, 1),
917 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
918 RT5677_DSP_IB_9_L_SFT, 1, 1),
919 };
920
921 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
922 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
923 RT5677_DSP_IB_01_H_SFT, 1, 1),
924 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
925 RT5677_DSP_IB_23_H_SFT, 1, 1),
926 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
927 RT5677_DSP_IB_45_H_SFT, 1, 1),
928 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
929 RT5677_DSP_IB_6_H_SFT, 1, 1),
930 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
931 RT5677_DSP_IB_7_H_SFT, 1, 1),
932 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
933 RT5677_DSP_IB_8_H_SFT, 1, 1),
934 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
935 RT5677_DSP_IB_9_H_SFT, 1, 1),
936 };
937
938 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
939 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
940 RT5677_DSP_IB_01_L_SFT, 1, 1),
941 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
942 RT5677_DSP_IB_23_L_SFT, 1, 1),
943 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
944 RT5677_DSP_IB_45_L_SFT, 1, 1),
945 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
946 RT5677_DSP_IB_6_L_SFT, 1, 1),
947 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
948 RT5677_DSP_IB_7_L_SFT, 1, 1),
949 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
950 RT5677_DSP_IB_8_L_SFT, 1, 1),
951 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
952 RT5677_DSP_IB_9_L_SFT, 1, 1),
953 };
954
955
956 /* Mux */
957 /* DAC1 L/R source */ /* MX-29 [10:8] */
958 static const char * const rt5677_dac1_src[] = {
959 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
960 "OB 01"
961 };
962
963 static SOC_ENUM_SINGLE_DECL(
964 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
965 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
966
967 static const struct snd_kcontrol_new rt5677_dac1_mux =
968 SOC_DAPM_ENUM("DAC1 source", rt5677_dac1_enum);
969
970 /* ADDA1 L/R source */ /* MX-29 [1:0] */
971 static const char * const rt5677_adda1_src[] = {
972 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
973 };
974
975 static SOC_ENUM_SINGLE_DECL(
976 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
977 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
978
979 static const struct snd_kcontrol_new rt5677_adda1_mux =
980 SOC_DAPM_ENUM("ADDA1 source", rt5677_adda1_enum);
981
982
983 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
984 static const char * const rt5677_dac2l_src[] = {
985 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
986 "OB 2",
987 };
988
989 static SOC_ENUM_SINGLE_DECL(
990 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
991 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
992
993 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
994 SOC_DAPM_ENUM("DAC2 L source", rt5677_dac2l_enum);
995
996 static const char * const rt5677_dac2r_src[] = {
997 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
998 "OB 3", "Haptic Generator", "VAD ADC"
999 };
1000
1001 static SOC_ENUM_SINGLE_DECL(
1002 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1003 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1004
1005 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1006 SOC_DAPM_ENUM("DAC2 R source", rt5677_dac2r_enum);
1007
1008 /*DAC3 L/R source*/ /* MX-16 [6:4] [2:0] */
1009 static const char * const rt5677_dac3l_src[] = {
1010 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1011 "SLB DAC 4", "OB 4"
1012 };
1013
1014 static SOC_ENUM_SINGLE_DECL(
1015 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1016 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1017
1018 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1019 SOC_DAPM_ENUM("DAC3 L source", rt5677_dac3l_enum);
1020
1021 static const char * const rt5677_dac3r_src[] = {
1022 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1023 "SLB DAC 5", "OB 5"
1024 };
1025
1026 static SOC_ENUM_SINGLE_DECL(
1027 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1028 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1029
1030 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1031 SOC_DAPM_ENUM("DAC3 R source", rt5677_dac3r_enum);
1032
1033 /*DAC4 L/R source*/ /* MX-16 [14:12] [10:8] */
1034 static const char * const rt5677_dac4l_src[] = {
1035 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1036 "SLB DAC 6", "OB 6"
1037 };
1038
1039 static SOC_ENUM_SINGLE_DECL(
1040 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1041 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1042
1043 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1044 SOC_DAPM_ENUM("DAC4 L source", rt5677_dac4l_enum);
1045
1046 static const char * const rt5677_dac4r_src[] = {
1047 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1048 "SLB DAC 7", "OB 7"
1049 };
1050
1051 static SOC_ENUM_SINGLE_DECL(
1052 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1053 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1054
1055 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1056 SOC_DAPM_ENUM("DAC4 R source", rt5677_dac4r_enum);
1057
1058 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1059 static const char * const rt5677_iob_bypass_src[] = {
1060 "Bypass", "Pass SRC"
1061 };
1062
1063 static SOC_ENUM_SINGLE_DECL(
1064 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1065 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1066
1067 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1068 SOC_DAPM_ENUM("OB01 Bypass source", rt5677_ob01_bypass_src_enum);
1069
1070 static SOC_ENUM_SINGLE_DECL(
1071 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1072 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1073
1074 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1075 SOC_DAPM_ENUM("OB23 Bypass source", rt5677_ob23_bypass_src_enum);
1076
1077 static SOC_ENUM_SINGLE_DECL(
1078 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1079 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1080
1081 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1082 SOC_DAPM_ENUM("IB01 Bypass source", rt5677_ib01_bypass_src_enum);
1083
1084 static SOC_ENUM_SINGLE_DECL(
1085 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1086 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1087
1088 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1089 SOC_DAPM_ENUM("IB23 Bypass source", rt5677_ib23_bypass_src_enum);
1090
1091 static SOC_ENUM_SINGLE_DECL(
1092 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1093 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1094
1095 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1096 SOC_DAPM_ENUM("IB45 Bypass source", rt5677_ib45_bypass_src_enum);
1097
1098 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1099 static const char * const rt5677_stereo_adc2_src[] = {
1100 "DD MIX1", "DMIC", "Stereo DAC MIX"
1101 };
1102
1103 static SOC_ENUM_SINGLE_DECL(
1104 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1105 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1106
1107 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1108 SOC_DAPM_ENUM("Stereo1 ADC2 source", rt5677_stereo1_adc2_enum);
1109
1110 static SOC_ENUM_SINGLE_DECL(
1111 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1112 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1113
1114 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1115 SOC_DAPM_ENUM("Stereo2 ADC2 source", rt5677_stereo2_adc2_enum);
1116
1117 static SOC_ENUM_SINGLE_DECL(
1118 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1119 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1120
1121 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1122 SOC_DAPM_ENUM("Stereo3 ADC2 source", rt5677_stereo3_adc2_enum);
1123
1124 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1125 static const char * const rt5677_dmic_src[] = {
1126 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1127 };
1128
1129 static SOC_ENUM_SINGLE_DECL(
1130 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1131 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1132
1133 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1134 SOC_DAPM_ENUM("Mono DMIC L source", rt5677_mono_dmic_l_enum);
1135
1136 static SOC_ENUM_SINGLE_DECL(
1137 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1138 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1139
1140 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1141 SOC_DAPM_ENUM("Mono DMIC R source", rt5677_mono_dmic_r_enum);
1142
1143 static SOC_ENUM_SINGLE_DECL(
1144 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1145 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1146
1147 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1148 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5677_stereo1_dmic_enum);
1149
1150 static SOC_ENUM_SINGLE_DECL(
1151 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1152 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1153
1154 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1155 SOC_DAPM_ENUM("Stereo2 DMIC source", rt5677_stereo2_dmic_enum);
1156
1157 static SOC_ENUM_SINGLE_DECL(
1158 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1159 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1160
1161 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1162 SOC_DAPM_ENUM("Stereo3 DMIC source", rt5677_stereo3_dmic_enum);
1163
1164 static SOC_ENUM_SINGLE_DECL(
1165 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1166 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1167
1168 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1169 SOC_DAPM_ENUM("Stereo4 DMIC source", rt5677_stereo4_dmic_enum);
1170
1171 /* Stereo2 ADC source */ /* MX-26 [0] */
1172 static const char * const rt5677_stereo2_adc_lr_src[] = {
1173 "L", "LR"
1174 };
1175
1176 static SOC_ENUM_SINGLE_DECL(
1177 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1178 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1179
1180 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1181 SOC_DAPM_ENUM("Stereo2 ADC LR source", rt5677_stereo2_adc_lr_enum);
1182
1183 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1184 static const char * const rt5677_stereo_adc1_src[] = {
1185 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1186 };
1187
1188 static SOC_ENUM_SINGLE_DECL(
1189 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1190 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1191
1192 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1193 SOC_DAPM_ENUM("Stereo1 ADC1 source", rt5677_stereo1_adc1_enum);
1194
1195 static SOC_ENUM_SINGLE_DECL(
1196 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1197 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1198
1199 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1200 SOC_DAPM_ENUM("Stereo2 ADC1 source", rt5677_stereo2_adc1_enum);
1201
1202 static SOC_ENUM_SINGLE_DECL(
1203 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1204 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1205
1206 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1207 SOC_DAPM_ENUM("Stereo3 ADC1 source", rt5677_stereo3_adc1_enum);
1208
1209 /* Mono ADC Left source 2 */ /* MX-28 [11:10] */
1210 static const char * const rt5677_mono_adc2_l_src[] = {
1211 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1212 };
1213
1214 static SOC_ENUM_SINGLE_DECL(
1215 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1216 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1217
1218 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1219 SOC_DAPM_ENUM("Mono ADC2 L source", rt5677_mono_adc2_l_enum);
1220
1221 /* Mono ADC Left source 1 */ /* MX-28 [13:12] */
1222 static const char * const rt5677_mono_adc1_l_src[] = {
1223 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1224 };
1225
1226 static SOC_ENUM_SINGLE_DECL(
1227 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1228 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1229
1230 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1231 SOC_DAPM_ENUM("Mono ADC1 L source", rt5677_mono_adc1_l_enum);
1232
1233 /* Mono ADC Right source 2 */ /* MX-28 [3:2] */
1234 static const char * const rt5677_mono_adc2_r_src[] = {
1235 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1236 };
1237
1238 static SOC_ENUM_SINGLE_DECL(
1239 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1240 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1241
1242 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1243 SOC_DAPM_ENUM("Mono ADC2 R source", rt5677_mono_adc2_r_enum);
1244
1245 /* Mono ADC Right source 1 */ /* MX-28 [5:4] */
1246 static const char * const rt5677_mono_adc1_r_src[] = {
1247 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1248 };
1249
1250 static SOC_ENUM_SINGLE_DECL(
1251 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1252 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1253
1254 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1255 SOC_DAPM_ENUM("Mono ADC1 R source", rt5677_mono_adc1_r_enum);
1256
1257 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1258 static const char * const rt5677_stereo4_adc2_src[] = {
1259 "DD MIX1", "DMIC", "DD MIX2"
1260 };
1261
1262 static SOC_ENUM_SINGLE_DECL(
1263 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1264 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1265
1266 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1267 SOC_DAPM_ENUM("Stereo4 ADC2 source", rt5677_stereo4_adc2_enum);
1268
1269
1270 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1271 static const char * const rt5677_stereo4_adc1_src[] = {
1272 "DD MIX1", "ADC1/2", "DD MIX2"
1273 };
1274
1275 static SOC_ENUM_SINGLE_DECL(
1276 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1277 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1278
1279 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1280 SOC_DAPM_ENUM("Stereo4 ADC1 source", rt5677_stereo4_adc1_enum);
1281
1282 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1283 static const char * const rt5677_inbound01_src[] = {
1284 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1285 "VAD ADC/DAC1 FS"
1286 };
1287
1288 static SOC_ENUM_SINGLE_DECL(
1289 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1290 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1291
1292 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1293 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1294
1295 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1296 static const char * const rt5677_inbound23_src[] = {
1297 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1298 "DAC1 FS", "IF4 DAC"
1299 };
1300
1301 static SOC_ENUM_SINGLE_DECL(
1302 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1303 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1304
1305 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1306 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1307
1308 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1309 static const char * const rt5677_inbound45_src[] = {
1310 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1311 "IF3 DAC"
1312 };
1313
1314 static SOC_ENUM_SINGLE_DECL(
1315 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1316 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1317
1318 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1319 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1320
1321 /* InBound6 Source */ /* MX-A3 [2:0] */
1322 static const char * const rt5677_inbound6_src[] = {
1323 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1324 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1325 };
1326
1327 static SOC_ENUM_SINGLE_DECL(
1328 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1329 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1330
1331 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1332 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1333
1334 /* InBound7 Source */ /* MX-A4 [14:12] */
1335 static const char * const rt5677_inbound7_src[] = {
1336 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1337 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1338 };
1339
1340 static SOC_ENUM_SINGLE_DECL(
1341 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1342 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1343
1344 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1345 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1346
1347 /* InBound8 Source */ /* MX-A4 [10:8] */
1348 static const char * const rt5677_inbound8_src[] = {
1349 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1350 "MONO ADC MIX L", "DACL1 FS"
1351 };
1352
1353 static SOC_ENUM_SINGLE_DECL(
1354 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1355 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1356
1357 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1358 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1359
1360 /* InBound9 Source */ /* MX-A4 [6:4] */
1361 static const char * const rt5677_inbound9_src[] = {
1362 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1363 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1364 };
1365
1366 static SOC_ENUM_SINGLE_DECL(
1367 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1368 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1369
1370 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1371 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1372
1373 /* VAD Source */ /* MX-9F [6:4] */
1374 static const char * const rt5677_vad_src[] = {
1375 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1376 "STO3 ADC MIX L"
1377 };
1378
1379 static SOC_ENUM_SINGLE_DECL(
1380 rt5677_vad_enum, RT5677_VAD_CTRL4,
1381 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1382
1383 static const struct snd_kcontrol_new rt5677_vad_src_mux =
1384 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1385
1386 /* Sidetone Source */ /* MX-13 [11:9] */
1387 static const char * const rt5677_sidetone_src[] = {
1388 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1389 };
1390
1391 static SOC_ENUM_SINGLE_DECL(
1392 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1393 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1394
1395 static const struct snd_kcontrol_new rt5677_sidetone_mux =
1396 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1397
1398 /* DAC1/2 Source */ /* MX-15 [1:0] */
1399 static const char * const rt5677_dac12_src[] = {
1400 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1401 };
1402
1403 static SOC_ENUM_SINGLE_DECL(
1404 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1405 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1406
1407 static const struct snd_kcontrol_new rt5677_dac12_mux =
1408 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1409
1410 /* DAC3 Source */ /* MX-15 [5:4] */
1411 static const char * const rt5677_dac3_src[] = {
1412 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1413 };
1414
1415 static SOC_ENUM_SINGLE_DECL(
1416 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1417 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1418
1419 static const struct snd_kcontrol_new rt5677_dac3_mux =
1420 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1421
1422 /* PDM channel source */ /* MX-31 [13:12][9:8][5:4][1:0] */
1423 static const char * const rt5677_pdm_src[] = {
1424 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1425 };
1426
1427 static SOC_ENUM_SINGLE_DECL(
1428 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1429 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1430
1431 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1432 SOC_DAPM_ENUM("PDM1 source", rt5677_pdm1_l_enum);
1433
1434 static SOC_ENUM_SINGLE_DECL(
1435 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1436 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1437
1438 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1439 SOC_DAPM_ENUM("PDM2 source", rt5677_pdm2_l_enum);
1440
1441 static SOC_ENUM_SINGLE_DECL(
1442 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1443 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1444
1445 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1446 SOC_DAPM_ENUM("PDM1 source", rt5677_pdm1_r_enum);
1447
1448 static SOC_ENUM_SINGLE_DECL(
1449 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1450 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1451
1452 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1453 SOC_DAPM_ENUM("PDM2 source", rt5677_pdm2_r_enum);
1454
1455 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0]*/
1456 static const char * const rt5677_if12_adc1_src[] = {
1457 "STO1 ADC MIX", "OB01", "VAD ADC"
1458 };
1459
1460 static SOC_ENUM_SINGLE_DECL(
1461 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1462 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1463
1464 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1465 SOC_DAPM_ENUM("IF1 ADC1 source", rt5677_if1_adc1_enum);
1466
1467 static SOC_ENUM_SINGLE_DECL(
1468 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1469 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1470
1471 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1472 SOC_DAPM_ENUM("IF2 ADC1 source", rt5677_if2_adc1_enum);
1473
1474 static SOC_ENUM_SINGLE_DECL(
1475 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1476 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1477
1478 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1479 SOC_DAPM_ENUM("SLB ADC1 source", rt5677_slb_adc1_enum);
1480
1481 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1482 static const char * const rt5677_if12_adc2_src[] = {
1483 "STO2 ADC MIX", "OB23"
1484 };
1485
1486 static SOC_ENUM_SINGLE_DECL(
1487 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1488 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1489
1490 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1491 SOC_DAPM_ENUM("IF1 ADC2 source", rt5677_if1_adc2_enum);
1492
1493 static SOC_ENUM_SINGLE_DECL(
1494 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1495 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1496
1497 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1498 SOC_DAPM_ENUM("IF2 ADC2 source", rt5677_if2_adc2_enum);
1499
1500 static SOC_ENUM_SINGLE_DECL(
1501 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1502 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1503
1504 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1505 SOC_DAPM_ENUM("SLB ADC2 source", rt5677_slb_adc2_enum);
1506
1507 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1508 static const char * const rt5677_if12_adc3_src[] = {
1509 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1510 };
1511
1512 static SOC_ENUM_SINGLE_DECL(
1513 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1514 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1515
1516 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1517 SOC_DAPM_ENUM("IF1 ADC3 source", rt5677_if1_adc3_enum);
1518
1519 static SOC_ENUM_SINGLE_DECL(
1520 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1521 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1522
1523 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1524 SOC_DAPM_ENUM("IF2 ADC3 source", rt5677_if2_adc3_enum);
1525
1526 static SOC_ENUM_SINGLE_DECL(
1527 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1528 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1529
1530 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1531 SOC_DAPM_ENUM("SLB ADC3 source", rt5677_slb_adc3_enum);
1532
1533 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1534 static const char * const rt5677_if12_adc4_src[] = {
1535 "STO4 ADC MIX", "OB67", "OB01"
1536 };
1537
1538 static SOC_ENUM_SINGLE_DECL(
1539 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1540 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1541
1542 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1543 SOC_DAPM_ENUM("IF1 ADC4 source", rt5677_if1_adc4_enum);
1544
1545 static SOC_ENUM_SINGLE_DECL(
1546 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1547 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1548
1549 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1550 SOC_DAPM_ENUM("IF2 ADC4 source", rt5677_if2_adc4_enum);
1551
1552 static SOC_ENUM_SINGLE_DECL(
1553 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1554 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1555
1556 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1557 SOC_DAPM_ENUM("SLB ADC4 source", rt5677_slb_adc4_enum);
1558
1559 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4]*/
1560 static const char * const rt5677_if34_adc_src[] = {
1561 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1562 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1563 };
1564
1565 static SOC_ENUM_SINGLE_DECL(
1566 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1567 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1568
1569 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1570 SOC_DAPM_ENUM("IF3 ADC source", rt5677_if3_adc_enum);
1571
1572 static SOC_ENUM_SINGLE_DECL(
1573 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1574 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1575
1576 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1577 SOC_DAPM_ENUM("IF4 ADC source", rt5677_if4_adc_enum);
1578
1579 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
1580 struct snd_kcontrol *kcontrol, int event)
1581 {
1582 struct snd_soc_codec *codec = w->codec;
1583 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1584
1585 switch (event) {
1586 case SND_SOC_DAPM_POST_PMU:
1587 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1588 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
1589 break;
1590
1591 case SND_SOC_DAPM_PRE_PMD:
1592 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1593 RT5677_PWR_BST1_P, 0);
1594 break;
1595
1596 default:
1597 return 0;
1598 }
1599
1600 return 0;
1601 }
1602
1603 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
1604 struct snd_kcontrol *kcontrol, int event)
1605 {
1606 struct snd_soc_codec *codec = w->codec;
1607 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1608
1609 switch (event) {
1610 case SND_SOC_DAPM_POST_PMU:
1611 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1612 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
1613 break;
1614
1615 case SND_SOC_DAPM_PRE_PMD:
1616 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1617 RT5677_PWR_BST2_P, 0);
1618 break;
1619
1620 default:
1621 return 0;
1622 }
1623
1624 return 0;
1625 }
1626
1627 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
1628 struct snd_kcontrol *kcontrol, int event)
1629 {
1630 struct snd_soc_codec *codec = w->codec;
1631 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1632
1633 switch (event) {
1634 case SND_SOC_DAPM_POST_PMU:
1635 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
1636 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
1637 break;
1638 default:
1639 return 0;
1640 }
1641
1642 return 0;
1643 }
1644
1645 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
1646 struct snd_kcontrol *kcontrol, int event)
1647 {
1648 struct snd_soc_codec *codec = w->codec;
1649 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1650
1651 switch (event) {
1652 case SND_SOC_DAPM_POST_PMU:
1653 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
1654 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
1655 break;
1656 default:
1657 return 0;
1658 }
1659
1660 return 0;
1661 }
1662
1663 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
1664 struct snd_kcontrol *kcontrol, int event)
1665 {
1666 struct snd_soc_codec *codec = w->codec;
1667 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1668
1669 switch (event) {
1670 case SND_SOC_DAPM_POST_PMU:
1671 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1672 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1673 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
1674 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
1675 break;
1676 default:
1677 return 0;
1678 }
1679
1680 return 0;
1681 }
1682
1683 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1684 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
1685 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
1686 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
1687 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
1688
1689 /* Input Side */
1690 /* micbias */
1691 SND_SOC_DAPM_SUPPLY("micbias1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
1692 0, rt5677_set_micbias1_event, SND_SOC_DAPM_POST_PMU),
1693
1694 /* Input Lines */
1695 SND_SOC_DAPM_INPUT("DMIC L1"),
1696 SND_SOC_DAPM_INPUT("DMIC R1"),
1697 SND_SOC_DAPM_INPUT("DMIC L2"),
1698 SND_SOC_DAPM_INPUT("DMIC R2"),
1699 SND_SOC_DAPM_INPUT("DMIC L3"),
1700 SND_SOC_DAPM_INPUT("DMIC R3"),
1701 SND_SOC_DAPM_INPUT("DMIC L4"),
1702 SND_SOC_DAPM_INPUT("DMIC R4"),
1703
1704 SND_SOC_DAPM_INPUT("IN1P"),
1705 SND_SOC_DAPM_INPUT("IN1N"),
1706 SND_SOC_DAPM_INPUT("IN2P"),
1707 SND_SOC_DAPM_INPUT("IN2N"),
1708
1709 SND_SOC_DAPM_INPUT("Haptic Generator"),
1710
1711 SND_SOC_DAPM_PGA("DMIC1", RT5677_DMIC_CTRL1, RT5677_DMIC_1_EN_SFT, 0,
1712 NULL, 0),
1713 SND_SOC_DAPM_PGA("DMIC2", RT5677_DMIC_CTRL1, RT5677_DMIC_2_EN_SFT, 0,
1714 NULL, 0),
1715 SND_SOC_DAPM_PGA("DMIC3", RT5677_DMIC_CTRL1, RT5677_DMIC_3_EN_SFT, 0,
1716 NULL, 0),
1717 SND_SOC_DAPM_PGA("DMIC4", RT5677_DMIC_CTRL2, RT5677_DMIC_4_EN_SFT, 0,
1718 NULL, 0),
1719
1720 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1721 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1722
1723 /* Boost */
1724 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
1725 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
1726 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1727 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
1728 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
1729 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1730
1731 /* ADCs */
1732 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
1733 0, 0),
1734 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
1735 0, 0),
1736 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
1737
1738 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
1739 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
1740 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
1741 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
1742 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
1743 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
1744 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
1745 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
1746
1747 /* ADC Mux */
1748 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1749 &rt5677_sto1_dmic_mux),
1750 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1751 &rt5677_sto1_adc1_mux),
1752 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1753 &rt5677_sto1_adc2_mux),
1754 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
1755 &rt5677_sto2_dmic_mux),
1756 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1757 &rt5677_sto2_adc1_mux),
1758 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1759 &rt5677_sto2_adc2_mux),
1760 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
1761 &rt5677_sto2_adc_lr_mux),
1762 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
1763 &rt5677_sto3_dmic_mux),
1764 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1765 &rt5677_sto3_adc1_mux),
1766 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1767 &rt5677_sto3_adc2_mux),
1768 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
1769 &rt5677_sto4_dmic_mux),
1770 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1771 &rt5677_sto4_adc1_mux),
1772 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1773 &rt5677_sto4_adc2_mux),
1774 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1775 &rt5677_mono_dmic_l_mux),
1776 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1777 &rt5677_mono_dmic_r_mux),
1778 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
1779 &rt5677_mono_adc2_l_mux),
1780 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
1781 &rt5677_mono_adc1_l_mux),
1782 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
1783 &rt5677_mono_adc1_r_mux),
1784 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
1785 &rt5677_mono_adc2_r_mux),
1786
1787 /* ADC Mixer */
1788 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
1789 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
1790 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
1791 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
1792 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
1793 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
1794 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
1795 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
1796 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1797 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
1798 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1799 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
1800 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1801 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
1802 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1803 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
1804 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
1805 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
1806 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
1807 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
1808 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
1809 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
1810 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
1811 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
1812 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
1813 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1814 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1815 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
1816 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
1817 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1818 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1819 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
1820
1821 /* ADC PGA */
1822 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1823 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1824 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1825 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1826 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1827 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1828 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1829 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1830 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1831 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1832 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1833 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1834 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1835 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1836 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1837 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1838 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1839 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1840
1841 /* DSP */
1842 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
1843 &rt5677_ib9_src_mux),
1844 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
1845 &rt5677_ib8_src_mux),
1846 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
1847 &rt5677_ib7_src_mux),
1848 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
1849 &rt5677_ib6_src_mux),
1850 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
1851 &rt5677_ib45_src_mux),
1852 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
1853 &rt5677_ib23_src_mux),
1854 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
1855 &rt5677_ib01_src_mux),
1856 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
1857 &rt5677_ib45_bypass_src_mux),
1858 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1859 &rt5677_ib23_bypass_src_mux),
1860 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1861 &rt5677_ib01_bypass_src_mux),
1862 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1863 &rt5677_ob23_bypass_src_mux),
1864 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1865 &rt5677_ob01_bypass_src_mux),
1866
1867 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
1868 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
1869
1870 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
1871 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
1872 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
1873 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
1874 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
1875 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
1876
1877 /* Digital Interface */
1878 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
1879 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
1880 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1881 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1882 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1883 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1884 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1885 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1886 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1887 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1888 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1889 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1890 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1891 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1892 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1893 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1894 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1895 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1896
1897 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
1898 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
1899 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1900 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1901 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1902 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1903 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1904 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1905 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1906 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1907 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1908 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1909 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1910 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1911 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1912 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1913 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1914 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1915
1916 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
1917 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
1918 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1919 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1920 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1921 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1922 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1923 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1924
1925 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
1926 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
1927 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1928 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1929 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1930 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1931 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1932 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1933
1934 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
1935 RT5677_PWR_SLB_BIT, 0, NULL, 0),
1936 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1937 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1938 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1939 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1940 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1941 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1942 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1943 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1944 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1945 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1946 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1947 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1948 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1949 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1950 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1951 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1952
1953 /* Digital Interface Select */
1954 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1955 &rt5677_if1_adc1_mux),
1956 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1957 &rt5677_if1_adc2_mux),
1958 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1959 &rt5677_if1_adc3_mux),
1960 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1961 &rt5677_if1_adc4_mux),
1962 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1963 &rt5677_if2_adc1_mux),
1964 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1965 &rt5677_if2_adc2_mux),
1966 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1967 &rt5677_if2_adc3_mux),
1968 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1969 &rt5677_if2_adc4_mux),
1970 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
1971 &rt5677_if3_adc_mux),
1972 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
1973 &rt5677_if4_adc_mux),
1974 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
1975 &rt5677_slb_adc1_mux),
1976 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
1977 &rt5677_slb_adc2_mux),
1978 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
1979 &rt5677_slb_adc3_mux),
1980 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
1981 &rt5677_slb_adc4_mux),
1982
1983 /* Audio Interface */
1984 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1985 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1986 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1987 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1988 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1989 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1990 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
1991 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
1992 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
1993 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
1994
1995 /* Sidetone Mux */
1996 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
1997 &rt5677_sidetone_mux),
1998 /* VAD Mux*/
1999 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2000 &rt5677_vad_src_mux),
2001
2002 /* Tensilica DSP */
2003 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2004 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2005 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2006 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2007 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2008 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2009 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2010 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2011 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2012 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2013 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2014 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2015 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2016
2017 /* Output Side */
2018 /* DAC mixer before sound effect */
2019 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2020 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2021 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2022 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2023 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2024
2025 /* DAC Mux */
2026 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2027 &rt5677_dac1_mux),
2028 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2029 &rt5677_adda1_mux),
2030 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2031 &rt5677_dac12_mux),
2032 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2033 &rt5677_dac3_mux),
2034
2035 /* DAC2 channel Mux */
2036 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2037 &rt5677_dac2_l_mux),
2038 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2039 &rt5677_dac2_r_mux),
2040
2041 /* DAC3 channel Mux */
2042 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2043 &rt5677_dac3_l_mux),
2044 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2045 &rt5677_dac3_r_mux),
2046
2047 /* DAC4 channel Mux */
2048 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2049 &rt5677_dac4_l_mux),
2050 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2051 &rt5677_dac4_r_mux),
2052
2053 /* DAC Mixer */
2054 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2055 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2056 SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2,
2057 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2058 SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2,
2059 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2060
2061 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2062 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2063 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2064 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2065 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2066 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2067 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2068 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2069 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2070 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2071 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2072 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2073 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2074 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2075 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2076 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2077 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2078 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2079 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2080 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2081
2082 /* DACs */
2083 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2084 RT5677_PWR_DAC1_BIT, 0),
2085 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2086 RT5677_PWR_DAC2_BIT, 0),
2087 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2088 RT5677_PWR_DAC3_BIT, 0),
2089
2090 /* PDM */
2091 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2092 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2093 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2094 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2095
2096 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2097 1, &rt5677_pdm1_l_mux),
2098 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2099 1, &rt5677_pdm1_r_mux),
2100 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2101 1, &rt5677_pdm2_l_mux),
2102 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2103 1, &rt5677_pdm2_r_mux),
2104
2105 SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2106 0, NULL, 0),
2107 SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2108 0, NULL, 0),
2109 SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2110 0, NULL, 0),
2111
2112 /* Output Lines */
2113 SND_SOC_DAPM_OUTPUT("LOUT1"),
2114 SND_SOC_DAPM_OUTPUT("LOUT2"),
2115 SND_SOC_DAPM_OUTPUT("LOUT3"),
2116 SND_SOC_DAPM_OUTPUT("PDM1L"),
2117 SND_SOC_DAPM_OUTPUT("PDM1R"),
2118 SND_SOC_DAPM_OUTPUT("PDM2L"),
2119 SND_SOC_DAPM_OUTPUT("PDM2R"),
2120 };
2121
2122 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2123 { "DMIC1", NULL, "DMIC L1" },
2124 { "DMIC1", NULL, "DMIC R1" },
2125 { "DMIC2", NULL, "DMIC L2" },
2126 { "DMIC2", NULL, "DMIC R2" },
2127 { "DMIC3", NULL, "DMIC L3" },
2128 { "DMIC3", NULL, "DMIC R3" },
2129 { "DMIC4", NULL, "DMIC L4" },
2130 { "DMIC4", NULL, "DMIC R4" },
2131
2132 { "DMIC L1", NULL, "DMIC CLK" },
2133 { "DMIC R1", NULL, "DMIC CLK" },
2134 { "DMIC L2", NULL, "DMIC CLK" },
2135 { "DMIC R2", NULL, "DMIC CLK" },
2136 { "DMIC L3", NULL, "DMIC CLK" },
2137 { "DMIC R3", NULL, "DMIC CLK" },
2138 { "DMIC L4", NULL, "DMIC CLK" },
2139 { "DMIC R4", NULL, "DMIC CLK" },
2140
2141 { "BST1", NULL, "IN1P" },
2142 { "BST1", NULL, "IN1N" },
2143 { "BST2", NULL, "IN2P" },
2144 { "BST2", NULL, "IN2N" },
2145
2146 { "IN1P", NULL, "micbias1" },
2147 { "IN1N", NULL, "micbias1" },
2148 { "IN2P", NULL, "micbias1" },
2149 { "IN2N", NULL, "micbias1" },
2150
2151 { "ADC 1", NULL, "BST1" },
2152 { "ADC 1", NULL, "ADC 1 power" },
2153 { "ADC 1", NULL, "ADC1 clock" },
2154 { "ADC 2", NULL, "BST2" },
2155 { "ADC 2", NULL, "ADC 2 power" },
2156 { "ADC 2", NULL, "ADC2 clock" },
2157
2158 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2159 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2160 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2161 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2162
2163 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2164 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2165 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2166 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2167
2168 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2169 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2170 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2171 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2172
2173 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2174 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2175 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2176 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2177
2178 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2179 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2180 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2181 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2182
2183 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2184 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2185 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2186 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2187
2188 { "ADC 1_2", NULL, "ADC 1" },
2189 { "ADC 1_2", NULL, "ADC 2" },
2190
2191 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2192 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2193 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2194
2195 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2196 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2197 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2198
2199 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2200 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2201 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2202
2203 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2204 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2205 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2206
2207 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2208 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2209 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2210
2211 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2212 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2213 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2214
2215 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2216 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2217 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2218
2219 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2220 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2221 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
2222
2223 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
2224 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
2225 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2226
2227 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
2228 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
2229 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2230
2231 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
2232 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
2233 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2234
2235 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
2236 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
2237 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2238
2239 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2240 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2241 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2242 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2243
2244 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2245 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2246 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2247
2248 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2249 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2250 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2251
2252 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
2253 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
2254
2255 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2256 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2257 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2258 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2259
2260 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
2261 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
2262
2263 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
2264 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
2265
2266 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
2267 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
2268 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2269
2270 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
2271 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
2272 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2273
2274 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
2275 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
2276
2277 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2278 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2279 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2280 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2281
2282 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
2283 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
2284 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2285
2286 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
2287 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
2288 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2289
2290 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
2291 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
2292
2293 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2294 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2295 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2296 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2297
2298 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
2299 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
2300 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2301
2302 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
2303 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
2304 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2305
2306 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
2307 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
2308
2309 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
2310 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
2311 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2312 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2313
2314 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
2315 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
2316 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2317 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2318
2319 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
2320 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
2321
2322 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2323 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2324 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2325 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2326 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2327
2328 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2329 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2330 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2331
2332 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2333 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2334
2335 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2336 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2337 { "IF1 ADC3 Mux", "OB45", "OB45" },
2338
2339 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2340 { "IF1 ADC4 Mux", "OB67", "OB67" },
2341 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2342
2343 { "AIF1TX", NULL, "I2S1" },
2344 { "AIF1TX", NULL, "IF1 ADC1 Mux" },
2345 { "AIF1TX", NULL, "IF1 ADC2 Mux" },
2346 { "AIF1TX", NULL, "IF1 ADC3 Mux" },
2347 { "AIF1TX", NULL, "IF1 ADC4 Mux" },
2348
2349 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2350 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2351 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2352
2353 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2354 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2355
2356 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2357 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2358 { "IF2 ADC3 Mux", "OB45", "OB45" },
2359
2360 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2361 { "IF2 ADC4 Mux", "OB67", "OB67" },
2362 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2363
2364 { "AIF2TX", NULL, "I2S2" },
2365 { "AIF2TX", NULL, "IF2 ADC1 Mux" },
2366 { "AIF2TX", NULL, "IF2 ADC2 Mux" },
2367 { "AIF2TX", NULL, "IF2 ADC3 Mux" },
2368 { "AIF2TX", NULL, "IF2 ADC4 Mux" },
2369
2370 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2371 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2372 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2373 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2374 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2375 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
2376 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
2377 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2378
2379 { "AIF3TX", NULL, "I2S3" },
2380 { "AIF3TX", NULL, "IF3 ADC Mux" },
2381
2382 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2383 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2384 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2385 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2386 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2387 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
2388 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
2389 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2390
2391 { "AIF4TX", NULL, "I2S4" },
2392 { "AIF4TX", NULL, "IF4 ADC Mux" },
2393
2394 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2395 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2396 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2397
2398 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2399 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2400
2401 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2402 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2403 { "SLB ADC3 Mux", "OB45", "OB45" },
2404
2405 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2406 { "SLB ADC4 Mux", "OB67", "OB67" },
2407 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2408
2409 { "SLBTX", NULL, "SLB" },
2410 { "SLBTX", NULL, "SLB ADC1 Mux" },
2411 { "SLBTX", NULL, "SLB ADC2 Mux" },
2412 { "SLBTX", NULL, "SLB ADC3 Mux" },
2413 { "SLBTX", NULL, "SLB ADC4 Mux" },
2414
2415 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
2416 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
2417 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
2418 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2419 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
2420
2421 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
2422 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
2423
2424 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
2425 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
2426 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
2427 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2428 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
2429 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
2430
2431 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
2432 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
2433
2434 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
2435 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
2436 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
2437 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2438 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
2439
2440 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
2441 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
2442
2443 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
2444 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
2445 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
2446 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2447 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
2448 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2449 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2450 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2451
2452 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
2453 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
2454 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
2455 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2456 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
2457 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2458 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2459 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2460
2461 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2462 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2463 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2464 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2465 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2466 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
2467
2468 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2469 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2470 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2471 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2472 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2473 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
2474 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
2475
2476 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2477 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2478 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2479 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
2480 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
2481 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
2482 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
2483
2484 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2485 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2486 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2487 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
2488 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
2489 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
2490 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
2491
2492 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2493 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2494 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2495 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
2496 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
2497 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
2498 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
2499
2500 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2501 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2502 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2503 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
2504 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
2505 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
2506 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
2507
2508 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2509 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2510 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2511 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
2512 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
2513 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
2514 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
2515
2516 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2517 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2518 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2519 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
2520 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
2521 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
2522 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
2523
2524 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
2525 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
2526 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
2527 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
2528
2529 { "OutBound2", NULL, "OB23 Bypass Mux" },
2530 { "OutBound3", NULL, "OB23 Bypass Mux" },
2531 { "OutBound4", NULL, "OB4 MIX" },
2532 { "OutBound5", NULL, "OB5 MIX" },
2533 { "OutBound6", NULL, "OB6 MIX" },
2534 { "OutBound7", NULL, "OB7 MIX" },
2535
2536 { "OB45", NULL, "OutBound4" },
2537 { "OB45", NULL, "OutBound5" },
2538 { "OB67", NULL, "OutBound6" },
2539 { "OB67", NULL, "OutBound7" },
2540
2541 { "IF1 DAC0", NULL, "AIF1RX" },
2542 { "IF1 DAC1", NULL, "AIF1RX" },
2543 { "IF1 DAC2", NULL, "AIF1RX" },
2544 { "IF1 DAC3", NULL, "AIF1RX" },
2545 { "IF1 DAC4", NULL, "AIF1RX" },
2546 { "IF1 DAC5", NULL, "AIF1RX" },
2547 { "IF1 DAC6", NULL, "AIF1RX" },
2548 { "IF1 DAC7", NULL, "AIF1RX" },
2549 { "IF1 DAC0", NULL, "I2S1" },
2550 { "IF1 DAC1", NULL, "I2S1" },
2551 { "IF1 DAC2", NULL, "I2S1" },
2552 { "IF1 DAC3", NULL, "I2S1" },
2553 { "IF1 DAC4", NULL, "I2S1" },
2554 { "IF1 DAC5", NULL, "I2S1" },
2555 { "IF1 DAC6", NULL, "I2S1" },
2556 { "IF1 DAC7", NULL, "I2S1" },
2557
2558 { "IF1 DAC01", NULL, "IF1 DAC0" },
2559 { "IF1 DAC01", NULL, "IF1 DAC1" },
2560 { "IF1 DAC23", NULL, "IF1 DAC2" },
2561 { "IF1 DAC23", NULL, "IF1 DAC3" },
2562 { "IF1 DAC45", NULL, "IF1 DAC4" },
2563 { "IF1 DAC45", NULL, "IF1 DAC5" },
2564 { "IF1 DAC67", NULL, "IF1 DAC6" },
2565 { "IF1 DAC67", NULL, "IF1 DAC7" },
2566
2567 { "IF2 DAC0", NULL, "AIF2RX" },
2568 { "IF2 DAC1", NULL, "AIF2RX" },
2569 { "IF2 DAC2", NULL, "AIF2RX" },
2570 { "IF2 DAC3", NULL, "AIF2RX" },
2571 { "IF2 DAC4", NULL, "AIF2RX" },
2572 { "IF2 DAC5", NULL, "AIF2RX" },
2573 { "IF2 DAC6", NULL, "AIF2RX" },
2574 { "IF2 DAC7", NULL, "AIF2RX" },
2575 { "IF2 DAC0", NULL, "I2S2" },
2576 { "IF2 DAC1", NULL, "I2S2" },
2577 { "IF2 DAC2", NULL, "I2S2" },
2578 { "IF2 DAC3", NULL, "I2S2" },
2579 { "IF2 DAC4", NULL, "I2S2" },
2580 { "IF2 DAC5", NULL, "I2S2" },
2581 { "IF2 DAC6", NULL, "I2S2" },
2582 { "IF2 DAC7", NULL, "I2S2" },
2583
2584 { "IF2 DAC01", NULL, "IF2 DAC0" },
2585 { "IF2 DAC01", NULL, "IF2 DAC1" },
2586 { "IF2 DAC23", NULL, "IF2 DAC2" },
2587 { "IF2 DAC23", NULL, "IF2 DAC3" },
2588 { "IF2 DAC45", NULL, "IF2 DAC4" },
2589 { "IF2 DAC45", NULL, "IF2 DAC5" },
2590 { "IF2 DAC67", NULL, "IF2 DAC6" },
2591 { "IF2 DAC67", NULL, "IF2 DAC7" },
2592
2593 { "IF3 DAC", NULL, "AIF3RX" },
2594 { "IF3 DAC", NULL, "I2S3" },
2595
2596 { "IF4 DAC", NULL, "AIF4RX" },
2597 { "IF4 DAC", NULL, "I2S4" },
2598
2599 { "IF3 DAC L", NULL, "IF3 DAC" },
2600 { "IF3 DAC R", NULL, "IF3 DAC" },
2601
2602 { "IF4 DAC L", NULL, "IF4 DAC" },
2603 { "IF4 DAC R", NULL, "IF4 DAC" },
2604
2605 { "SLB DAC0", NULL, "SLBRX" },
2606 { "SLB DAC1", NULL, "SLBRX" },
2607 { "SLB DAC2", NULL, "SLBRX" },
2608 { "SLB DAC3", NULL, "SLBRX" },
2609 { "SLB DAC4", NULL, "SLBRX" },
2610 { "SLB DAC5", NULL, "SLBRX" },
2611 { "SLB DAC6", NULL, "SLBRX" },
2612 { "SLB DAC7", NULL, "SLBRX" },
2613 { "SLB DAC0", NULL, "SLB" },
2614 { "SLB DAC1", NULL, "SLB" },
2615 { "SLB DAC2", NULL, "SLB" },
2616 { "SLB DAC3", NULL, "SLB" },
2617 { "SLB DAC4", NULL, "SLB" },
2618 { "SLB DAC5", NULL, "SLB" },
2619 { "SLB DAC6", NULL, "SLB" },
2620 { "SLB DAC7", NULL, "SLB" },
2621
2622 { "SLB DAC01", NULL, "SLB DAC0" },
2623 { "SLB DAC01", NULL, "SLB DAC1" },
2624 { "SLB DAC23", NULL, "SLB DAC2" },
2625 { "SLB DAC23", NULL, "SLB DAC3" },
2626 { "SLB DAC45", NULL, "SLB DAC4" },
2627 { "SLB DAC45", NULL, "SLB DAC5" },
2628 { "SLB DAC67", NULL, "SLB DAC6" },
2629 { "SLB DAC67", NULL, "SLB DAC7" },
2630
2631 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2632 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2633 { "ADDA1 Mux", "OB 67", "OB67" },
2634
2635 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
2636 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
2637 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
2638 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
2639 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
2640 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
2641
2642 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
2643 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
2644 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2645 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
2646 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
2647 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2648
2649 { "DAC1 FS", NULL, "DAC1 MIXL" },
2650 { "DAC1 FS", NULL, "DAC1 MIXR" },
2651
2652 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
2653 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
2654 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
2655 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
2656 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
2657 { "DAC2 L Mux", "OB 2", "OutBound2" },
2658
2659 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
2660 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
2661 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
2662 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
2663 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
2664 { "DAC2 R Mux", "OB 3", "OutBound3" },
2665 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
2666 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
2667
2668 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
2669 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
2670 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
2671 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
2672 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
2673 { "DAC3 L Mux", "OB 4", "OutBound4" },
2674
2675 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
2676 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
2677 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
2678 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
2679 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
2680 { "DAC3 R Mux", "OB 5", "OutBound5" },
2681
2682 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
2683 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
2684 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
2685 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
2686 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
2687 { "DAC4 L Mux", "OB 6", "OutBound6" },
2688
2689 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
2690 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
2691 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
2692 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
2693 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
2694 { "DAC4 R Mux", "OB 7", "OutBound7" },
2695
2696 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
2697 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
2698 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
2699 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
2700 { "Sidetone Mux", "ADC1", "ADC 1" },
2701 { "Sidetone Mux", "ADC2", "ADC 2" },
2702
2703 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
2704 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2705 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2706 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
2707 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2708 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
2709 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2710 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2711 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
2712 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2713
2714 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
2715 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2716 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2717 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
2718 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2719 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
2720 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2721 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2722 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
2723 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2724
2725 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2726 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2727 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
2728 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
2729 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2730 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2731 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
2732 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
2733
2734 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2735 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2736 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
2737 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
2738 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2739 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2740 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
2741 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
2742
2743 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
2744 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
2745 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
2746 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
2747 { "DD1 MIX", NULL, "DD1 MIXL" },
2748 { "DD1 MIX", NULL, "DD1 MIXR" },
2749 { "DD2 MIX", NULL, "DD2 MIXL" },
2750 { "DD2 MIX", NULL, "DD2 MIXR" },
2751
2752 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
2753 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
2754 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
2755 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
2756
2757 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2758 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2759 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
2760 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
2761
2762 { "DAC 1", NULL, "DAC12 SRC Mux" },
2763 { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll },
2764 { "DAC 2", NULL, "DAC12 SRC Mux" },
2765 { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll },
2766 { "DAC 3", NULL, "DAC3 SRC Mux" },
2767 { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll },
2768
2769 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2770 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2771 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
2772 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
2773 { "PDM1 L Mux", NULL, "PDM1 Power" },
2774 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2775 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2776 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
2777 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
2778 { "PDM1 R Mux", NULL, "PDM1 Power" },
2779 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2780 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2781 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
2782 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
2783 { "PDM2 L Mux", NULL, "PDM2 Power" },
2784 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2785 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2786 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
2787 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
2788 { "PDM2 R Mux", NULL, "PDM2 Power" },
2789
2790 { "LOUT1 amp", NULL, "DAC 1" },
2791 { "LOUT2 amp", NULL, "DAC 2" },
2792 { "LOUT3 amp", NULL, "DAC 3" },
2793
2794 { "LOUT1", NULL, "LOUT1 amp" },
2795 { "LOUT2", NULL, "LOUT2 amp" },
2796 { "LOUT3", NULL, "LOUT3 amp" },
2797
2798 { "PDM1L", NULL, "PDM1 L Mux" },
2799 { "PDM1R", NULL, "PDM1 R Mux" },
2800 { "PDM2L", NULL, "PDM2 L Mux" },
2801 { "PDM2R", NULL, "PDM2 R Mux" },
2802 };
2803
2804 static int get_clk_info(int sclk, int rate)
2805 {
2806 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
2807
2808 if (sclk <= 0 || rate <= 0)
2809 return -EINVAL;
2810
2811 rate = rate << 8;
2812 for (i = 0; i < ARRAY_SIZE(pd); i++)
2813 if (sclk == rate * pd[i])
2814 return i;
2815
2816 return -EINVAL;
2817 }
2818
2819 static int rt5677_hw_params(struct snd_pcm_substream *substream,
2820 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2821 {
2822 struct snd_soc_codec *codec = dai->codec;
2823 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2824 unsigned int val_len = 0, val_clk, mask_clk;
2825 int pre_div, bclk_ms, frame_size;
2826
2827 rt5677->lrck[dai->id] = params_rate(params);
2828 pre_div = get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
2829 if (pre_div < 0) {
2830 dev_err(codec->dev, "Unsupported clock setting\n");
2831 return -EINVAL;
2832 }
2833 frame_size = snd_soc_params_to_frame_size(params);
2834 if (frame_size < 0) {
2835 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2836 return -EINVAL;
2837 }
2838 bclk_ms = frame_size > 32;
2839 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
2840
2841 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2842 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
2843 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2844 bclk_ms, pre_div, dai->id);
2845
2846 switch (params_width(params)) {
2847 case 16:
2848 break;
2849 case 20:
2850 val_len |= RT5677_I2S_DL_20;
2851 break;
2852 case 24:
2853 val_len |= RT5677_I2S_DL_24;
2854 break;
2855 case 8:
2856 val_len |= RT5677_I2S_DL_8;
2857 break;
2858 default:
2859 return -EINVAL;
2860 }
2861
2862 switch (dai->id) {
2863 case RT5677_AIF1:
2864 mask_clk = RT5677_I2S_PD1_MASK;
2865 val_clk = pre_div << RT5677_I2S_PD1_SFT;
2866 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2867 RT5677_I2S_DL_MASK, val_len);
2868 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2869 mask_clk, val_clk);
2870 break;
2871 case RT5677_AIF2:
2872 mask_clk = RT5677_I2S_PD2_MASK;
2873 val_clk = pre_div << RT5677_I2S_PD2_SFT;
2874 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2875 RT5677_I2S_DL_MASK, val_len);
2876 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2877 mask_clk, val_clk);
2878 break;
2879 case RT5677_AIF3:
2880 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
2881 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
2882 pre_div << RT5677_I2S_PD3_SFT;
2883 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2884 RT5677_I2S_DL_MASK, val_len);
2885 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2886 mask_clk, val_clk);
2887 break;
2888 case RT5677_AIF4:
2889 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
2890 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
2891 pre_div << RT5677_I2S_PD4_SFT;
2892 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2893 RT5677_I2S_DL_MASK, val_len);
2894 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2895 mask_clk, val_clk);
2896 break;
2897 default:
2898 break;
2899 }
2900
2901 return 0;
2902 }
2903
2904 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2905 {
2906 struct snd_soc_codec *codec = dai->codec;
2907 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2908 unsigned int reg_val = 0;
2909
2910 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2911 case SND_SOC_DAIFMT_CBM_CFM:
2912 rt5677->master[dai->id] = 1;
2913 break;
2914 case SND_SOC_DAIFMT_CBS_CFS:
2915 reg_val |= RT5677_I2S_MS_S;
2916 rt5677->master[dai->id] = 0;
2917 break;
2918 default:
2919 return -EINVAL;
2920 }
2921
2922 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2923 case SND_SOC_DAIFMT_NB_NF:
2924 break;
2925 case SND_SOC_DAIFMT_IB_NF:
2926 reg_val |= RT5677_I2S_BP_INV;
2927 break;
2928 default:
2929 return -EINVAL;
2930 }
2931
2932 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2933 case SND_SOC_DAIFMT_I2S:
2934 break;
2935 case SND_SOC_DAIFMT_LEFT_J:
2936 reg_val |= RT5677_I2S_DF_LEFT;
2937 break;
2938 case SND_SOC_DAIFMT_DSP_A:
2939 reg_val |= RT5677_I2S_DF_PCM_A;
2940 break;
2941 case SND_SOC_DAIFMT_DSP_B:
2942 reg_val |= RT5677_I2S_DF_PCM_B;
2943 break;
2944 default:
2945 return -EINVAL;
2946 }
2947
2948 switch (dai->id) {
2949 case RT5677_AIF1:
2950 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2951 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2952 RT5677_I2S_DF_MASK, reg_val);
2953 break;
2954 case RT5677_AIF2:
2955 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2956 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2957 RT5677_I2S_DF_MASK, reg_val);
2958 break;
2959 case RT5677_AIF3:
2960 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2961 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2962 RT5677_I2S_DF_MASK, reg_val);
2963 break;
2964 case RT5677_AIF4:
2965 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2966 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2967 RT5677_I2S_DF_MASK, reg_val);
2968 break;
2969 default:
2970 break;
2971 }
2972
2973
2974 return 0;
2975 }
2976
2977 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
2978 int clk_id, unsigned int freq, int dir)
2979 {
2980 struct snd_soc_codec *codec = dai->codec;
2981 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2982 unsigned int reg_val = 0;
2983
2984 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
2985 return 0;
2986
2987 switch (clk_id) {
2988 case RT5677_SCLK_S_MCLK:
2989 reg_val |= RT5677_SCLK_SRC_MCLK;
2990 break;
2991 case RT5677_SCLK_S_PLL1:
2992 reg_val |= RT5677_SCLK_SRC_PLL1;
2993 break;
2994 case RT5677_SCLK_S_RCCLK:
2995 reg_val |= RT5677_SCLK_SRC_RCCLK;
2996 break;
2997 default:
2998 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2999 return -EINVAL;
3000 }
3001 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3002 RT5677_SCLK_SRC_MASK, reg_val);
3003 rt5677->sysclk = freq;
3004 rt5677->sysclk_src = clk_id;
3005
3006 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3007
3008 return 0;
3009 }
3010
3011 /**
3012 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3013 * @freq_in: external clock provided to codec.
3014 * @freq_out: target clock which codec works on.
3015 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
3016 *
3017 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
3018 *
3019 * Returns 0 for success or negative error code.
3020 */
3021 static int rt5677_pll_calc(const unsigned int freq_in,
3022 const unsigned int freq_out, struct rt5677_pll_code *pll_code)
3023 {
3024 int max_n = RT5677_PLL_N_MAX, max_m = RT5677_PLL_M_MAX;
3025 int k, red, n_t, pll_out, in_t;
3026 int n = 0, m = 0, m_t = 0;
3027 int out_t, red_t = abs(freq_out - freq_in);
3028 bool m_bp = false, k_bp = false;
3029
3030 if (RT5677_PLL_INP_MAX < freq_in || RT5677_PLL_INP_MIN > freq_in)
3031 return -EINVAL;
3032
3033 k = 100000000 / freq_out - 2;
3034 if (k > RT5677_PLL_K_MAX)
3035 k = RT5677_PLL_K_MAX;
3036 for (n_t = 0; n_t <= max_n; n_t++) {
3037 in_t = freq_in / (k + 2);
3038 pll_out = freq_out / (n_t + 2);
3039 if (in_t < 0)
3040 continue;
3041 if (in_t == pll_out) {
3042 m_bp = true;
3043 n = n_t;
3044 goto code_find;
3045 }
3046 red = abs(in_t - pll_out);
3047 if (red < red_t) {
3048 m_bp = true;
3049 n = n_t;
3050 m = m_t;
3051 if (red == 0)
3052 goto code_find;
3053 red_t = red;
3054 }
3055 for (m_t = 0; m_t <= max_m; m_t++) {
3056 out_t = in_t / (m_t + 2);
3057 red = abs(out_t - pll_out);
3058 if (red < red_t) {
3059 m_bp = false;
3060 n = n_t;
3061 m = m_t;
3062 if (red == 0)
3063 goto code_find;
3064 red_t = red;
3065 }
3066 }
3067 }
3068 pr_debug("Only get approximation about PLL\n");
3069
3070 code_find:
3071
3072 pll_code->m_bp = m_bp;
3073 pll_code->k_bp = k_bp;
3074 pll_code->m_code = m;
3075 pll_code->n_code = n;
3076 pll_code->k_code = k;
3077 return 0;
3078 }
3079
3080 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3081 unsigned int freq_in, unsigned int freq_out)
3082 {
3083 struct snd_soc_codec *codec = dai->codec;
3084 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3085 struct rt5677_pll_code pll_code;
3086 int ret;
3087
3088 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
3089 freq_out == rt5677->pll_out)
3090 return 0;
3091
3092 if (!freq_in || !freq_out) {
3093 dev_dbg(codec->dev, "PLL disabled\n");
3094
3095 rt5677->pll_in = 0;
3096 rt5677->pll_out = 0;
3097 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3098 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
3099 return 0;
3100 }
3101
3102 switch (source) {
3103 case RT5677_PLL1_S_MCLK:
3104 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3105 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
3106 break;
3107 case RT5677_PLL1_S_BCLK1:
3108 case RT5677_PLL1_S_BCLK2:
3109 case RT5677_PLL1_S_BCLK3:
3110 case RT5677_PLL1_S_BCLK4:
3111 switch (dai->id) {
3112 case RT5677_AIF1:
3113 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3114 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
3115 break;
3116 case RT5677_AIF2:
3117 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3118 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
3119 break;
3120 case RT5677_AIF3:
3121 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3122 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
3123 break;
3124 case RT5677_AIF4:
3125 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3126 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
3127 break;
3128 default:
3129 break;
3130 }
3131 break;
3132 default:
3133 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3134 return -EINVAL;
3135 }
3136
3137 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
3138 if (ret < 0) {
3139 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3140 return ret;
3141 }
3142
3143 dev_dbg(codec->dev, "m_bypass=%d k_bypass=%d m=%d n=%d k=%d\n",
3144 pll_code.m_bp, pll_code.k_bp,
3145 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
3146 (pll_code.k_bp ? 0 : pll_code.k_code));
3147
3148 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
3149 pll_code.n_code << RT5677_PLL_N_SFT |
3150 pll_code.k_bp << RT5677_PLL_K_BP_SFT |
3151 (pll_code.k_bp ? 0 : pll_code.k_code));
3152 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
3153 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
3154 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
3155
3156 rt5677->pll_in = freq_in;
3157 rt5677->pll_out = freq_out;
3158 rt5677->pll_src = source;
3159
3160 return 0;
3161 }
3162
3163 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3164 enum snd_soc_bias_level level)
3165 {
3166 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3167
3168 switch (level) {
3169 case SND_SOC_BIAS_ON:
3170 break;
3171
3172 case SND_SOC_BIAS_PREPARE:
3173 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
3174 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3175 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
3176 0x0055);
3177 regmap_update_bits(rt5677->regmap,
3178 RT5677_PR_BASE + RT5677_BIAS_CUR4,
3179 0x0f00, 0x0f00);
3180 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3181 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3182 RT5677_PWR_BG | RT5677_PWR_VREF2,
3183 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3184 RT5677_PWR_BG | RT5677_PWR_VREF2);
3185 mdelay(20);
3186 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3187 RT5677_PWR_FV1 | RT5677_PWR_FV2,
3188 RT5677_PWR_FV1 | RT5677_PWR_FV2);
3189 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
3190 RT5677_PWR_CORE, RT5677_PWR_CORE);
3191 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
3192 0x1, 0x1);
3193 }
3194 break;
3195
3196 case SND_SOC_BIAS_STANDBY:
3197 break;
3198
3199 case SND_SOC_BIAS_OFF:
3200 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
3201 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
3202 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
3203 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0000);
3204 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
3205 regmap_update_bits(rt5677->regmap,
3206 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
3207 break;
3208
3209 default:
3210 break;
3211 }
3212 codec->dapm.bias_level = level;
3213
3214 return 0;
3215 }
3216
3217 static int rt5677_probe(struct snd_soc_codec *codec)
3218 {
3219 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3220
3221 rt5677->codec = codec;
3222
3223 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
3224
3225 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
3226 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
3227
3228 return 0;
3229 }
3230
3231 static int rt5677_remove(struct snd_soc_codec *codec)
3232 {
3233 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3234
3235 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3236
3237 return 0;
3238 }
3239
3240 #ifdef CONFIG_PM
3241 static int rt5677_suspend(struct snd_soc_codec *codec)
3242 {
3243 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3244
3245 regcache_cache_only(rt5677->regmap, true);
3246 regcache_mark_dirty(rt5677->regmap);
3247
3248 return 0;
3249 }
3250
3251 static int rt5677_resume(struct snd_soc_codec *codec)
3252 {
3253 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3254
3255 regcache_cache_only(rt5677->regmap, false);
3256 regcache_sync(rt5677->regmap);
3257
3258 return 0;
3259 }
3260 #else
3261 #define rt5677_suspend NULL
3262 #define rt5677_resume NULL
3263 #endif
3264
3265 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3266 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3267 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3268
3269 static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
3270 .hw_params = rt5677_hw_params,
3271 .set_fmt = rt5677_set_dai_fmt,
3272 .set_sysclk = rt5677_set_dai_sysclk,
3273 .set_pll = rt5677_set_dai_pll,
3274 };
3275
3276 static struct snd_soc_dai_driver rt5677_dai[] = {
3277 {
3278 .name = "rt5677-aif1",
3279 .id = RT5677_AIF1,
3280 .playback = {
3281 .stream_name = "AIF1 Playback",
3282 .channels_min = 1,
3283 .channels_max = 2,
3284 .rates = RT5677_STEREO_RATES,
3285 .formats = RT5677_FORMATS,
3286 },
3287 .capture = {
3288 .stream_name = "AIF1 Capture",
3289 .channels_min = 1,
3290 .channels_max = 2,
3291 .rates = RT5677_STEREO_RATES,
3292 .formats = RT5677_FORMATS,
3293 },
3294 .ops = &rt5677_aif_dai_ops,
3295 },
3296 {
3297 .name = "rt5677-aif2",
3298 .id = RT5677_AIF2,
3299 .playback = {
3300 .stream_name = "AIF2 Playback",
3301 .channels_min = 1,
3302 .channels_max = 2,
3303 .rates = RT5677_STEREO_RATES,
3304 .formats = RT5677_FORMATS,
3305 },
3306 .capture = {
3307 .stream_name = "AIF2 Capture",
3308 .channels_min = 1,
3309 .channels_max = 2,
3310 .rates = RT5677_STEREO_RATES,
3311 .formats = RT5677_FORMATS,
3312 },
3313 .ops = &rt5677_aif_dai_ops,
3314 },
3315 {
3316 .name = "rt5677-aif3",
3317 .id = RT5677_AIF3,
3318 .playback = {
3319 .stream_name = "AIF3 Playback",
3320 .channels_min = 1,
3321 .channels_max = 2,
3322 .rates = RT5677_STEREO_RATES,
3323 .formats = RT5677_FORMATS,
3324 },
3325 .capture = {
3326 .stream_name = "AIF3 Capture",
3327 .channels_min = 1,
3328 .channels_max = 2,
3329 .rates = RT5677_STEREO_RATES,
3330 .formats = RT5677_FORMATS,
3331 },
3332 .ops = &rt5677_aif_dai_ops,
3333 },
3334 {
3335 .name = "rt5677-aif4",
3336 .id = RT5677_AIF4,
3337 .playback = {
3338 .stream_name = "AIF4 Playback",
3339 .channels_min = 1,
3340 .channels_max = 2,
3341 .rates = RT5677_STEREO_RATES,
3342 .formats = RT5677_FORMATS,
3343 },
3344 .capture = {
3345 .stream_name = "AIF4 Capture",
3346 .channels_min = 1,
3347 .channels_max = 2,
3348 .rates = RT5677_STEREO_RATES,
3349 .formats = RT5677_FORMATS,
3350 },
3351 .ops = &rt5677_aif_dai_ops,
3352 },
3353 {
3354 .name = "rt5677-slimbus",
3355 .id = RT5677_AIF5,
3356 .playback = {
3357 .stream_name = "SLIMBus Playback",
3358 .channels_min = 1,
3359 .channels_max = 2,
3360 .rates = RT5677_STEREO_RATES,
3361 .formats = RT5677_FORMATS,
3362 },
3363 .capture = {
3364 .stream_name = "SLIMBus Capture",
3365 .channels_min = 1,
3366 .channels_max = 2,
3367 .rates = RT5677_STEREO_RATES,
3368 .formats = RT5677_FORMATS,
3369 },
3370 .ops = &rt5677_aif_dai_ops,
3371 },
3372 };
3373
3374 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
3375 .probe = rt5677_probe,
3376 .remove = rt5677_remove,
3377 .suspend = rt5677_suspend,
3378 .resume = rt5677_resume,
3379 .set_bias_level = rt5677_set_bias_level,
3380 .idle_bias_off = true,
3381 .controls = rt5677_snd_controls,
3382 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
3383 .dapm_widgets = rt5677_dapm_widgets,
3384 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
3385 .dapm_routes = rt5677_dapm_routes,
3386 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
3387 };
3388
3389 static const struct regmap_config rt5677_regmap = {
3390 .reg_bits = 8,
3391 .val_bits = 16,
3392
3393 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
3394 RT5677_PR_SPACING),
3395
3396 .volatile_reg = rt5677_volatile_register,
3397 .readable_reg = rt5677_readable_register,
3398
3399 .cache_type = REGCACHE_RBTREE,
3400 .reg_defaults = rt5677_reg,
3401 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
3402 .ranges = rt5677_ranges,
3403 .num_ranges = ARRAY_SIZE(rt5677_ranges),
3404 };
3405
3406 static const struct i2c_device_id rt5677_i2c_id[] = {
3407 { "rt5677", 0 },
3408 { }
3409 };
3410 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
3411
3412 static int rt5677_i2c_probe(struct i2c_client *i2c,
3413 const struct i2c_device_id *id)
3414 {
3415 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
3416 struct rt5677_priv *rt5677;
3417 int ret;
3418 unsigned int val;
3419
3420 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
3421 GFP_KERNEL);
3422 if (rt5677 == NULL)
3423 return -ENOMEM;
3424
3425 i2c_set_clientdata(i2c, rt5677);
3426
3427 if (pdata)
3428 rt5677->pdata = *pdata;
3429
3430 rt5677->regmap = devm_regmap_init_i2c(i2c, &rt5677_regmap);
3431 if (IS_ERR(rt5677->regmap)) {
3432 ret = PTR_ERR(rt5677->regmap);
3433 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3434 ret);
3435 return ret;
3436 }
3437
3438 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
3439 if (val != RT5677_DEVICE_ID) {
3440 dev_err(&i2c->dev,
3441 "Device with ID register %x is not rt5677\n", val);
3442 return -ENODEV;
3443 }
3444
3445 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3446
3447 ret = regmap_register_patch(rt5677->regmap, init_list,
3448 ARRAY_SIZE(init_list));
3449 if (ret != 0)
3450 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3451
3452 if (rt5677->pdata.in1_diff)
3453 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3454 RT5677_IN_DF1, RT5677_IN_DF1);
3455
3456 if (rt5677->pdata.in2_diff)
3457 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3458 RT5677_IN_DF2, RT5677_IN_DF2);
3459
3460 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
3461 rt5677_dai, ARRAY_SIZE(rt5677_dai));
3462 if (ret < 0)
3463 goto err;
3464
3465 return 0;
3466 err:
3467 return ret;
3468 }
3469
3470 static int rt5677_i2c_remove(struct i2c_client *i2c)
3471 {
3472 snd_soc_unregister_codec(&i2c->dev);
3473
3474 return 0;
3475 }
3476
3477 static struct i2c_driver rt5677_i2c_driver = {
3478 .driver = {
3479 .name = "rt5677",
3480 .owner = THIS_MODULE,
3481 },
3482 .probe = rt5677_i2c_probe,
3483 .remove = rt5677_i2c_remove,
3484 .id_table = rt5677_i2c_id,
3485 };
3486
3487 static int __init rt5677_modinit(void)
3488 {
3489 return i2c_add_driver(&rt5677_i2c_driver);
3490 }
3491 module_init(rt5677_modinit);
3492
3493 static void __exit rt5677_modexit(void)
3494 {
3495 i2c_del_driver(&rt5677_i2c_driver);
3496 }
3497 module_exit(rt5677_modexit);
3498
3499 MODULE_DESCRIPTION("ASoC RT5677 driver");
3500 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
3501 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support