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jme: Fix device PM wakeup API usage
[linux/fpc-iii.git] / sound / soc / codecs / tlv320aic3x.c
blob80d2722392ff9c73496a8c9760b0a14c79cb36c7
1 /*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33, aic3007.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
33 */
34
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/of.h>
44 #include <linux/of_gpio.h>
45 #include <linux/slab.h>
46 #include <sound/core.h>
47 #include <sound/pcm.h>
48 #include <sound/pcm_params.h>
49 #include <sound/soc.h>
50 #include <sound/initval.h>
51 #include <sound/tlv.h>
52 #include <sound/tlv320aic3x.h>
53
54 #include "tlv320aic3x.h"
55
56 #define AIC3X_NUM_SUPPLIES 4
57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62 };
63
64 static LIST_HEAD(reset_list);
65
66 struct aic3x_priv;
67
68 struct aic3x_disable_nb {
69 struct notifier_block nb;
70 struct aic3x_priv *aic3x;
71 };
72
73 /* codec private data */
74 struct aic3x_priv {
75 struct snd_soc_codec *codec;
76 struct regmap *regmap;
77 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
78 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
79 struct aic3x_setup_data *setup;
80 unsigned int sysclk;
81 struct list_head list;
82 int master;
83 int gpio_reset;
84 int power;
85 #define AIC3X_MODEL_3X 0
86 #define AIC3X_MODEL_33 1
87 #define AIC3X_MODEL_3007 2
88 u16 model;
89
90 /* Selects the micbias voltage */
91 enum aic3x_micbias_voltage micbias_vg;
92 };
93
94 static const struct reg_default aic3x_reg[] = {
95 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 },
96 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
97 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 },
98 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 },
99 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 },
100 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 },
101 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe },
102 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 },
103 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 },
104 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 },
105 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 },
106 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
107 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 },
108 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 },
109 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 },
110 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 },
111 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 },
112 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
113 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
114 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
115 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 },
116 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
117 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
118 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
119 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
120 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
121 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
122 { 108, 0x00 }, { 109, 0x00 },
123 };
124
125 static const struct regmap_config aic3x_regmap = {
126 .reg_bits = 8,
127 .val_bits = 8,
128
129 .max_register = DAC_ICC_ADJ,
130 .reg_defaults = aic3x_reg,
131 .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
132 .cache_type = REGCACHE_RBTREE,
133 };
134
135 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
136 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
137 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
138
139 /*
140 * All input lines are connected when !0xf and disconnected with 0xf bit field,
141 * so we have to use specific dapm_put call for input mixer
142 */
143 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
144 struct snd_ctl_elem_value *ucontrol)
145 {
146 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
147 struct soc_mixer_control *mc =
148 (struct soc_mixer_control *)kcontrol->private_value;
149 unsigned int reg = mc->reg;
150 unsigned int shift = mc->shift;
151 int max = mc->max;
152 unsigned int mask = (1 << fls(max)) - 1;
153 unsigned int invert = mc->invert;
154 unsigned short val;
155 struct snd_soc_dapm_update update;
156 int connect, change;
157
158 val = (ucontrol->value.integer.value[0] & mask);
159
160 mask = 0xf;
161 if (val)
162 val = mask;
163
164 connect = !!val;
165
166 if (invert)
167 val = mask - val;
168
169 mask <<= shift;
170 val <<= shift;
171
172 change = snd_soc_test_bits(codec, reg, mask, val);
173 if (change) {
174 update.kcontrol = kcontrol;
175 update.reg = reg;
176 update.mask = mask;
177 update.val = val;
178
179 snd_soc_dapm_mixer_update_power(&codec->dapm, kcontrol, connect,
180 &update);
181 }
182
183 return change;
184 }
185
186 /*
187 * mic bias power on/off share the same register bits with
188 * output voltage of mic bias. when power on mic bias, we
189 * need reclaim it to voltage value.
190 * 0x0 = Powered off
191 * 0x1 = MICBIAS output is powered to 2.0V,
192 * 0x2 = MICBIAS output is powered to 2.5V
193 * 0x3 = MICBIAS output is connected to AVDD
194 */
195 static int mic_bias_event(struct snd_soc_dapm_widget *w,
196 struct snd_kcontrol *kcontrol, int event)
197 {
198 struct snd_soc_codec *codec = w->codec;
199 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
200
201 switch (event) {
202 case SND_SOC_DAPM_POST_PMU:
203 /* change mic bias voltage to user defined */
204 snd_soc_update_bits(codec, MICBIAS_CTRL,
205 MICBIAS_LEVEL_MASK,
206 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
207 break;
208
209 case SND_SOC_DAPM_PRE_PMD:
210 snd_soc_update_bits(codec, MICBIAS_CTRL,
211 MICBIAS_LEVEL_MASK, 0);
212 break;
213 }
214 return 0;
215 }
216
217 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
218 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
219 static const char *aic3x_left_hpcom_mux[] =
220 { "differential of HPLOUT", "constant VCM", "single-ended" };
221 static const char *aic3x_right_hpcom_mux[] =
222 { "differential of HPROUT", "constant VCM", "single-ended",
223 "differential of HPLCOM", "external feedback" };
224 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
225 static const char *aic3x_adc_hpf[] =
226 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
227
228 #define LDAC_ENUM 0
229 #define RDAC_ENUM 1
230 #define LHPCOM_ENUM 2
231 #define RHPCOM_ENUM 3
232 #define LINE1L_2_L_ENUM 4
233 #define LINE1L_2_R_ENUM 5
234 #define LINE1R_2_L_ENUM 6
235 #define LINE1R_2_R_ENUM 7
236 #define LINE2L_ENUM 8
237 #define LINE2R_ENUM 9
238 #define ADC_HPF_ENUM 10
239
240 static const struct soc_enum aic3x_enum[] = {
241 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
242 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
243 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
244 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
245 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
246 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
247 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
248 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
249 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
250 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
251 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
252 };
253
254 static const char *aic3x_agc_level[] =
255 { "-5.5dB", "-8dB", "-10dB", "-12dB", "-14dB", "-17dB", "-20dB", "-24dB" };
256 static const struct soc_enum aic3x_agc_level_enum[] = {
257 SOC_ENUM_SINGLE(LAGC_CTRL_A, 4, 8, aic3x_agc_level),
258 SOC_ENUM_SINGLE(RAGC_CTRL_A, 4, 8, aic3x_agc_level),
259 };
260
261 static const char *aic3x_agc_attack[] = { "8ms", "11ms", "16ms", "20ms" };
262 static const struct soc_enum aic3x_agc_attack_enum[] = {
263 SOC_ENUM_SINGLE(LAGC_CTRL_A, 2, 4, aic3x_agc_attack),
264 SOC_ENUM_SINGLE(RAGC_CTRL_A, 2, 4, aic3x_agc_attack),
265 };
266
267 static const char *aic3x_agc_decay[] = { "100ms", "200ms", "400ms", "500ms" };
268 static const struct soc_enum aic3x_agc_decay_enum[] = {
269 SOC_ENUM_SINGLE(LAGC_CTRL_A, 0, 4, aic3x_agc_decay),
270 SOC_ENUM_SINGLE(RAGC_CTRL_A, 0, 4, aic3x_agc_decay),
271 };
272
273 /*
274 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
275 */
276 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
277 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
278 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
279 /*
280 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
281 * Step size is approximately 0.5 dB over most of the scale but increasing
282 * near the very low levels.
283 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
284 * but having increasing dB difference below that (and where it doesn't count
285 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
286 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
287 */
288 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
289
290 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
291 /* Output */
292 SOC_DOUBLE_R_TLV("PCM Playback Volume",
293 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
294
295 /*
296 * Output controls that map to output mixer switches. Note these are
297 * only for swapped L-to-R and R-to-L routes. See below stereo controls
298 * for direct L-to-L and R-to-R routes.
299 */
300 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
301 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
302 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
303 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
304 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
305 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
306
307 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
308 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
309 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
310 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
311 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
312 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
313
314 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
315 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
316 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
317 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
318 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
319 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
320
321 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
322 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
323 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
324 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
325 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
326 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
327
328 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
329 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
330 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
331 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
332 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
333 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
334
335 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
336 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
337 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
338 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
339 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
340 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
341
342 /* Stereo output controls for direct L-to-L and R-to-R routes */
343 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
344 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
345 0, 118, 1, output_stage_tlv),
346 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
347 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
348 0, 118, 1, output_stage_tlv),
349 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
350 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
351 0, 118, 1, output_stage_tlv),
352
353 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
354 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
355 0, 118, 1, output_stage_tlv),
356 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
357 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
358 0, 118, 1, output_stage_tlv),
359 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
360 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
361 0, 118, 1, output_stage_tlv),
362
363 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
364 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
365 0, 118, 1, output_stage_tlv),
366 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
367 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
368 0, 118, 1, output_stage_tlv),
369 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
370 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
371 0, 118, 1, output_stage_tlv),
372
373 /* Output pin mute controls */
374 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
375 0x01, 0),
376 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
377 0x01, 0),
378 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
379 0x01, 0),
380
381 /*
382 * Note: enable Automatic input Gain Controller with care. It can
383 * adjust PGA to max value when ADC is on and will never go back.
384 */
385 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
386 SOC_ENUM("Left AGC Target level", aic3x_agc_level_enum[0]),
387 SOC_ENUM("Right AGC Target level", aic3x_agc_level_enum[1]),
388 SOC_ENUM("Left AGC Attack time", aic3x_agc_attack_enum[0]),
389 SOC_ENUM("Right AGC Attack time", aic3x_agc_attack_enum[1]),
390 SOC_ENUM("Left AGC Decay time", aic3x_agc_decay_enum[0]),
391 SOC_ENUM("Right AGC Decay time", aic3x_agc_decay_enum[1]),
392
393 /* De-emphasis */
394 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
395
396 /* Input */
397 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
398 0, 119, 0, adc_tlv),
399 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
400
401 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
402 };
403
404 static const struct snd_kcontrol_new aic3x_mono_controls[] = {
405 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
406 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
407 0, 118, 1, output_stage_tlv),
408 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
409 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
410 0, 118, 1, output_stage_tlv),
411 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
412 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
413 0, 118, 1, output_stage_tlv),
414
415 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
416 };
417
418 /*
419 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
420 */
421 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
422
423 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
424 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
425
426 /* Left DAC Mux */
427 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
428 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
429
430 /* Right DAC Mux */
431 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
432 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
433
434 /* Left HPCOM Mux */
435 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
436 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
437
438 /* Right HPCOM Mux */
439 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
440 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
441
442 /* Left Line Mixer */
443 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
444 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
448 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
449 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
450 };
451
452 /* Right Line Mixer */
453 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
454 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
460 };
461
462 /* Mono Mixer */
463 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
464 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
465 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
466 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
469 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
470 };
471
472 /* Left HP Mixer */
473 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
474 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
475 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
476 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
477 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
478 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
479 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
480 };
481
482 /* Right HP Mixer */
483 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
484 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
485 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
486 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
487 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
488 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
489 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
490 };
491
492 /* Left HPCOM Mixer */
493 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
494 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
495 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
496 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
497 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
498 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
499 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
500 };
501
502 /* Right HPCOM Mixer */
503 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
504 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
505 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
506 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
507 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
508 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
509 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
510 };
511
512 /* Left PGA Mixer */
513 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
514 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
515 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
516 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
517 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
518 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
519 };
520
521 /* Right PGA Mixer */
522 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
523 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
524 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
525 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
526 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
527 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
528 };
529
530 /* Left Line1 Mux */
531 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
532 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
533 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
534 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
535
536 /* Right Line1 Mux */
537 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
538 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
539 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
540 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
541
542 /* Left Line2 Mux */
543 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
544 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
545
546 /* Right Line2 Mux */
547 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
548 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
549
550 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
551 /* Left DAC to Left Outputs */
552 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
553 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
554 &aic3x_left_dac_mux_controls),
555 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
556 &aic3x_left_hpcom_mux_controls),
557 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
558 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
559 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
560
561 /* Right DAC to Right Outputs */
562 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
563 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
564 &aic3x_right_dac_mux_controls),
565 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
566 &aic3x_right_hpcom_mux_controls),
567 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
568 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
569 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
570
571 /* Inputs to Left ADC */
572 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
573 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
574 &aic3x_left_pga_mixer_controls[0],
575 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
576 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
577 &aic3x_left_line1l_mux_controls),
578 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
579 &aic3x_left_line1r_mux_controls),
580 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
581 &aic3x_left_line2_mux_controls),
582
583 /* Inputs to Right ADC */
584 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
585 LINE1R_2_RADC_CTRL, 2, 0),
586 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
587 &aic3x_right_pga_mixer_controls[0],
588 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
589 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
590 &aic3x_right_line1l_mux_controls),
591 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
592 &aic3x_right_line1r_mux_controls),
593 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
594 &aic3x_right_line2_mux_controls),
595
596 /*
597 * Not a real mic bias widget but similar function. This is for dynamic
598 * control of GPIO1 digital mic modulator clock output function when
599 * using digital mic.
600 */
601 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
602 AIC3X_GPIO1_REG, 4, 0xf,
603 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
604 AIC3X_GPIO1_FUNC_DISABLED),
605
606 /*
607 * Also similar function like mic bias. Selects digital mic with
608 * configurable oversampling rate instead of ADC converter.
609 */
610 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
611 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
612 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
613 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
614 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
615 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
616
617 /* Mic Bias */
618 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
619 mic_bias_event,
620 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
621
622 /* Output mixers */
623 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
624 &aic3x_left_line_mixer_controls[0],
625 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
626 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
627 &aic3x_right_line_mixer_controls[0],
628 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
629 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
630 &aic3x_left_hp_mixer_controls[0],
631 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
632 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
633 &aic3x_right_hp_mixer_controls[0],
634 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
635 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
636 &aic3x_left_hpcom_mixer_controls[0],
637 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
638 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
639 &aic3x_right_hpcom_mixer_controls[0],
640 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
641
642 SND_SOC_DAPM_OUTPUT("LLOUT"),
643 SND_SOC_DAPM_OUTPUT("RLOUT"),
644 SND_SOC_DAPM_OUTPUT("HPLOUT"),
645 SND_SOC_DAPM_OUTPUT("HPROUT"),
646 SND_SOC_DAPM_OUTPUT("HPLCOM"),
647 SND_SOC_DAPM_OUTPUT("HPRCOM"),
648
649 SND_SOC_DAPM_INPUT("MIC3L"),
650 SND_SOC_DAPM_INPUT("MIC3R"),
651 SND_SOC_DAPM_INPUT("LINE1L"),
652 SND_SOC_DAPM_INPUT("LINE1R"),
653 SND_SOC_DAPM_INPUT("LINE2L"),
654 SND_SOC_DAPM_INPUT("LINE2R"),
655
656 /*
657 * Virtual output pin to detection block inside codec. This can be
658 * used to keep codec bias on if gpio or detection features are needed.
659 * Force pin on or construct a path with an input jack and mic bias
660 * widgets.
661 */
662 SND_SOC_DAPM_OUTPUT("Detection"),
663 };
664
665 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {
666 /* Mono Output */
667 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
668
669 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
670 &aic3x_mono_mixer_controls[0],
671 ARRAY_SIZE(aic3x_mono_mixer_controls)),
672
673 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
674 };
675
676 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
677 /* Class-D outputs */
678 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
679 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
680
681 SND_SOC_DAPM_OUTPUT("SPOP"),
682 SND_SOC_DAPM_OUTPUT("SPOM"),
683 };
684
685 static const struct snd_soc_dapm_route intercon[] = {
686 /* Left Input */
687 {"Left Line1L Mux", "single-ended", "LINE1L"},
688 {"Left Line1L Mux", "differential", "LINE1L"},
689 {"Left Line1R Mux", "single-ended", "LINE1R"},
690 {"Left Line1R Mux", "differential", "LINE1R"},
691
692 {"Left Line2L Mux", "single-ended", "LINE2L"},
693 {"Left Line2L Mux", "differential", "LINE2L"},
694
695 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
696 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
697 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
698 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
699 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
700
701 {"Left ADC", NULL, "Left PGA Mixer"},
702 {"Left ADC", NULL, "GPIO1 dmic modclk"},
703
704 /* Right Input */
705 {"Right Line1R Mux", "single-ended", "LINE1R"},
706 {"Right Line1R Mux", "differential", "LINE1R"},
707 {"Right Line1L Mux", "single-ended", "LINE1L"},
708 {"Right Line1L Mux", "differential", "LINE1L"},
709
710 {"Right Line2R Mux", "single-ended", "LINE2R"},
711 {"Right Line2R Mux", "differential", "LINE2R"},
712
713 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
714 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
715 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
716 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
717 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
718
719 {"Right ADC", NULL, "Right PGA Mixer"},
720 {"Right ADC", NULL, "GPIO1 dmic modclk"},
721
722 /*
723 * Logical path between digital mic enable and GPIO1 modulator clock
724 * output function
725 */
726 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
727 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
728 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
729
730 /* Left DAC Output */
731 {"Left DAC Mux", "DAC_L1", "Left DAC"},
732 {"Left DAC Mux", "DAC_L2", "Left DAC"},
733 {"Left DAC Mux", "DAC_L3", "Left DAC"},
734
735 /* Right DAC Output */
736 {"Right DAC Mux", "DAC_R1", "Right DAC"},
737 {"Right DAC Mux", "DAC_R2", "Right DAC"},
738 {"Right DAC Mux", "DAC_R3", "Right DAC"},
739
740 /* Left Line Output */
741 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
742 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
743 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
744 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
745 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
746 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
747
748 {"Left Line Out", NULL, "Left Line Mixer"},
749 {"Left Line Out", NULL, "Left DAC Mux"},
750 {"LLOUT", NULL, "Left Line Out"},
751
752 /* Right Line Output */
753 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
754 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
755 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
756 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
757 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
758 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
759
760 {"Right Line Out", NULL, "Right Line Mixer"},
761 {"Right Line Out", NULL, "Right DAC Mux"},
762 {"RLOUT", NULL, "Right Line Out"},
763
764 /* Left HP Output */
765 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
766 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
767 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
768 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
769 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
770 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
771
772 {"Left HP Out", NULL, "Left HP Mixer"},
773 {"Left HP Out", NULL, "Left DAC Mux"},
774 {"HPLOUT", NULL, "Left HP Out"},
775
776 /* Right HP Output */
777 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
778 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
779 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
780 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
781 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
782 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
783
784 {"Right HP Out", NULL, "Right HP Mixer"},
785 {"Right HP Out", NULL, "Right DAC Mux"},
786 {"HPROUT", NULL, "Right HP Out"},
787
788 /* Left HPCOM Output */
789 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
790 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
791 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
792 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
793 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
794 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
795
796 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
797 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
798 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
799 {"Left HP Com", NULL, "Left HPCOM Mux"},
800 {"HPLCOM", NULL, "Left HP Com"},
801
802 /* Right HPCOM Output */
803 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
804 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
805 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
806 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
807 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
808 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
809
810 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
811 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
812 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
813 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
814 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
815 {"Right HP Com", NULL, "Right HPCOM Mux"},
816 {"HPRCOM", NULL, "Right HP Com"},
817 };
818
819 static const struct snd_soc_dapm_route intercon_mono[] = {
820 /* Mono Output */
821 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
822 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
823 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
824 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
825 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
826 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
827 {"Mono Out", NULL, "Mono Mixer"},
828 {"MONO_LOUT", NULL, "Mono Out"},
829 };
830
831 static const struct snd_soc_dapm_route intercon_3007[] = {
832 /* Class-D outputs */
833 {"Left Class-D Out", NULL, "Left Line Out"},
834 {"Right Class-D Out", NULL, "Left Line Out"},
835 {"SPOP", NULL, "Left Class-D Out"},
836 {"SPOM", NULL, "Right Class-D Out"},
837 };
838
839 static int aic3x_add_widgets(struct snd_soc_codec *codec)
840 {
841 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
842 struct snd_soc_dapm_context *dapm = &codec->dapm;
843
844 switch (aic3x->model) {
845 case AIC3X_MODEL_3X:
846 case AIC3X_MODEL_33:
847 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets,
848 ARRAY_SIZE(aic3x_dapm_mono_widgets));
849 snd_soc_dapm_add_routes(dapm, intercon_mono,
850 ARRAY_SIZE(intercon_mono));
851 break;
852 case AIC3X_MODEL_3007:
853 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
854 ARRAY_SIZE(aic3007_dapm_widgets));
855 snd_soc_dapm_add_routes(dapm, intercon_3007,
856 ARRAY_SIZE(intercon_3007));
857 break;
858 }
859
860 return 0;
861 }
862
863 static int aic3x_hw_params(struct snd_pcm_substream *substream,
864 struct snd_pcm_hw_params *params,
865 struct snd_soc_dai *dai)
866 {
867 struct snd_soc_codec *codec = dai->codec;
868 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
869 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
870 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
871 u16 d, pll_d = 1;
872 int clk;
873
874 /* select data word length */
875 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
876 switch (params_format(params)) {
877 case SNDRV_PCM_FORMAT_S16_LE:
878 break;
879 case SNDRV_PCM_FORMAT_S20_3LE:
880 data |= (0x01 << 4);
881 break;
882 case SNDRV_PCM_FORMAT_S24_LE:
883 data |= (0x02 << 4);
884 break;
885 case SNDRV_PCM_FORMAT_S32_LE:
886 data |= (0x03 << 4);
887 break;
888 }
889 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
890
891 /* Fsref can be 44100 or 48000 */
892 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
893
894 /* Try to find a value for Q which allows us to bypass the PLL and
895 * generate CODEC_CLK directly. */
896 for (pll_q = 2; pll_q < 18; pll_q++)
897 if (aic3x->sysclk / (128 * pll_q) == fsref) {
898 bypass_pll = 1;
899 break;
900 }
901
902 if (bypass_pll) {
903 pll_q &= 0xf;
904 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
905 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
906 /* disable PLL if it is bypassed */
907 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
908
909 } else {
910 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
911 /* enable PLL when it is used */
912 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
913 PLL_ENABLE, PLL_ENABLE);
914 }
915
916 /* Route Left DAC to left channel input and
917 * right DAC to right channel input */
918 data = (LDAC2LCH | RDAC2RCH);
919 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
920 if (params_rate(params) >= 64000)
921 data |= DUAL_RATE_MODE;
922 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
923
924 /* codec sample rate select */
925 data = (fsref * 20) / params_rate(params);
926 if (params_rate(params) < 64000)
927 data /= 2;
928 data /= 5;
929 data -= 2;
930 data |= (data << 4);
931 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
932
933 if (bypass_pll)
934 return 0;
935
936 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
937 * one wins the game. Try with d==0 first, next with d!=0.
938 * Constraints for j are according to the datasheet.
939 * The sysclk is divided by 1000 to prevent integer overflows.
940 */
941
942 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
943
944 for (r = 1; r <= 16; r++)
945 for (p = 1; p <= 8; p++) {
946 for (j = 4; j <= 55; j++) {
947 /* This is actually 1000*((j+(d/10000))*r)/p
948 * The term had to be converted to get
949 * rid of the division by 10000; d = 0 here
950 */
951 int tmp_clk = (1000 * j * r) / p;
952
953 /* Check whether this values get closer than
954 * the best ones we had before
955 */
956 if (abs(codec_clk - tmp_clk) <
957 abs(codec_clk - last_clk)) {
958 pll_j = j; pll_d = 0;
959 pll_r = r; pll_p = p;
960 last_clk = tmp_clk;
961 }
962
963 /* Early exit for exact matches */
964 if (tmp_clk == codec_clk)
965 goto found;
966 }
967 }
968
969 /* try with d != 0 */
970 for (p = 1; p <= 8; p++) {
971 j = codec_clk * p / 1000;
972
973 if (j < 4 || j > 11)
974 continue;
975
976 /* do not use codec_clk here since we'd loose precision */
977 d = ((2048 * p * fsref) - j * aic3x->sysclk)
978 * 100 / (aic3x->sysclk/100);
979
980 clk = (10000 * j + d) / (10 * p);
981
982 /* check whether this values get closer than the best
983 * ones we had before */
984 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
985 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
986 last_clk = clk;
987 }
988
989 /* Early exit for exact matches */
990 if (clk == codec_clk)
991 goto found;
992 }
993
994 if (last_clk == 0) {
995 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
996 return -EINVAL;
997 }
998
999 found:
1000 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
1001 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
1002 pll_r << PLLR_SHIFT);
1003 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1004 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
1005 (pll_d >> 6) << PLLD_MSB_SHIFT);
1006 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
1007 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1008
1009 return 0;
1010 }
1011
1012 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
1013 {
1014 struct snd_soc_codec *codec = dai->codec;
1015 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
1016 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
1017
1018 if (mute) {
1019 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1020 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
1021 } else {
1022 snd_soc_write(codec, LDAC_VOL, ldac_reg);
1023 snd_soc_write(codec, RDAC_VOL, rdac_reg);
1024 }
1025
1026 return 0;
1027 }
1028
1029 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1030 int clk_id, unsigned int freq, int dir)
1031 {
1032 struct snd_soc_codec *codec = codec_dai->codec;
1033 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1034
1035 /* set clock on MCLK or GPIO2 or BCLK */
1036 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1037 clk_id << PLLCLK_IN_SHIFT);
1038 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1039 clk_id << CLKDIV_IN_SHIFT);
1040
1041 aic3x->sysclk = freq;
1042 return 0;
1043 }
1044
1045 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1046 unsigned int fmt)
1047 {
1048 struct snd_soc_codec *codec = codec_dai->codec;
1049 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1050 u8 iface_areg, iface_breg;
1051 int delay = 0;
1052
1053 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1054 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1055
1056 /* set master/slave audio interface */
1057 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1058 case SND_SOC_DAIFMT_CBM_CFM:
1059 aic3x->master = 1;
1060 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1061 break;
1062 case SND_SOC_DAIFMT_CBS_CFS:
1063 aic3x->master = 0;
1064 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
1065 break;
1066 default:
1067 return -EINVAL;
1068 }
1069
1070 /*
1071 * match both interface format and signal polarities since they
1072 * are fixed
1073 */
1074 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1075 SND_SOC_DAIFMT_INV_MASK)) {
1076 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1077 break;
1078 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1079 delay = 1;
1080 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1081 iface_breg |= (0x01 << 6);
1082 break;
1083 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1084 iface_breg |= (0x02 << 6);
1085 break;
1086 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1087 iface_breg |= (0x03 << 6);
1088 break;
1089 default:
1090 return -EINVAL;
1091 }
1092
1093 /* set iface */
1094 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1095 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1096 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1097
1098 return 0;
1099 }
1100
1101 static int aic3x_regulator_event(struct notifier_block *nb,
1102 unsigned long event, void *data)
1103 {
1104 struct aic3x_disable_nb *disable_nb =
1105 container_of(nb, struct aic3x_disable_nb, nb);
1106 struct aic3x_priv *aic3x = disable_nb->aic3x;
1107
1108 if (event & REGULATOR_EVENT_DISABLE) {
1109 /*
1110 * Put codec to reset and require cache sync as at least one
1111 * of the supplies was disabled
1112 */
1113 if (gpio_is_valid(aic3x->gpio_reset))
1114 gpio_set_value(aic3x->gpio_reset, 0);
1115 regcache_mark_dirty(aic3x->regmap);
1116 }
1117
1118 return 0;
1119 }
1120
1121 static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1122 {
1123 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1124 unsigned int pll_c, pll_d;
1125 int ret;
1126
1127 if (power) {
1128 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1129 aic3x->supplies);
1130 if (ret)
1131 goto out;
1132 aic3x->power = 1;
1133
1134 if (gpio_is_valid(aic3x->gpio_reset)) {
1135 udelay(1);
1136 gpio_set_value(aic3x->gpio_reset, 1);
1137 }
1138
1139 /* Sync reg_cache with the hardware */
1140 regcache_cache_only(aic3x->regmap, false);
1141 regcache_sync(aic3x->regmap);
1142
1143 /* Rewrite paired PLL D registers in case cached sync skipped
1144 * writing one of them and thus caused other one also not
1145 * being written
1146 */
1147 pll_c = snd_soc_read(codec, AIC3X_PLL_PROGC_REG);
1148 pll_d = snd_soc_read(codec, AIC3X_PLL_PROGD_REG);
1149 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
1150 pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
1151 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, pll_c);
1152 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, pll_d);
1153 }
1154 } else {
1155 /*
1156 * Do soft reset to this codec instance in order to clear
1157 * possible VDD leakage currents in case the supply regulators
1158 * remain on
1159 */
1160 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1161 regcache_mark_dirty(aic3x->regmap);
1162 aic3x->power = 0;
1163 /* HW writes are needless when bias is off */
1164 regcache_cache_only(aic3x->regmap, true);
1165 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1166 aic3x->supplies);
1167 }
1168 out:
1169 return ret;
1170 }
1171
1172 static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1173 enum snd_soc_bias_level level)
1174 {
1175 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1176
1177 switch (level) {
1178 case SND_SOC_BIAS_ON:
1179 break;
1180 case SND_SOC_BIAS_PREPARE:
1181 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
1182 aic3x->master) {
1183 /* enable pll */
1184 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1185 PLL_ENABLE, PLL_ENABLE);
1186 }
1187 break;
1188 case SND_SOC_BIAS_STANDBY:
1189 if (!aic3x->power)
1190 aic3x_set_power(codec, 1);
1191 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
1192 aic3x->master) {
1193 /* disable pll */
1194 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1195 PLL_ENABLE, 0);
1196 }
1197 break;
1198 case SND_SOC_BIAS_OFF:
1199 if (aic3x->power)
1200 aic3x_set_power(codec, 0);
1201 break;
1202 }
1203 codec->dapm.bias_level = level;
1204
1205 return 0;
1206 }
1207
1208 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1209 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1210 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1211
1212 static const struct snd_soc_dai_ops aic3x_dai_ops = {
1213 .hw_params = aic3x_hw_params,
1214 .digital_mute = aic3x_mute,
1215 .set_sysclk = aic3x_set_dai_sysclk,
1216 .set_fmt = aic3x_set_dai_fmt,
1217 };
1218
1219 static struct snd_soc_dai_driver aic3x_dai = {
1220 .name = "tlv320aic3x-hifi",
1221 .playback = {
1222 .stream_name = "Playback",
1223 .channels_min = 2,
1224 .channels_max = 2,
1225 .rates = AIC3X_RATES,
1226 .formats = AIC3X_FORMATS,},
1227 .capture = {
1228 .stream_name = "Capture",
1229 .channels_min = 2,
1230 .channels_max = 2,
1231 .rates = AIC3X_RATES,
1232 .formats = AIC3X_FORMATS,},
1233 .ops = &aic3x_dai_ops,
1234 .symmetric_rates = 1,
1235 };
1236
1237 static int aic3x_suspend(struct snd_soc_codec *codec)
1238 {
1239 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1240
1241 return 0;
1242 }
1243
1244 static int aic3x_resume(struct snd_soc_codec *codec)
1245 {
1246 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1247
1248 return 0;
1249 }
1250
1251 static void aic3x_mono_init(struct snd_soc_codec *codec)
1252 {
1253 /* DAC to Mono Line Out default volume and route to Output mixer */
1254 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1255 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1256
1257 /* unmute all outputs */
1258 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1259
1260 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1261 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1262 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1263
1264 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1265 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1266 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1267 }
1268
1269 /*
1270 * initialise the AIC3X driver
1271 * register the mixer and dsp interfaces with the kernel
1272 */
1273 static int aic3x_init(struct snd_soc_codec *codec)
1274 {
1275 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1276
1277 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1278 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1279
1280 /* DAC default volume and mute */
1281 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1282 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1283
1284 /* DAC to HP default volume and route to Output mixer */
1285 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1286 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1287 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1288 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1289 /* DAC to Line Out default volume and route to Output mixer */
1290 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1291 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1292
1293 /* unmute all outputs */
1294 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1295 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1296 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1297 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1298 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1299 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
1300
1301 /* ADC default volume and unmute */
1302 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1303 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
1304 /* By default route Line1 to ADC PGA mixer */
1305 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1306 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1307
1308 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1309 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1310 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1311 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1312 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1313 /* PGA to Line Out default volume, disconnect from Output Mixer */
1314 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1315 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1316
1317 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1318 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1319 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1320 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1321 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1322 /* Line2 Line Out default volume, disconnect from Output Mixer */
1323 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1324 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1325
1326 switch (aic3x->model) {
1327 case AIC3X_MODEL_3X:
1328 case AIC3X_MODEL_33:
1329 aic3x_mono_init(codec);
1330 break;
1331 case AIC3X_MODEL_3007:
1332 snd_soc_write(codec, CLASSD_CTRL, 0);
1333 break;
1334 }
1335
1336 return 0;
1337 }
1338
1339 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1340 {
1341 struct aic3x_priv *a;
1342
1343 list_for_each_entry(a, &reset_list, list) {
1344 if (gpio_is_valid(aic3x->gpio_reset) &&
1345 aic3x->gpio_reset == a->gpio_reset)
1346 return true;
1347 }
1348
1349 return false;
1350 }
1351
1352 static int aic3x_probe(struct snd_soc_codec *codec)
1353 {
1354 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1355 int ret, i;
1356
1357 INIT_LIST_HEAD(&aic3x->list);
1358 aic3x->codec = codec;
1359
1360 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1361 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1362 aic3x->disable_nb[i].aic3x = aic3x;
1363 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1364 &aic3x->disable_nb[i].nb);
1365 if (ret) {
1366 dev_err(codec->dev,
1367 "Failed to request regulator notifier: %d\n",
1368 ret);
1369 goto err_notif;
1370 }
1371 }
1372
1373 regcache_mark_dirty(aic3x->regmap);
1374 aic3x_init(codec);
1375
1376 if (aic3x->setup) {
1377 /* setup GPIO functions */
1378 snd_soc_write(codec, AIC3X_GPIO1_REG,
1379 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1380 snd_soc_write(codec, AIC3X_GPIO2_REG,
1381 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1382 }
1383
1384 switch (aic3x->model) {
1385 case AIC3X_MODEL_3X:
1386 case AIC3X_MODEL_33:
1387 snd_soc_add_codec_controls(codec, aic3x_mono_controls,
1388 ARRAY_SIZE(aic3x_mono_controls));
1389 break;
1390 case AIC3X_MODEL_3007:
1391 snd_soc_add_codec_controls(codec,
1392 &aic3x_classd_amp_gain_ctrl, 1);
1393 break;
1394 }
1395
1396 /* set mic bias voltage */
1397 switch (aic3x->micbias_vg) {
1398 case AIC3X_MICBIAS_2_0V:
1399 case AIC3X_MICBIAS_2_5V:
1400 case AIC3X_MICBIAS_AVDDV:
1401 snd_soc_update_bits(codec, MICBIAS_CTRL,
1402 MICBIAS_LEVEL_MASK,
1403 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1404 break;
1405 case AIC3X_MICBIAS_OFF:
1406 /*
1407 * noting to do. target won't enter here. This is just to avoid
1408 * compile time warning "warning: enumeration value
1409 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1410 */
1411 break;
1412 }
1413
1414 aic3x_add_widgets(codec);
1415
1416 return 0;
1417
1418 err_notif:
1419 while (i--)
1420 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1421 &aic3x->disable_nb[i].nb);
1422 return ret;
1423 }
1424
1425 static int aic3x_remove(struct snd_soc_codec *codec)
1426 {
1427 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1428 int i;
1429
1430 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1431 list_del(&aic3x->list);
1432 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1433 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1434 &aic3x->disable_nb[i].nb);
1435
1436 return 0;
1437 }
1438
1439 static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1440 .set_bias_level = aic3x_set_bias_level,
1441 .idle_bias_off = true,
1442 .probe = aic3x_probe,
1443 .remove = aic3x_remove,
1444 .suspend = aic3x_suspend,
1445 .resume = aic3x_resume,
1446 .controls = aic3x_snd_controls,
1447 .num_controls = ARRAY_SIZE(aic3x_snd_controls),
1448 .dapm_widgets = aic3x_dapm_widgets,
1449 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
1450 .dapm_routes = intercon,
1451 .num_dapm_routes = ARRAY_SIZE(intercon),
1452 };
1453
1454 /*
1455 * AIC3X 2 wire address can be up to 4 devices with device addresses
1456 * 0x18, 0x19, 0x1A, 0x1B
1457 */
1458
1459 static const struct i2c_device_id aic3x_i2c_id[] = {
1460 { "tlv320aic3x", AIC3X_MODEL_3X },
1461 { "tlv320aic33", AIC3X_MODEL_33 },
1462 { "tlv320aic3007", AIC3X_MODEL_3007 },
1463 { "tlv320aic3106", AIC3X_MODEL_3X },
1464 { }
1465 };
1466 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1467
1468 static const struct reg_default aic3007_class_d[] = {
1469 /* Class-D speaker driver init; datasheet p. 46 */
1470 { AIC3X_PAGE_SELECT, 0x0D },
1471 { 0xD, 0x0D },
1472 { 0x8, 0x5C },
1473 { 0x8, 0x5D },
1474 { 0x8, 0x5C },
1475 { AIC3X_PAGE_SELECT, 0x00 },
1476 };
1477
1478 /*
1479 * If the i2c layer weren't so broken, we could pass this kind of data
1480 * around
1481 */
1482 static int aic3x_i2c_probe(struct i2c_client *i2c,
1483 const struct i2c_device_id *id)
1484 {
1485 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1486 struct aic3x_priv *aic3x;
1487 struct aic3x_setup_data *ai3x_setup;
1488 struct device_node *np = i2c->dev.of_node;
1489 int ret, i;
1490 u32 value;
1491
1492 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
1493 if (aic3x == NULL) {
1494 dev_err(&i2c->dev, "failed to create private data\n");
1495 return -ENOMEM;
1496 }
1497
1498 aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap);
1499 if (IS_ERR(aic3x->regmap)) {
1500 ret = PTR_ERR(aic3x->regmap);
1501 return ret;
1502 }
1503
1504 regcache_cache_only(aic3x->regmap, true);
1505
1506 i2c_set_clientdata(i2c, aic3x);
1507 if (pdata) {
1508 aic3x->gpio_reset = pdata->gpio_reset;
1509 aic3x->setup = pdata->setup;
1510 aic3x->micbias_vg = pdata->micbias_vg;
1511 } else if (np) {
1512 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1513 GFP_KERNEL);
1514 if (ai3x_setup == NULL) {
1515 dev_err(&i2c->dev, "failed to create private data\n");
1516 return -ENOMEM;
1517 }
1518
1519 ret = of_get_named_gpio(np, "gpio-reset", 0);
1520 if (ret >= 0)
1521 aic3x->gpio_reset = ret;
1522 else
1523 aic3x->gpio_reset = -1;
1524
1525 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1526 ai3x_setup->gpio_func, 2) >= 0) {
1527 aic3x->setup = ai3x_setup;
1528 }
1529
1530 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1531 switch (value) {
1532 case 1 :
1533 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1534 break;
1535 case 2 :
1536 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1537 break;
1538 case 3 :
1539 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1540 break;
1541 default :
1542 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1543 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1544 "found in DT\n");
1545 }
1546 } else {
1547 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1548 }
1549
1550 } else {
1551 aic3x->gpio_reset = -1;
1552 }
1553
1554 aic3x->model = id->driver_data;
1555
1556 if (gpio_is_valid(aic3x->gpio_reset) &&
1557 !aic3x_is_shared_reset(aic3x)) {
1558 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1559 if (ret != 0)
1560 goto err;
1561 gpio_direction_output(aic3x->gpio_reset, 0);
1562 }
1563
1564 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1565 aic3x->supplies[i].supply = aic3x_supply_names[i];
1566
1567 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1568 aic3x->supplies);
1569 if (ret != 0) {
1570 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1571 goto err_gpio;
1572 }
1573
1574 if (aic3x->model == AIC3X_MODEL_3007) {
1575 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d,
1576 ARRAY_SIZE(aic3007_class_d));
1577 if (ret != 0)
1578 dev_err(&i2c->dev, "Failed to init class D: %d\n",
1579 ret);
1580 }
1581
1582 ret = snd_soc_register_codec(&i2c->dev,
1583 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1584
1585 if (ret != 0)
1586 goto err_gpio;
1587
1588 list_add(&aic3x->list, &reset_list);
1589
1590 return 0;
1591
1592 err_gpio:
1593 if (gpio_is_valid(aic3x->gpio_reset) &&
1594 !aic3x_is_shared_reset(aic3x))
1595 gpio_free(aic3x->gpio_reset);
1596 err:
1597 return ret;
1598 }
1599
1600 static int aic3x_i2c_remove(struct i2c_client *client)
1601 {
1602 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1603
1604 snd_soc_unregister_codec(&client->dev);
1605 if (gpio_is_valid(aic3x->gpio_reset) &&
1606 !aic3x_is_shared_reset(aic3x)) {
1607 gpio_set_value(aic3x->gpio_reset, 0);
1608 gpio_free(aic3x->gpio_reset);
1609 }
1610 return 0;
1611 }
1612
1613 #if defined(CONFIG_OF)
1614 static const struct of_device_id tlv320aic3x_of_match[] = {
1615 { .compatible = "ti,tlv320aic3x", },
1616 { .compatible = "ti,tlv320aic33" },
1617 { .compatible = "ti,tlv320aic3007" },
1618 { .compatible = "ti,tlv320aic3106" },
1619 {},
1620 };
1621 MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
1622 #endif
1623
1624 /* machine i2c codec control layer */
1625 static struct i2c_driver aic3x_i2c_driver = {
1626 .driver = {
1627 .name = "tlv320aic3x-codec",
1628 .owner = THIS_MODULE,
1629 .of_match_table = of_match_ptr(tlv320aic3x_of_match),
1630 },
1631 .probe = aic3x_i2c_probe,
1632 .remove = aic3x_i2c_remove,
1633 .id_table = aic3x_i2c_id,
1634 };
1635
1636 module_i2c_driver(aic3x_i2c_driver);
1637
1638 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1639 MODULE_AUTHOR("Vladimir Barinov");
1640 MODULE_LICENSE("GPL");
Linux with added FPC-III support