| blob | d41fe88ffea4303bff291cee91ef124d92adfad6 |
1 /*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 *
46 * Contains definitions specific to the Armada XP MV78460 SoC that are not
47 * common to all Armada XP SoCs.
48 */
50 #include "armada-xp.dtsi"
52 / {
53 model = "Marvell Armada XP MV78460 SoC";
54 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
56 aliases {
57 gpio0 = &gpio0;
58 gpio1 = &gpio1;
59 gpio2 = &gpio2;
60 eth3 = ð3;
61 };
64 cpus {
65 #address-cells = <1>;
66 #size-cells = <0>;
67 enable-method = "marvell,armada-xp-smp";
69 cpu@0 {
70 device_type = "cpu";
71 compatible = "marvell,sheeva-v7";
72 reg = <0>;
73 clocks = <&cpuclk 0>;
74 clock-latency = <1000000>;
75 };
77 cpu@1 {
78 device_type = "cpu";
79 compatible = "marvell,sheeva-v7";
80 reg = <1>;
81 clocks = <&cpuclk 1>;
82 clock-latency = <1000000>;
83 };
85 cpu@2 {
86 device_type = "cpu";
87 compatible = "marvell,sheeva-v7";
88 reg = <2>;
89 clocks = <&cpuclk 2>;
90 clock-latency = <1000000>;
91 };
93 cpu@3 {
94 device_type = "cpu";
95 compatible = "marvell,sheeva-v7";
96 reg = <3>;
97 clocks = <&cpuclk 3>;
98 clock-latency = <1000000>;
99 };
100 };
102 soc {
103 /*
104 * MV78460 has 4 PCIe units Gen2.0: Two units can be
105 * configured as x4 or quad x1 lanes. Two units are
106 * x4/x1.
107 */
108 pcie-controller {
109 compatible = "marvell,armada-xp-pcie";
110 status = "disabled";
111 device_type = "pci";
113 #address-cells = <3>;
114 #size-cells = <2>;
116 msi-parent = <&mpic>;
117 bus-range = <0x00 0xff>;
119 ranges =
120 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
121 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
122 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
123 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
124 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
125 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
126 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
127 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
128 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
129 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
130 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
131 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
132 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
133 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
134 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
135 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
136 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
137 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
139 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
140 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
141 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
142 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
143 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
144 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
145 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
146 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
148 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
149 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
151 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
152 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
154 pcie@1,0 {
155 device_type = "pci";
156 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
157 reg = <0x0800 0 0 0 0>;
158 #address-cells = <3>;
159 #size-cells = <2>;
160 #interrupt-cells = <1>;
161 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
162 0x81000000 0 0 0x81000000 0x1 0 1 0>;
163 interrupt-map-mask = <0 0 0 0>;
164 interrupt-map = <0 0 0 0 &mpic 58>;
165 marvell,pcie-port = <0>;
166 marvell,pcie-lane = <0>;
167 clocks = <&gateclk 5>;
168 status = "disabled";
169 };
171 pcie@2,0 {
172 device_type = "pci";
173 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
174 reg = <0x1000 0 0 0 0>;
175 #address-cells = <3>;
176 #size-cells = <2>;
177 #interrupt-cells = <1>;
178 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
179 0x81000000 0 0 0x81000000 0x2 0 1 0>;
180 interrupt-map-mask = <0 0 0 0>;
181 interrupt-map = <0 0 0 0 &mpic 59>;
182 marvell,pcie-port = <0>;
183 marvell,pcie-lane = <1>;
184 clocks = <&gateclk 6>;
185 status = "disabled";
186 };
188 pcie@3,0 {
189 device_type = "pci";
190 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
191 reg = <0x1800 0 0 0 0>;
192 #address-cells = <3>;
193 #size-cells = <2>;
194 #interrupt-cells = <1>;
195 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
196 0x81000000 0 0 0x81000000 0x3 0 1 0>;
197 interrupt-map-mask = <0 0 0 0>;
198 interrupt-map = <0 0 0 0 &mpic 60>;
199 marvell,pcie-port = <0>;
200 marvell,pcie-lane = <2>;
201 clocks = <&gateclk 7>;
202 status = "disabled";
203 };
205 pcie@4,0 {
206 device_type = "pci";
207 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
208 reg = <0x2000 0 0 0 0>;
209 #address-cells = <3>;
210 #size-cells = <2>;
211 #interrupt-cells = <1>;
212 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
213 0x81000000 0 0 0x81000000 0x4 0 1 0>;
214 interrupt-map-mask = <0 0 0 0>;
215 interrupt-map = <0 0 0 0 &mpic 61>;
216 marvell,pcie-port = <0>;
217 marvell,pcie-lane = <3>;
218 clocks = <&gateclk 8>;
219 status = "disabled";
220 };
222 pcie@5,0 {
223 device_type = "pci";
224 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
225 reg = <0x2800 0 0 0 0>;
226 #address-cells = <3>;
227 #size-cells = <2>;
228 #interrupt-cells = <1>;
229 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
230 0x81000000 0 0 0x81000000 0x5 0 1 0>;
231 interrupt-map-mask = <0 0 0 0>;
232 interrupt-map = <0 0 0 0 &mpic 62>;
233 marvell,pcie-port = <1>;
234 marvell,pcie-lane = <0>;
235 clocks = <&gateclk 9>;
236 status = "disabled";
237 };
239 pcie@6,0 {
240 device_type = "pci";
241 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
242 reg = <0x3000 0 0 0 0>;
243 #address-cells = <3>;
244 #size-cells = <2>;
245 #interrupt-cells = <1>;
246 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
247 0x81000000 0 0 0x81000000 0x6 0 1 0>;
248 interrupt-map-mask = <0 0 0 0>;
249 interrupt-map = <0 0 0 0 &mpic 63>;
250 marvell,pcie-port = <1>;
251 marvell,pcie-lane = <1>;
252 clocks = <&gateclk 10>;
253 status = "disabled";
254 };
256 pcie@7,0 {
257 device_type = "pci";
258 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
259 reg = <0x3800 0 0 0 0>;
260 #address-cells = <3>;
261 #size-cells = <2>;
262 #interrupt-cells = <1>;
263 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
264 0x81000000 0 0 0x81000000 0x7 0 1 0>;
265 interrupt-map-mask = <0 0 0 0>;
266 interrupt-map = <0 0 0 0 &mpic 64>;
267 marvell,pcie-port = <1>;
268 marvell,pcie-lane = <2>;
269 clocks = <&gateclk 11>;
270 status = "disabled";
271 };
273 pcie@8,0 {
274 device_type = "pci";
275 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
276 reg = <0x4000 0 0 0 0>;
277 #address-cells = <3>;
278 #size-cells = <2>;
279 #interrupt-cells = <1>;
280 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
281 0x81000000 0 0 0x81000000 0x8 0 1 0>;
282 interrupt-map-mask = <0 0 0 0>;
283 interrupt-map = <0 0 0 0 &mpic 65>;
284 marvell,pcie-port = <1>;
285 marvell,pcie-lane = <3>;
286 clocks = <&gateclk 12>;
287 status = "disabled";
288 };
290 pcie@9,0 {
291 device_type = "pci";
292 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
293 reg = <0x4800 0 0 0 0>;
294 #address-cells = <3>;
295 #size-cells = <2>;
296 #interrupt-cells = <1>;
297 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
298 0x81000000 0 0 0x81000000 0x9 0 1 0>;
299 interrupt-map-mask = <0 0 0 0>;
300 interrupt-map = <0 0 0 0 &mpic 99>;
301 marvell,pcie-port = <2>;
302 marvell,pcie-lane = <0>;
303 clocks = <&gateclk 26>;
304 status = "disabled";
305 };
307 pcie@10,0 {
308 device_type = "pci";
309 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
310 reg = <0x5000 0 0 0 0>;
311 #address-cells = <3>;
312 #size-cells = <2>;
313 #interrupt-cells = <1>;
314 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
315 0x81000000 0 0 0x81000000 0xa 0 1 0>;
316 interrupt-map-mask = <0 0 0 0>;
317 interrupt-map = <0 0 0 0 &mpic 103>;
318 marvell,pcie-port = <3>;
319 marvell,pcie-lane = <0>;
320 clocks = <&gateclk 27>;
321 status = "disabled";
322 };
323 };
325 internal-regs {
326 gpio0: gpio@18100 {
327 compatible = "marvell,orion-gpio";
328 reg = <0x18100 0x40>;
329 ngpios = <32>;
330 gpio-controller;
331 #gpio-cells = <2>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
334 interrupts = <82>, <83>, <84>, <85>;
335 };
337 gpio1: gpio@18140 {
338 compatible = "marvell,orion-gpio";
339 reg = <0x18140 0x40>;
340 ngpios = <32>;
341 gpio-controller;
342 #gpio-cells = <2>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
345 interrupts = <87>, <88>, <89>, <90>;
346 };
348 gpio2: gpio@18180 {
349 compatible = "marvell,orion-gpio";
350 reg = <0x18180 0x40>;
351 ngpios = <3>;
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 interrupts = <91>;
357 };
359 eth3: ethernet@34000 {
360 compatible = "marvell,armada-xp-neta";
361 reg = <0x34000 0x4000>;
362 interrupts = <14>;
363 clocks = <&gateclk 1>;
364 status = "disabled";
365 };
366 };
367 };
368 };
370 &pinctrl {
371 compatible = "marvell,mv78460-pinctrl";
372 };