| blob | 38830d8d47835d30db060b77c49d4beb385ded4a |
1 /*
2 * OMAP2/3 CM module functions
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/delay.h>
15 #include <linux/spinlock.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
21 #include <plat/common.h>
28 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
29 #define DPLL_AUTOIDLE_DISABLE 0x0
30 #define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
32 /* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
33 #define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
34 #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
38 };
41 {
43 }
46 {
48 }
50 /* Read-modify-write a register in a CM module. Caller must lock */
52 {
53 u32 v;
61 }
64 {
66 }
69 {
71 }
73 /*
74 *
75 */
78 {
79 u32 v;
85 }
88 {
89 u32 v;
100 else
104 }
107 {
109 }
112 {
114 }
117 {
119 }
122 {
124 }
127 {
129 }
132 {
134 }
136 /*
137 * DPLL autoidle control
138 */
141 {
142 u32 v;
148 }
151 {
153 }
156 {
158 }
160 /*
161 * APLL autoidle control
162 */
165 {
166 u32 v;
172 }
175 {
177 OMAP24XX_AUTO_54M_MASK);
178 }
181 {
183 OMAP24XX_AUTO_54M_MASK);
184 }
187 {
189 OMAP24XX_AUTO_96M_MASK);
190 }
193 {
195 OMAP24XX_AUTO_96M_MASK);
196 }
198 /*
199 *
200 */
202 /**
203 * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
204 * @prcm_mod: PRCM module offset
205 * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
206 * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
207 *
208 * XXX document
209 */
211 {
213 u8 cm_idlest_reg;
214 u32 mask;
227 else
234 }
236 /*
237 * Context save/restore code - OMAP3 only
238 */
239 #ifdef CONFIG_ARCH_OMAP3
241 u32 iva2_cm_clksel1;
242 u32 iva2_cm_clksel2;
243 u32 cm_sysconfig;
244 u32 sgx_cm_clksel;
245 u32 dss_cm_clksel;
246 u32 cam_cm_clksel;
247 u32 per_cm_clksel;
248 u32 emu_cm_clksel;
249 u32 emu_cm_clkstctrl;
250 u32 pll_cm_autoidle;
251 u32 pll_cm_autoidle2;
252 u32 pll_cm_clksel4;
253 u32 pll_cm_clksel5;
254 u32 pll_cm_clken2;
255 u32 cm_polctrl;
256 u32 iva2_cm_fclken;
257 u32 iva2_cm_clken_pll;
258 u32 core_cm_fclken1;
259 u32 core_cm_fclken3;
260 u32 sgx_cm_fclken;
261 u32 wkup_cm_fclken;
262 u32 dss_cm_fclken;
263 u32 cam_cm_fclken;
264 u32 per_cm_fclken;
265 u32 usbhost_cm_fclken;
266 u32 core_cm_iclken1;
267 u32 core_cm_iclken2;
268 u32 core_cm_iclken3;
269 u32 sgx_cm_iclken;
270 u32 wkup_cm_iclken;
271 u32 dss_cm_iclken;
272 u32 cam_cm_iclken;
273 u32 per_cm_iclken;
274 u32 usbhost_cm_iclken;
275 u32 iva2_cm_autoidle2;
276 u32 mpu_cm_autoidle2;
277 u32 iva2_cm_clkstctrl;
278 u32 mpu_cm_clkstctrl;
279 u32 core_cm_clkstctrl;
280 u32 sgx_cm_clkstctrl;
281 u32 dss_cm_clkstctrl;
282 u32 cam_cm_clkstctrl;
283 u32 per_cm_clkstctrl;
284 u32 neon_cm_clkstctrl;
285 u32 usbhost_cm_clkstctrl;
286 u32 core_cm_autoidle1;
287 u32 core_cm_autoidle2;
288 u32 core_cm_autoidle3;
289 u32 wkup_cm_autoidle;
290 u32 dss_cm_autoidle;
291 u32 cam_cm_autoidle;
292 u32 per_cm_autoidle;
293 u32 usbhost_cm_autoidle;
294 u32 sgx_cm_sleepdep;
295 u32 dss_cm_sleepdep;
296 u32 cam_cm_sleepdep;
297 u32 per_cm_sleepdep;
298 u32 usbhost_cm_sleepdep;
299 u32 cm_clkout_ctrl;
300 };
305 {
323 /*
324 * As per erratum i671, ROM code does not respect the PER DPLL
325 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
326 * In this case, even though this register has been saved in
327 * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
328 * by ourselves. So, we need to save it anyway.
329 */
401 OMAP2_CM_CLKSTCTRL);
420 OMAP3430_CM_SLEEPDEP);
429 OMAP3430_CM_SLEEPDEP);
432 OMAP3_CM_CLKOUT_CTRL_OFFSET);
433 }
436 {
438 CM_CLKSEL1);
440 CM_CLKSEL2);
443 CM_CLKSEL);
445 CM_CLKSEL);
447 CM_CLKSEL);
449 CM_CLKSEL);
451 CM_CLKSEL1);
453 OMAP2_CM_CLKSTCTRL);
454 /*
455 * As per erratum i671, ROM code does not respect the PER DPLL
456 * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
457 * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
458 */
460 CM_AUTOIDLE);
462 CM_AUTOIDLE2);
464 OMAP3430ES2_CM_CLKSEL4);
466 OMAP3430ES2_CM_CLKSEL5);
468 OMAP3430ES2_CM_CLKEN2);
471 CM_FCLKEN);
473 OMAP3430_CM_CLKEN_PLL);
475 CM_FCLKEN1);
477 OMAP3430ES2_CM_FCLKEN3);
479 CM_FCLKEN);
482 CM_FCLKEN);
484 CM_FCLKEN);
486 CM_FCLKEN);
490 CM_ICLKEN1);
492 CM_ICLKEN2);
494 CM_ICLKEN3);
496 CM_ICLKEN);
499 CM_ICLKEN);
501 CM_ICLKEN);
503 CM_ICLKEN);
507 CM_AUTOIDLE2);
509 CM_AUTOIDLE2);
511 OMAP2_CM_CLKSTCTRL);
513 OMAP2_CM_CLKSTCTRL);
515 OMAP2_CM_CLKSTCTRL);
517 OMAP2_CM_CLKSTCTRL);
519 OMAP2_CM_CLKSTCTRL);
521 OMAP2_CM_CLKSTCTRL);
523 OMAP2_CM_CLKSTCTRL);
525 OMAP2_CM_CLKSTCTRL);
529 CM_AUTOIDLE1);
531 CM_AUTOIDLE2);
533 CM_AUTOIDLE3);
535 CM_AUTOIDLE);
537 CM_AUTOIDLE);
539 CM_AUTOIDLE);
541 CM_AUTOIDLE);
545 OMAP3430_CM_SLEEPDEP);
547 OMAP3430_CM_SLEEPDEP);
549 OMAP3430_CM_SLEEPDEP);
551 OMAP3430_CM_SLEEPDEP);
555 OMAP3_CM_CLKOUT_CTRL_OFFSET);
556 }
557 #endif