| blob | 647daf8e7291cf0562b3ad5bf72b8df424cab49f |
1 /*
2 * MPC8568E MDS Device Tree Source
3 *
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "MPC8568EMDS";
16 compatible = "MPC8568EMDS", "MPC85xxMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 ethernet3 = &enet3;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 rapidio0 = &rio0;
30 };
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
36 PowerPC,8568@0 {
37 device_type = "cpu";
38 reg = <0x0>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 sleep = <&pmc 0x00008000 // core
44 &pmc 0x00004000>; // timebase
45 timebase-frequency = <0>;
46 bus-frequency = <0>;
47 clock-frequency = <0>;
48 next-level-cache = <&L2>;
49 };
50 };
52 memory {
53 device_type = "memory";
54 reg = <0x0 0x10000000>;
55 };
57 localbus@e0005000 {
58 #address-cells = <2>;
59 #size-cells = <1>;
60 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus",
61 "simple-bus";
62 reg = <0xe0005000 0x1000>;
63 interrupt-parent = <&mpic>;
64 interrupts = <19 2>;
66 ranges = <0x0 0x0 0xfe000000 0x02000000
67 0x1 0x0 0xf8000000 0x00008000
68 0x2 0x0 0xf0000000 0x04000000
69 0x4 0x0 0xf8008000 0x00008000
70 0x5 0x0 0xf8010000 0x00008000>;
72 nor@0,0 {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 compatible = "cfi-flash";
76 reg = <0x0 0x0 0x02000000>;
77 bank-width = <2>;
78 device-width = <2>;
79 };
81 bcsr@1,0 {
82 #address-cells = <1>;
83 #size-cells = <1>;
84 compatible = "fsl,mpc8568mds-bcsr";
85 reg = <1 0 0x8000>;
86 ranges = <0 1 0 0x8000>;
88 bcsr5: gpio-controller@11 {
89 #gpio-cells = <2>;
90 compatible = "fsl,mpc8568mds-bcsr-gpio";
91 reg = <0x5 0x1>;
92 gpio-controller;
93 };
94 };
96 pib@4,0 {
97 compatible = "fsl,mpc8568mds-pib";
98 reg = <4 0 0x8000>;
99 };
101 pib@5,0 {
102 compatible = "fsl,mpc8568mds-pib";
103 reg = <5 0 0x8000>;
104 };
105 };
107 soc8568@e0000000 {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 device_type = "soc";
111 compatible = "simple-bus";
112 ranges = <0x0 0xe0000000 0x100000>;
113 bus-frequency = <0>;
115 ecm-law@0 {
116 compatible = "fsl,ecm-law";
117 reg = <0x0 0x1000>;
118 fsl,num-laws = <10>;
119 };
121 ecm@1000 {
122 compatible = "fsl,mpc8568-ecm", "fsl,ecm";
123 reg = <0x1000 0x1000>;
124 interrupts = <17 2>;
125 interrupt-parent = <&mpic>;
126 };
128 memory-controller@2000 {
129 compatible = "fsl,mpc8568-memory-controller";
130 reg = <0x2000 0x1000>;
131 interrupt-parent = <&mpic>;
132 interrupts = <18 2>;
133 };
135 L2: l2-cache-controller@20000 {
136 compatible = "fsl,mpc8568-l2-cache-controller";
137 reg = <0x20000 0x1000>;
138 cache-line-size = <32>; // 32 bytes
139 cache-size = <0x80000>; // L2, 512K
140 interrupt-parent = <&mpic>;
141 interrupts = <16 2>;
142 };
144 i2c-sleep-nexus {
145 #address-cells = <1>;
146 #size-cells = <1>;
147 compatible = "simple-bus";
148 sleep = <&pmc 0x00000004>;
149 ranges;
151 i2c@3000 {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 cell-index = <0>;
155 compatible = "fsl-i2c";
156 reg = <0x3000 0x100>;
157 interrupts = <43 2>;
158 interrupt-parent = <&mpic>;
159 dfsrr;
161 rtc@68 {
162 compatible = "dallas,ds1374";
163 reg = <0x68>;
164 interrupts = <3 1>;
165 interrupt-parent = <&mpic>;
166 };
167 };
169 i2c@3100 {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 cell-index = <1>;
173 compatible = "fsl-i2c";
174 reg = <0x3100 0x100>;
175 interrupts = <43 2>;
176 interrupt-parent = <&mpic>;
177 dfsrr;
178 };
179 };
181 dma@21300 {
182 #address-cells = <1>;
183 #size-cells = <1>;
184 compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
185 reg = <0x21300 0x4>;
186 ranges = <0x0 0x21100 0x200>;
187 cell-index = <0>;
188 sleep = <&pmc 0x00000400>;
190 dma-channel@0 {
191 compatible = "fsl,mpc8568-dma-channel",
192 "fsl,eloplus-dma-channel";
193 reg = <0x0 0x80>;
194 cell-index = <0>;
195 interrupt-parent = <&mpic>;
196 interrupts = <20 2>;
197 };
198 dma-channel@80 {
199 compatible = "fsl,mpc8568-dma-channel",
200 "fsl,eloplus-dma-channel";
201 reg = <0x80 0x80>;
202 cell-index = <1>;
203 interrupt-parent = <&mpic>;
204 interrupts = <21 2>;
205 };
206 dma-channel@100 {
207 compatible = "fsl,mpc8568-dma-channel",
208 "fsl,eloplus-dma-channel";
209 reg = <0x100 0x80>;
210 cell-index = <2>;
211 interrupt-parent = <&mpic>;
212 interrupts = <22 2>;
213 };
214 dma-channel@180 {
215 compatible = "fsl,mpc8568-dma-channel",
216 "fsl,eloplus-dma-channel";
217 reg = <0x180 0x80>;
218 cell-index = <3>;
219 interrupt-parent = <&mpic>;
220 interrupts = <23 2>;
221 };
222 };
224 enet0: ethernet@24000 {
225 #address-cells = <1>;
226 #size-cells = <1>;
227 cell-index = <0>;
228 device_type = "network";
229 model = "eTSEC";
230 compatible = "gianfar";
231 reg = <0x24000 0x1000>;
232 ranges = <0x0 0x24000 0x1000>;
233 local-mac-address = [ 00 00 00 00 00 00 ];
234 interrupts = <29 2 30 2 34 2>;
235 interrupt-parent = <&mpic>;
236 tbi-handle = <&tbi0>;
237 phy-handle = <&phy2>;
238 sleep = <&pmc 0x00000080>;
240 mdio@520 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,gianfar-mdio";
244 reg = <0x520 0x20>;
246 phy0: ethernet-phy@7 {
247 interrupt-parent = <&mpic>;
248 interrupts = <1 1>;
249 reg = <0x7>;
250 device_type = "ethernet-phy";
251 };
252 phy1: ethernet-phy@1 {
253 interrupt-parent = <&mpic>;
254 interrupts = <2 1>;
255 reg = <0x1>;
256 device_type = "ethernet-phy";
257 };
258 phy2: ethernet-phy@2 {
259 interrupt-parent = <&mpic>;
260 interrupts = <1 1>;
261 reg = <0x2>;
262 device_type = "ethernet-phy";
263 };
264 phy3: ethernet-phy@3 {
265 interrupt-parent = <&mpic>;
266 interrupts = <2 1>;
267 reg = <0x3>;
268 device_type = "ethernet-phy";
269 };
270 tbi0: tbi-phy@11 {
271 reg = <0x11>;
272 device_type = "tbi-phy";
273 };
274 };
275 };
277 enet1: ethernet@25000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 cell-index = <1>;
281 device_type = "network";
282 model = "eTSEC";
283 compatible = "gianfar";
284 reg = <0x25000 0x1000>;
285 ranges = <0x0 0x25000 0x1000>;
286 local-mac-address = [ 00 00 00 00 00 00 ];
287 interrupts = <35 2 36 2 40 2>;
288 interrupt-parent = <&mpic>;
289 tbi-handle = <&tbi1>;
290 phy-handle = <&phy3>;
291 sleep = <&pmc 0x00000040>;
293 mdio@520 {
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "fsl,gianfar-tbi";
297 reg = <0x520 0x20>;
299 tbi1: tbi-phy@11 {
300 reg = <0x11>;
301 device_type = "tbi-phy";
302 };
303 };
304 };
306 duart-sleep-nexus {
307 #address-cells = <1>;
308 #size-cells = <1>;
309 compatible = "simple-bus";
310 sleep = <&pmc 0x00000002>;
311 ranges;
313 serial0: serial@4500 {
314 cell-index = <0>;
315 device_type = "serial";
316 compatible = "ns16550";
317 reg = <0x4500 0x100>;
318 clock-frequency = <0>;
319 interrupts = <42 2>;
320 interrupt-parent = <&mpic>;
321 };
323 serial1: serial@4600 {
324 cell-index = <1>;
325 device_type = "serial";
326 compatible = "ns16550";
327 reg = <0x4600 0x100>;
328 clock-frequency = <0>;
329 interrupts = <42 2>;
330 interrupt-parent = <&mpic>;
331 };
332 };
334 global-utilities@e0000 {
335 #address-cells = <1>;
336 #size-cells = <1>;
337 compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
338 reg = <0xe0000 0x1000>;
339 ranges = <0 0xe0000 0x1000>;
340 fsl,has-rstcr;
342 pmc: power@70 {
343 compatible = "fsl,mpc8568-pmc",
344 "fsl,mpc8548-pmc";
345 reg = <0x70 0x20>;
346 };
347 };
349 crypto@30000 {
350 compatible = "fsl,sec2.1", "fsl,sec2.0";
351 reg = <0x30000 0x10000>;
352 interrupts = <45 2>;
353 interrupt-parent = <&mpic>;
354 fsl,num-channels = <4>;
355 fsl,channel-fifo-len = <24>;
356 fsl,exec-units-mask = <0xfe>;
357 fsl,descriptor-types-mask = <0x12b0ebf>;
358 sleep = <&pmc 0x01000000>;
359 };
361 mpic: pic@40000 {
362 interrupt-controller;
363 #address-cells = <0>;
364 #interrupt-cells = <2>;
365 reg = <0x40000 0x40000>;
366 compatible = "chrp,open-pic";
367 device_type = "open-pic";
368 };
370 msi@41600 {
371 compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
372 reg = <0x41600 0x80>;
373 msi-available-ranges = <0 0x100>;
374 interrupts = <
375 0xe0 0
376 0xe1 0
377 0xe2 0
378 0xe3 0
379 0xe4 0
380 0xe5 0
381 0xe6 0
382 0xe7 0>;
383 interrupt-parent = <&mpic>;
384 };
386 par_io@e0100 {
387 reg = <0xe0100 0x100>;
388 device_type = "par_io";
389 num-ports = <7>;
391 pio1: ucc_pin@01 {
392 pio-map = <
393 /* port pin dir open_drain assignment has_irq */
394 0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
395 0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
396 0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
397 0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
398 0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
399 0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
400 0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
401 0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
402 0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
403 0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
404 0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
405 0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
406 0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
407 0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
408 0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
409 0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
410 0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
411 0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
412 0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
413 0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
414 0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
415 0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
416 0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
417 };
419 pio2: ucc_pin@02 {
420 pio-map = <
421 /* port pin dir open_drain assignment has_irq */
422 0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
423 0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
424 0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
425 0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
426 0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
427 0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
428 0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
429 0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
430 0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
431 0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
432 0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
433 0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
434 0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
435 0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
436 0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
437 0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
438 0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
439 0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
440 0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
441 0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
442 0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
443 0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
444 0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
445 0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
446 0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
447 };
448 };
449 };
451 qe@e0080000 {
452 #address-cells = <1>;
453 #size-cells = <1>;
454 device_type = "qe";
455 compatible = "fsl,qe";
456 ranges = <0x0 0xe0080000 0x40000>;
457 reg = <0xe0080000 0x480>;
458 sleep = <&pmc 0x00000800>;
459 brg-frequency = <0>;
460 bus-frequency = <396000000>;
461 fsl,qe-num-riscs = <2>;
462 fsl,qe-num-snums = <28>;
464 muram@10000 {
465 #address-cells = <1>;
466 #size-cells = <1>;
467 compatible = "fsl,qe-muram", "fsl,cpm-muram";
468 ranges = <0x0 0x10000 0x10000>;
470 data-only@0 {
471 compatible = "fsl,qe-muram-data",
472 "fsl,cpm-muram-data";
473 reg = <0x0 0x10000>;
474 };
475 };
477 spi@4c0 {
478 cell-index = <0>;
479 compatible = "fsl,spi";
480 reg = <0x4c0 0x40>;
481 interrupts = <2>;
482 interrupt-parent = <&qeic>;
483 mode = "cpu";
484 };
486 spi@500 {
487 cell-index = <1>;
488 compatible = "fsl,spi";
489 reg = <0x500 0x40>;
490 interrupts = <1>;
491 interrupt-parent = <&qeic>;
492 mode = "cpu";
493 };
495 enet2: ucc@2000 {
496 device_type = "network";
497 compatible = "ucc_geth";
498 cell-index = <1>;
499 reg = <0x2000 0x200>;
500 interrupts = <32>;
501 interrupt-parent = <&qeic>;
502 local-mac-address = [ 00 00 00 00 00 00 ];
503 rx-clock-name = "none";
504 tx-clock-name = "clk16";
505 pio-handle = <&pio1>;
506 phy-handle = <&phy0>;
507 phy-connection-type = "rgmii-id";
508 };
510 enet3: ucc@3000 {
511 device_type = "network";
512 compatible = "ucc_geth";
513 cell-index = <2>;
514 reg = <0x3000 0x200>;
515 interrupts = <33>;
516 interrupt-parent = <&qeic>;
517 local-mac-address = [ 00 00 00 00 00 00 ];
518 rx-clock-name = "none";
519 tx-clock-name = "clk16";
520 pio-handle = <&pio2>;
521 phy-handle = <&phy1>;
522 phy-connection-type = "rgmii-id";
523 };
525 mdio@2120 {
526 #address-cells = <1>;
527 #size-cells = <0>;
528 reg = <0x2120 0x18>;
529 compatible = "fsl,ucc-mdio";
531 /* These are the same PHYs as on
532 * gianfar's MDIO bus */
533 qe_phy0: ethernet-phy@07 {
534 interrupt-parent = <&mpic>;
535 interrupts = <1 1>;
536 reg = <0x7>;
537 device_type = "ethernet-phy";
538 };
539 qe_phy1: ethernet-phy@01 {
540 interrupt-parent = <&mpic>;
541 interrupts = <2 1>;
542 reg = <0x1>;
543 device_type = "ethernet-phy";
544 };
545 qe_phy2: ethernet-phy@02 {
546 interrupt-parent = <&mpic>;
547 interrupts = <1 1>;
548 reg = <0x2>;
549 device_type = "ethernet-phy";
550 };
551 qe_phy3: ethernet-phy@03 {
552 interrupt-parent = <&mpic>;
553 interrupts = <2 1>;
554 reg = <0x3>;
555 device_type = "ethernet-phy";
556 };
557 };
559 qeic: interrupt-controller@80 {
560 interrupt-controller;
561 compatible = "fsl,qe-ic";
562 #address-cells = <0>;
563 #interrupt-cells = <1>;
564 reg = <0x80 0x80>;
565 big-endian;
566 interrupts = <46 2 46 2>; //high:30 low:30
567 interrupt-parent = <&mpic>;
568 };
570 };
572 pci0: pci@e0008000 {
573 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
574 interrupt-map = <
575 /* IDSEL 0x12 AD18 */
576 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
577 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
578 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
579 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
581 /* IDSEL 0x13 AD19 */
582 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
583 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
584 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
585 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
587 interrupt-parent = <&mpic>;
588 interrupts = <24 2>;
589 bus-range = <0 255>;
590 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
591 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
592 sleep = <&pmc 0x80000000>;
593 clock-frequency = <66666666>;
594 #interrupt-cells = <1>;
595 #size-cells = <2>;
596 #address-cells = <3>;
597 reg = <0xe0008000 0x1000>;
598 compatible = "fsl,mpc8540-pci";
599 device_type = "pci";
600 };
602 /* PCI Express */
603 pci1: pcie@e000a000 {
604 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
605 interrupt-map = <
607 /* IDSEL 0x0 (PEX) */
608 00000 0x0 0x0 0x1 &mpic 0x0 0x1
609 00000 0x0 0x0 0x2 &mpic 0x1 0x1
610 00000 0x0 0x0 0x3 &mpic 0x2 0x1
611 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
613 interrupt-parent = <&mpic>;
614 interrupts = <26 2>;
615 bus-range = <0 255>;
616 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
617 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
618 sleep = <&pmc 0x20000000>;
619 clock-frequency = <33333333>;
620 #interrupt-cells = <1>;
621 #size-cells = <2>;
622 #address-cells = <3>;
623 reg = <0xe000a000 0x1000>;
624 compatible = "fsl,mpc8548-pcie";
625 device_type = "pci";
626 pcie@0 {
627 reg = <0x0 0x0 0x0 0x0 0x0>;
628 #size-cells = <2>;
629 #address-cells = <3>;
630 device_type = "pci";
631 ranges = <0x2000000 0x0 0xa0000000
632 0x2000000 0x0 0xa0000000
633 0x0 0x10000000
635 0x1000000 0x0 0x0
636 0x1000000 0x0 0x0
637 0x0 0x800000>;
638 };
639 };
641 rio0: rapidio@e00c00000 {
642 #address-cells = <2>;
643 #size-cells = <2>;
644 compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta";
645 reg = <0xe00c0000 0x20000>;
646 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
647 interrupts = <48 2 /* error */
648 49 2 /* bell_outb */
649 50 2 /* bell_inb */
650 53 2 /* msg1_tx */
651 54 2 /* msg1_rx */
652 55 2 /* msg2_tx */
653 56 2 /* msg2_rx */>;
654 interrupt-parent = <&mpic>;
655 sleep = <&pmc 0x00080000 /* controller */
656 &pmc 0x00040000>; /* message unit */
657 };
659 leds {
660 compatible = "gpio-leds";
662 green {
663 gpios = <&bcsr5 1 0>;
664 };
666 amber {
667 gpios = <&bcsr5 2 0>;
668 };
670 red {
671 gpios = <&bcsr5 3 0>;
672 };
673 };
674 };