| blob | e7b477f6a3fea32d68aaceb623469c9f8bd0053a |
1 /*
2 * MPC8572 DS Core1 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi.
7 *
8 * Please note to add "-b 1" for core1's dts compiling.
9 *
10 * Copyright 2007-2009 Freescale Semiconductor Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
18 /dts-v1/;
19 / {
20 model = "fsl,MPC8572DS";
21 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
22 #address-cells = <1>;
23 #size-cells = <1>;
25 aliases {
26 ethernet2 = &enet2;
27 ethernet3 = &enet3;
28 serial0 = &serial0;
29 pci2 = &pci2;
30 };
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
36 PowerPC,8572@1 {
37 device_type = "cpu";
38 reg = <0x1>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>;
44 bus-frequency = <0>;
45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
47 };
48 };
50 memory {
51 device_type = "memory";
52 reg = <0x0 0x0>; // Filled by U-Boot
53 };
55 soc8572@ffe00000 {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 device_type = "soc";
59 compatible = "simple-bus";
60 ranges = <0x0 0xffe00000 0x100000>;
61 bus-frequency = <0>; // Filled out by uboot.
63 L2: l2-cache-controller@20000 {
64 compatible = "fsl,mpc8572-l2-cache-controller";
65 reg = <0x20000 0x1000>;
66 cache-line-size = <32>; // 32 bytes
67 cache-size = <0x80000>; // L2, 512K
68 interrupt-parent = <&mpic>;
69 };
71 dma@c300 {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
75 reg = <0xc300 0x4>;
76 ranges = <0x0 0xc100 0x200>;
77 cell-index = <0>;
78 dma-channel@0 {
79 compatible = "fsl,mpc8572-dma-channel",
80 "fsl,eloplus-dma-channel";
81 reg = <0x0 0x80>;
82 cell-index = <0>;
83 interrupt-parent = <&mpic>;
84 interrupts = <76 2>;
85 };
86 dma-channel@80 {
87 compatible = "fsl,mpc8572-dma-channel",
88 "fsl,eloplus-dma-channel";
89 reg = <0x80 0x80>;
90 cell-index = <1>;
91 interrupt-parent = <&mpic>;
92 interrupts = <77 2>;
93 };
94 dma-channel@100 {
95 compatible = "fsl,mpc8572-dma-channel",
96 "fsl,eloplus-dma-channel";
97 reg = <0x100 0x80>;
98 cell-index = <2>;
99 interrupt-parent = <&mpic>;
100 interrupts = <78 2>;
101 };
102 dma-channel@180 {
103 compatible = "fsl,mpc8572-dma-channel",
104 "fsl,eloplus-dma-channel";
105 reg = <0x180 0x80>;
106 cell-index = <3>;
107 interrupt-parent = <&mpic>;
108 interrupts = <79 2>;
109 };
110 };
112 mdio@24520 {
113 #address-cells = <1>;
114 #size-cells = <0>;
115 compatible = "fsl,gianfar-mdio";
116 reg = <0x24520 0x20>;
118 phy2: ethernet-phy@2 {
119 interrupt-parent = <&mpic>;
120 reg = <0x2>;
121 };
122 phy3: ethernet-phy@3 {
123 interrupt-parent = <&mpic>;
124 reg = <0x3>;
125 };
126 };
128 enet2: ethernet@26000 {
129 cell-index = <2>;
130 device_type = "network";
131 model = "eTSEC";
132 compatible = "gianfar";
133 reg = <0x26000 0x1000>;
134 local-mac-address = [ 00 00 00 00 00 00 ];
135 interrupts = <31 2 32 2 33 2>;
136 interrupt-parent = <&mpic>;
137 phy-handle = <&phy2>;
138 phy-connection-type = "rgmii-id";
139 };
141 enet3: ethernet@27000 {
142 cell-index = <3>;
143 device_type = "network";
144 model = "eTSEC";
145 compatible = "gianfar";
146 reg = <0x27000 0x1000>;
147 local-mac-address = [ 00 00 00 00 00 00 ];
148 interrupts = <37 2 38 2 39 2>;
149 interrupt-parent = <&mpic>;
150 phy-handle = <&phy3>;
151 phy-connection-type = "rgmii-id";
152 };
154 msi@41600 {
155 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
156 reg = <0x41600 0x80>;
157 msi-available-ranges = <0x80 0x80>;
158 interrupts = <
159 0xe4 0
160 0xe5 0
161 0xe6 0
162 0xe7 0>;
163 interrupt-parent = <&mpic>;
164 };
166 serial0: serial@4600 {
167 cell-index = <1>;
168 device_type = "serial";
169 compatible = "ns16550";
170 reg = <0x4600 0x100>;
171 clock-frequency = <0>;
172 };
174 mpic: pic@40000 {
175 interrupt-controller;
176 #address-cells = <0>;
177 #interrupt-cells = <2>;
178 reg = <0x40000 0x40000>;
179 compatible = "chrp,open-pic";
180 device_type = "open-pic";
181 protected-sources = <
182 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
183 29 30 34 35 36 40 /* enet0 enet1 */
184 24 25 20 21 22 23 /* pci0 pci1 dma1 */
185 43 /* i2c */
186 0x1 0x2 0x3 0x4 /* pci slot */
187 0x9 0xa 0xb 0xc /* usb */
188 0x6 0x7 0xe 0x5 /* Audio elgacy SATA */
189 0xe0 0xe1 0xe2 0xe3 /* msi */
190 >;
191 };
192 };
194 pci2: pcie@ffe0a000 {
195 compatible = "fsl,mpc8548-pcie";
196 device_type = "pci";
197 #interrupt-cells = <1>;
198 #size-cells = <2>;
199 #address-cells = <3>;
200 reg = <0xffe0a000 0x1000>;
201 bus-range = <0 255>;
202 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
203 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
204 clock-frequency = <33333333>;
205 interrupt-parent = <&mpic>;
206 interrupts = <26 2>;
207 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
208 interrupt-map = <
209 /* IDSEL 0x0 */
210 0000 0x0 0x0 0x1 &mpic 0x0 0x1
211 0000 0x0 0x0 0x2 &mpic 0x1 0x1
212 0000 0x0 0x0 0x3 &mpic 0x2 0x1
213 0000 0x0 0x0 0x4 &mpic 0x3 0x1
214 >;
215 pcie@0 {
216 reg = <0x0 0x0 0x0 0x0 0x0>;
217 #size-cells = <2>;
218 #address-cells = <3>;
219 device_type = "pci";
220 ranges = <0x2000000 0x0 0xc0000000
221 0x2000000 0x0 0xc0000000
222 0x0 0x20000000
224 0x1000000 0x0 0x0
225 0x1000000 0x0 0x0
226 0x0 0x10000>;
227 };
228 };
229 };