pinctrl: make a copy of pinmux map
[linux/fpc-iii.git] / arch / powerpc / boot / dts / p1020rdb_camp_core0.dts
blobf0bf7f42f097c8dbe535898bd56548080dd691b0
1 /*
2  * P1020 RDB  Core0 Device Tree Source in CAMP mode.
3  *
4  * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5  * can be shared, all the other devices must be assigned to one core only.
6  * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
7  * eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
8  *
9  * Please note to add "-b 0" for core0's dts compiling.
10  *
11  * Copyright 2011 Freescale Semiconductor Inc.
12  *
13  * This program is free software; you can redistribute  it and/or modify it
14  * under  the terms of  the GNU General  Public License as published by the
15  * Free Software Foundation;  either version 2 of the  License, or (at your
16  * option) any later version.
17  */
19 /include/ "p1020si.dtsi"
21 / {
22         model = "fsl,P1020RDB";
23         compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
25         aliases {
26                 ethernet1 = &enet1;
27                 ethernet2 = &enet2;
28                 serial0 = &serial0;
29                 pci0 = &pci0;
30                 pci1 = &pci1;
31         };
33         cpus {
34                 PowerPC,P1020@1 {
35                 status = "disabled";
36                 };
37         };
39         memory {
40                 device_type = "memory";
41         };
43         localbus@ffe05000 {
44                 status = "disabled";
45         };
47         soc@ffe00000 {
48                 i2c@3000 {
49                         rtc@68 {
50                                 compatible = "dallas,ds1339";
51                                 reg = <0x68>;
52                         };
53                 };
55                 serial1: serial@4600 {
56                         status = "disabled";
57                 };
59                 spi@7000 {
60                         fsl_m25p80@0 {
61                                 #address-cells = <1>;
62                                 #size-cells = <1>;
63                                 compatible = "fsl,espi-flash";
64                                 reg = <0>;
65                                 linux,modalias = "fsl_m25p80";
66                                 spi-max-frequency = <40000000>;
68                                 partition@0 {
69                                         /* 512KB for u-boot Bootloader Image */
70                                         reg = <0x0 0x00080000>;
71                                         label = "SPI (RO) U-Boot Image";
72                                         read-only;
73                                 };
75                                 partition@80000 {
76                                         /* 512KB for DTB Image */
77                                         reg = <0x00080000 0x00080000>;
78                                         label = "SPI (RO) DTB Image";
79                                         read-only;
80                                 };
82                                 partition@100000 {
83                                         /* 4MB for Linux Kernel Image */
84                                         reg = <0x00100000 0x00400000>;
85                                         label = "SPI (RO) Linux Kernel Image";
86                                         read-only;
87                                 };
89                                 partition@500000 {
90                                         /* 4MB for Compressed RFS Image */
91                                         reg = <0x00500000 0x00400000>;
92                                         label = "SPI (RO) Compressed RFS Image";
93                                         read-only;
94                                 };
96                                 partition@900000 {
97                                         /* 7MB for JFFS2 based RFS */
98                                         reg = <0x00900000 0x00700000>;
99                                         label = "SPI (RW) JFFS2 RFS";
100                                 };
101                         };
102                 };
104                 mdio@24000 {
105                         phy0: ethernet-phy@0 {
106                                 interrupt-parent = <&mpic>;
107                                 interrupts = <3 1>;
108                                 reg = <0x0>;
109                         };
110                         phy1: ethernet-phy@1 {
111                                 interrupt-parent = <&mpic>;
112                                 interrupts = <2 1>;
113                                 reg = <0x1>;
114                         };
115                 };
117                 mdio@25000 {
118                         tbi0: tbi-phy@11 {
119                                 reg = <0x11>;
120                                 device_type = "tbi-phy";
121                         };
122                 };
124                 enet0: ethernet@b0000 {
125                         status = "disabled";
126                 };
128                 enet1: ethernet@b1000 {
129                         phy-handle = <&phy0>;
130                         tbi-handle = <&tbi0>;
131                         phy-connection-type = "sgmii";
132                 };
134                 enet2: ethernet@b2000 {
135                         phy-handle = <&phy1>;
136                         phy-connection-type = "rgmii-id";
137                 };
139                 usb@22000 {
140                         phy_type = "ulpi";
141                 };
143                 /* USB2 is shared with localbus, so it must be disabled
144                    by default. We can't put 'status = "disabled";' here
145                    since U-Boot doesn't clear the status property when
146                    it enables USB2. OTOH, U-Boot does create a new node
147                    when there isn't any. So, just comment it out.
148                 usb@23000 {
149                         phy_type = "ulpi";
150                 };
151                 */
153                 mpic: pic@40000 {
154                         protected-sources = <
155                         42 29 30 34     /* serial1, enet0-queue-group0 */
156                         17 18 24 45     /* enet0-queue-group1, crypto */
157                         >;
158                 };
160         };
162         pci0: pcie@ffe09000 {
163                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
164                           0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
165                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
166                 interrupt-map = <
167                         /* IDSEL 0x0 */
168                         0000 0x0 0x0 0x1 &mpic 0x4 0x1
169                         0000 0x0 0x0 0x2 &mpic 0x5 0x1
170                         0000 0x0 0x0 0x3 &mpic 0x6 0x1
171                         0000 0x0 0x0 0x4 &mpic 0x7 0x1
172                         >;
173                 pcie@0 {
174                         reg = <0x0 0x0 0x0 0x0 0x0>;
175                         #size-cells = <2>;
176                         #address-cells = <3>;
177                         device_type = "pci";
178                         ranges = <0x2000000 0x0 0xa0000000
179                                   0x2000000 0x0 0xa0000000
180                                   0x0 0x20000000
182                                   0x1000000 0x0 0x0
183                                   0x1000000 0x0 0x0
184                                   0x0 0x100000>;
185                 };
186         };
188         pci1: pcie@ffe0a000 {
189                 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
190                           0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
191                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
192                 interrupt-map = <
193                         /* IDSEL 0x0 */
194                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
195                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
196                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
197                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
198                         >;
199                 pcie@0 {
200                         reg = <0x0 0x0 0x0 0x0 0x0>;
201                         #size-cells = <2>;
202                         #address-cells = <3>;
203                         device_type = "pci";
204                         ranges = <0x2000000 0x0 0x80000000
205                                   0x2000000 0x0 0x80000000
206                                   0x0 0x20000000
208                                   0x1000000 0x0 0x0
209                                   0x1000000 0x0 0x0
210                                   0x0 0x100000>;
211                 };
212         };