arch/powerpc/boot/dts/p2020ds.dts

   1 /*
   2  * P2020 DS Device Tree Source
   3  *
   4  * Copyright 2009-2011 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /include/ "p2020si.dtsi"
  13
  14 / {
  15         model = "fsl,P2020DS";
  16         compatible = "fsl,P2020DS";
  17
  18         aliases {
  19                 ethernet0 = &enet0;
  20                 ethernet1 = &enet1;
  21                 ethernet2 = &enet2;
  22                 serial0 = &serial0;
  23                 serial1 = &serial1;
  24                 pci0 = &pci0;
  25                 pci1 = &pci1;
  26                 pci2 = &pci2;
  27         };
  28
  29
  30         memory {
  31                 device_type = "memory";
  32         };
  33
  34         localbus@ffe05000 {
  35                 compatible = "fsl,elbc", "simple-bus";
  36                 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
  37                           0x1 0x0 0x0 0xe0000000 0x08000000
  38                           0x2 0x0 0x0 0xffa00000 0x00040000
  39                           0x3 0x0 0x0 0xffdf0000 0x00008000
  40                           0x4 0x0 0x0 0xffa40000 0x00040000
  41                           0x5 0x0 0x0 0xffa80000 0x00040000
  42                           0x6 0x0 0x0 0xffac0000 0x00040000>;
  43
  44                 nor@0,0 {
  45                         #address-cells = <1>;
  46                         #size-cells = <1>;
  47                         compatible = "cfi-flash";
  48                         reg = <0x0 0x0 0x8000000>;
  49                         bank-width = <2>;
  50                         device-width = <1>;
  51
  52                         ramdisk@0 {
  53                                 reg = <0x0 0x03000000>;
  54                                 read-only;
  55                         };
  56
  57                         diagnostic@3000000 {
  58                                 reg = <0x03000000 0x00e00000>;
  59                                 read-only;
  60                         };
  61
  62                         dink@3e00000 {
  63                                 reg = <0x03e00000 0x00200000>;
  64                                 read-only;
  65                         };
  66
  67                         kernel@4000000 {
  68                                 reg = <0x04000000 0x00400000>;
  69                                 read-only;
  70                         };
  71
  72                         jffs2@4400000 {
  73                                 reg = <0x04400000 0x03b00000>;
  74                         };
  75
  76                         dtb@7f00000 {
  77                                 reg = <0x07f00000 0x00080000>;
  78                                 read-only;
  79                         };
  80
  81                         u-boot@7f80000 {
  82                                 reg = <0x07f80000 0x00080000>;
  83                                 read-only;
  84                         };
  85                 };
  86
  87                 nand@2,0 {
  88                         #address-cells = <1>;
  89                         #size-cells = <1>;
  90                         compatible = "fsl,elbc-fcm-nand";
  91                         reg = <0x2 0x0 0x40000>;
  92
  93                         u-boot@0 {
  94                                 reg = <0x0 0x02000000>;
  95                                 read-only;
  96                         };
  97
  98                         jffs2@2000000 {
  99                                 reg = <0x02000000 0x10000000>;
 100                         };
 101
 102                         ramdisk@12000000 {
 103                                 reg = <0x12000000 0x08000000>;
 104                                 read-only;
 105                         };
 106
 107                         kernel@1a000000 {
 108                                 reg = <0x1a000000 0x04000000>;
 109                         };
 110
 111                         dtb@1e000000 {
 112                                 reg = <0x1e000000 0x01000000>;
 113                                 read-only;
 114                         };
 115
 116                         empty@1f000000 {
 117                                 reg = <0x1f000000 0x21000000>;
 118                         };
 119                 };
 120
 121                 board-control@3,0 {
 122                         compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
 123                         reg = <0x3 0x0 0x30>;
 124                 };
 125
 126                 nand@4,0 {
 127                         compatible = "fsl,elbc-fcm-nand";
 128                         reg = <0x4 0x0 0x40000>;
 129                 };
 130
 131                 nand@5,0 {
 132                         compatible = "fsl,elbc-fcm-nand";
 133                         reg = <0x5 0x0 0x40000>;
 134                 };
 135
 136                 nand@6,0 {
 137                         compatible = "fsl,elbc-fcm-nand";
 138                         reg = <0x6 0x0 0x40000>;
 139                 };
 140         };
 141
 142         soc@ffe00000 {
 143
 144                 usb@22000 {
 145                         phy_type = "ulpi";
 146                 };
 147
 148                 mdio@24520 {
 149                         phy0: ethernet-phy@0 {
 150                                 interrupt-parent = <&mpic>;
 151                                 interrupts = <3 1>;
 152                                 reg = <0x0>;
 153                         };
 154                         phy1: ethernet-phy@1 {
 155                                 interrupt-parent = <&mpic>;
 156                                 interrupts = <3 1>;
 157                                 reg = <0x1>;
 158                         };
 159                         phy2: ethernet-phy@2 {
 160                                 interrupt-parent = <&mpic>;
 161                                 interrupts = <3 1>;
 162                                 reg = <0x2>;
 163                         };
 164                         tbi0: tbi-phy@11 {
 165                                 reg = <0x11>;
 166                                 device_type = "tbi-phy";
 167                         };
 168
 169                 };
 170
 171                 mdio@25520 {
 172                         tbi1: tbi-phy@11 {
 173                                 reg = <0x11>;
 174                                 device_type = "tbi-phy";
 175                         };
 176                 };
 177
 178                 mdio@26520 {
 179                         tbi2: tbi-phy@11 {
 180                                 reg = <0x11>;
 181                                 device_type = "tbi-phy";
 182                         };
 183
 184                 };
 185
 186                 ptp_clock@24E00 {
 187                         compatible = "fsl,etsec-ptp";
 188                         reg = <0x24E00 0xB0>;
 189                         interrupts = <68 2 69 2 70 2>;
 190                         interrupt-parent = < &mpic >;
 191                         fsl,tclk-period = <5>;
 192                         fsl,tmr-prsc = <200>;
 193                         fsl,tmr-add = <0xCCCCCCCD>;
 194                         fsl,tmr-fiper1 = <0x3B9AC9FB>;
 195                         fsl,tmr-fiper2 = <0x0001869B>;
 196                         fsl,max-adj = <249999999>;
 197                 };
 198
 199                 enet0: ethernet@24000 {
 200                         tbi-handle = <&tbi0>;
 201                         phy-handle = <&phy0>;
 202                         phy-connection-type = "rgmii-id";
 203                 };
 204
 205                 enet1: ethernet@25000 {
 206                         tbi-handle = <&tbi1>;
 207                         phy-handle = <&phy1>;
 208                         phy-connection-type = "rgmii-id";
 209
 210                 };
 211
 212                 enet2: ethernet@26000 {
 213                         tbi-handle = <&tbi2>;
 214                         phy-handle = <&phy2>;
 215                         phy-connection-type = "rgmii-id";
 216                 };
 217
 218
 219                 msi@41600 {
 220                         compatible = "fsl,mpic-msi";
 221                 };
 222         };
 223
 224         pci0: pcie@ffe08000 {
 225                 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
 226                           0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
 227                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 228                 interrupt-map = <
 229                         /* IDSEL 0x0 */
 230                         0000 0x0 0x0 0x1 &mpic 0x8 0x1
 231                         0000 0x0 0x0 0x2 &mpic 0x9 0x1
 232                         0000 0x0 0x0 0x3 &mpic 0xa 0x1
 233                         0000 0x0 0x0 0x4 &mpic 0xb 0x1
 234                         >;
 235                 pcie@0 {
 236                         reg = <0x0 0x0 0x0 0x0 0x0>;
 237                         #size-cells = <2>;
 238                         #address-cells = <3>;
 239                         device_type = "pci";
 240                         ranges = <0x2000000 0x0 0x80000000
 241                                   0x2000000 0x0 0x80000000
 242                                   0x0 0x20000000
 243
 244                                   0x1000000 0x0 0x0
 245                                   0x1000000 0x0 0x0
 246                                   0x0 0x10000>;
 247                 };
 248         };
 249
 250         pci1: pcie@ffe09000 {
 251                 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
 252                           0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
 253                 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
 254                 interrupt-map = <
 255
 256                         // IDSEL 0x11 func 0 - PCI slot 1
 257                         0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
 258                         0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
 259
 260                         // IDSEL 0x11 func 1 - PCI slot 1
 261                         0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
 262                         0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
 263
 264                         // IDSEL 0x11 func 2 - PCI slot 1
 265                         0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
 266                         0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
 267
 268                         // IDSEL 0x11 func 3 - PCI slot 1
 269                         0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
 270                         0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
 271
 272                         // IDSEL 0x11 func 4 - PCI slot 1
 273                         0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
 274                         0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
 275
 276                         // IDSEL 0x11 func 5 - PCI slot 1
 277                         0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
 278                         0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
 279
 280                         // IDSEL 0x11 func 6 - PCI slot 1
 281                         0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
 282                         0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
 283
 284                         // IDSEL 0x11 func 7 - PCI slot 1
 285                         0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
 286                         0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
 287
 288                         // IDSEL 0x1d  Audio
 289                         0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
 290
 291                         // IDSEL 0x1e Legacy
 292                         0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
 293                         0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
 294
 295                         // IDSEL 0x1f IDE/SATA
 296                         0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
 297                         0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
 298                         >;
 299
 300                 pcie@0 {
 301                         reg = <0x0 0x0 0x0 0x0 0x0>;
 302                         #size-cells = <2>;
 303                         #address-cells = <3>;
 304                         device_type = "pci";
 305                         ranges = <0x2000000 0x0 0xa0000000
 306                                   0x2000000 0x0 0xa0000000
 307                                   0x0 0x20000000
 308
 309                                   0x1000000 0x0 0x0
 310                                   0x1000000 0x0 0x0
 311                                   0x0 0x10000>;
 312                         uli1575@0 {
 313                                 reg = <0x0 0x0 0x0 0x0 0x0>;
 314                                 #size-cells = <2>;
 315                                 #address-cells = <3>;
 316                                 ranges = <0x2000000 0x0 0xa0000000
 317                                           0x2000000 0x0 0xa0000000
 318                                           0x0 0x20000000
 319
 320                                           0x1000000 0x0 0x0
 321                                           0x1000000 0x0 0x0
 322                                           0x0 0x10000>;
 323                                 isa@1e {
 324                                         device_type = "isa";
 325                                         #interrupt-cells = <2>;
 326                                         #size-cells = <1>;
 327                                         #address-cells = <2>;
 328                                         reg = <0xf000 0x0 0x0 0x0 0x0>;
 329                                         ranges = <0x1 0x0 0x1000000 0x0 0x0
 330                                                   0x1000>;
 331                                         interrupt-parent = <&i8259>;
 332
 333                                         i8259: interrupt-controller@20 {
 334                                                 reg = <0x1 0x20 0x2
 335                                                        0x1 0xa0 0x2
 336                                                        0x1 0x4d0 0x2>;
 337                                                 interrupt-controller;
 338                                                 device_type = "interrupt-controller";
 339                                                 #address-cells = <0>;
 340                                                 #interrupt-cells = <2>;
 341                                                 compatible = "chrp,iic";
 342                                                 interrupts = <4 1>;
 343                                                 interrupt-parent = <&mpic>;
 344                                         };
 345
 346                                         i8042@60 {
 347                                                 #size-cells = <0>;
 348                                                 #address-cells = <1>;
 349                                                 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
 350                                                 interrupts = <1 3 12 3>;
 351                                                 interrupt-parent =
 352                                                         <&i8259>;
 353
 354                                                 keyboard@0 {
 355                                                         reg = <0x0>;
 356                                                         compatible = "pnpPNP,303";
 357                                                 };
 358
 359                                                 mouse@1 {
 360                                                         reg = <0x1>;
 361                                                         compatible = "pnpPNP,f03";
 362                                                 };
 363                                         };
 364
 365                                         rtc@70 {
 366                                                 compatible = "pnpPNP,b00";
 367                                                 reg = <0x1 0x70 0x2>;
 368                                         };
 369
 370                                         gpio@400 {
 371                                                 reg = <0x1 0x400 0x80>;
 372                                         };
 373                                 };
 374                         };
 375                 };
 376
 377         };
 378
 379         pci2: pcie@ffe0a000 {
 380                 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
 381                           0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
 382                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 383                 interrupt-map = <
 384                         /* IDSEL 0x0 */
 385                         0000 0x0 0x0 0x1 &mpic 0x0 0x1
 386                         0000 0x0 0x0 0x2 &mpic 0x1 0x1
 387                         0000 0x0 0x0 0x3 &mpic 0x2 0x1
 388                         0000 0x0 0x0 0x4 &mpic 0x3 0x1
 389                         >;
 390                 pcie@0 {
 391                         reg = <0x0 0x0 0x0 0x0 0x0>;
 392                         #size-cells = <2>;
 393                         #address-cells = <3>;
 394                         device_type = "pci";
 395                         ranges = <0x2000000 0x0 0xc0000000
 396                                   0x2000000 0x0 0xc0000000
 397                                   0x0 0x20000000
 398
 399                                   0x1000000 0x0 0x0
 400                                   0x1000000 0x0 0x0
 401                                   0x0 0x10000>;
 402                 };
 403         };
 404 };