| blob | b725dab0f88a01eae1e085e094310e21d898e605 |
1 /*
2 * Kernel execution entry point code.
3 *
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Rewritten for PReP
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2005 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 *
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
29 */
31 #include <linux/init.h>
32 #include <asm/processor.h>
33 #include <asm/page.h>
34 #include <asm/mmu.h>
35 #include <asm/pgtable.h>
36 #include <asm/cputable.h>
37 #include <asm/thread_info.h>
38 #include <asm/ppc_asm.h>
39 #include <asm/asm-offsets.h>
40 #include <asm/ptrace.h>
41 #include <asm/synch.h>
42 #include "head_booke.h"
45 /* As with the other PowerPC ports, it is expected that when code
46 * execution begins here, the following registers contain valid, yet
47 * optional, information:
48 *
49 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
50 * r4 - Starting address of the init RAM disk
51 * r5 - Ending address of the init RAM disk
52 * r6 - Start of kernel command line string (e.g. "mem=128")
53 * r7 - End of kernel command line string
54 *
55 */
56 __HEAD
57 _ENTRY(_stext);
58 _ENTRY(_start);
59 /*
60 * Reserve a word at a fixed location to store the address
61 * of abatron_pteptrs
62 */
63 nop
64 mr r31,r3 /* save device tree ptr */
65 li r24,0 /* CPU number */
67 bl init_cpu_state
69 /*
70 * This is where the main kernel code starts.
71 */
73 /* ptr to current */
74 lis r2,init_task@h
75 ori r2,r2,init_task@l
77 /* ptr to current thread */
78 addi r4,r2,THREAD /* init task's THREAD */
79 mtspr SPRN_SPRG_THREAD,r4
81 /* stack */
82 lis r1,init_thread_union@h
83 ori r1,r1,init_thread_union@l
84 li r0,0
85 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
87 bl early_init
89 #ifdef CONFIG_RELOCATABLE
90 /*
91 * r25 will contain RPN/ERPN for the start address of memory
92 *
93 * Add the difference between KERNELBASE and PAGE_OFFSET to the
94 * start of physical memory to get kernstart_addr.
95 */
96 lis r3,kernstart_addr@ha
97 la r3,kernstart_addr@l(r3)
99 lis r4,KERNELBASE@h
100 ori r4,r4,KERNELBASE@l
101 lis r5,PAGE_OFFSET@h
102 ori r5,r5,PAGE_OFFSET@l
103 subf r4,r5,r4
105 rlwinm r6,r25,0,28,31 /* ERPN */
106 rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */
107 add r7,r7,r4
109 stw r6,0(r3)
110 stw r7,4(r3)
111 #endif
113 /*
114 * Decide what sort of machine this is and initialize the MMU.
115 */
116 li r3,0
117 mr r4,r31
118 bl machine_init
119 bl MMU_init
121 /* Setup PTE pointers for the Abatron bdiGDB */
122 lis r6, swapper_pg_dir@h
123 ori r6, r6, swapper_pg_dir@l
124 lis r5, abatron_pteptrs@h
125 ori r5, r5, abatron_pteptrs@l
126 lis r4, KERNELBASE@h
127 ori r4, r4, KERNELBASE@l
128 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
129 stw r6, 0(r5)
131 /* Clear the Machine Check Syndrome Register */
132 li r0,0
133 mtspr SPRN_MCSR,r0
135 /* Let's move on */
136 lis r4,start_kernel@h
137 ori r4,r4,start_kernel@l
138 lis r3,MSR_KERNEL@h
139 ori r3,r3,MSR_KERNEL@l
140 mtspr SPRN_SRR0,r4
141 mtspr SPRN_SRR1,r3
142 rfi /* change context and jump to start_kernel */
144 /*
145 * Interrupt vector entry code
146 *
147 * The Book E MMUs are always on so we don't need to handle
148 * interrupts in real mode as with previous PPC processors. In
149 * this case we handle interrupts in the kernel virtual address
150 * space.
151 *
152 * Interrupt vectors are dynamically placed relative to the
153 * interrupt prefix as determined by the address of interrupt_base.
154 * The interrupt vectors offsets are programmed using the labels
155 * for each interrupt vector entry.
156 *
157 * Interrupt vectors must be aligned on a 16 byte boundary.
158 * We align on a 32 byte cache line boundary for good measure.
159 */
161 interrupt_base:
162 /* Critical Input Interrupt */
163 CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
165 /* Machine Check Interrupt */
166 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
167 MCHECK_EXCEPTION(0x0210, MachineCheckA, machine_check_exception)
169 /* Data Storage Interrupt */
170 DATA_STORAGE_EXCEPTION
172 /* Instruction Storage Interrupt */
173 INSTRUCTION_STORAGE_EXCEPTION
175 /* External Input Interrupt */
176 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
178 /* Alignment Interrupt */
179 ALIGNMENT_EXCEPTION
181 /* Program Interrupt */
182 PROGRAM_EXCEPTION
184 /* Floating Point Unavailable Interrupt */
185 #ifdef CONFIG_PPC_FPU
186 FP_UNAVAILABLE_EXCEPTION
187 #else
188 EXCEPTION(0x2010, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
189 #endif
190 /* System Call Interrupt */
191 START_EXCEPTION(SystemCall)
192 NORMAL_EXCEPTION_PROLOG
193 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
195 /* Auxiliary Processor Unavailable Interrupt */
196 EXCEPTION(0x2020, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
198 /* Decrementer Interrupt */
199 DECREMENTER_EXCEPTION
201 /* Fixed Internal Timer Interrupt */
202 /* TODO: Add FIT support */
203 EXCEPTION(0x1010, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
205 /* Watchdog Timer Interrupt */
206 /* TODO: Add watchdog support */
207 #ifdef CONFIG_BOOKE_WDT
208 CRITICAL_EXCEPTION(0x1020, WatchdogTimer, WatchdogException)
209 #else
210 CRITICAL_EXCEPTION(0x1020, WatchdogTimer, unknown_exception)
211 #endif
213 /* Data TLB Error Interrupt */
214 START_EXCEPTION(DataTLBError44x)
215 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
216 mtspr SPRN_SPRG_WSCRATCH1, r11
217 mtspr SPRN_SPRG_WSCRATCH2, r12
218 mtspr SPRN_SPRG_WSCRATCH3, r13
219 mfcr r11
220 mtspr SPRN_SPRG_WSCRATCH4, r11
221 mfspr r10, SPRN_DEAR /* Get faulting address */
223 /* If we are faulting a kernel address, we have to use the
224 * kernel page tables.
225 */
226 lis r11, PAGE_OFFSET@h
227 cmplw r10, r11
228 blt+ 3f
229 lis r11, swapper_pg_dir@h
230 ori r11, r11, swapper_pg_dir@l
232 mfspr r12,SPRN_MMUCR
233 rlwinm r12,r12,0,0,23 /* Clear TID */
235 b 4f
237 /* Get the PGD for the current thread */
238 3:
239 mfspr r11,SPRN_SPRG_THREAD
240 lwz r11,PGDIR(r11)
242 /* Load PID into MMUCR TID */
243 mfspr r12,SPRN_MMUCR
244 mfspr r13,SPRN_PID /* Get PID */
245 rlwimi r12,r13,0,24,31 /* Set TID */
247 4:
248 mtspr SPRN_MMUCR,r12
250 /* Mask of required permission bits. Note that while we
251 * do copy ESR:ST to _PAGE_RW position as trying to write
252 * to an RO page is pretty common, we don't do it with
253 * _PAGE_DIRTY. We could do it, but it's a fairly rare
254 * event so I'd rather take the overhead when it happens
255 * rather than adding an instruction here. We should measure
256 * whether the whole thing is worth it in the first place
257 * as we could avoid loading SPRN_ESR completely in the first
258 * place...
259 *
260 * TODO: Is it worth doing that mfspr & rlwimi in the first
261 * place or can we save a couple of instructions here ?
262 */
263 mfspr r12,SPRN_ESR
264 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
265 rlwimi r13,r12,10,30,30
267 /* Load the PTE */
268 /* Compute pgdir/pmd offset */
269 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
270 lwzx r11, r12, r11 /* Get pgd/pmd entry */
271 rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
272 beq 2f /* Bail if no table */
274 /* Compute pte address */
275 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
276 lwz r11, 0(r12) /* Get high word of pte entry */
277 lwz r12, 4(r12) /* Get low word of pte entry */
279 lis r10,tlb_44x_index@ha
281 andc. r13,r13,r12 /* Check permission */
283 /* Load the next available TLB index */
284 lwz r13,tlb_44x_index@l(r10)
286 bne 2f /* Bail if permission mismach */
288 /* Increment, rollover, and store TLB index */
289 addi r13,r13,1
291 /* Compare with watermark (instruction gets patched) */
292 .globl tlb_44x_patch_hwater_D
293 tlb_44x_patch_hwater_D:
294 cmpwi 0,r13,1 /* reserve entries */
295 ble 5f
296 li r13,0
297 5:
298 /* Store the next available TLB index */
299 stw r13,tlb_44x_index@l(r10)
301 /* Re-load the faulting address */
302 mfspr r10,SPRN_DEAR
304 /* Jump to common tlb load */
305 b finish_tlb_load_44x
307 2:
308 /* The bailout. Restore registers to pre-exception conditions
309 * and call the heavyweights to help us out.
310 */
311 mfspr r11, SPRN_SPRG_RSCRATCH4
312 mtcr r11
313 mfspr r13, SPRN_SPRG_RSCRATCH3
314 mfspr r12, SPRN_SPRG_RSCRATCH2
315 mfspr r11, SPRN_SPRG_RSCRATCH1
316 mfspr r10, SPRN_SPRG_RSCRATCH0
317 b DataStorage
319 /* Instruction TLB Error Interrupt */
320 /*
321 * Nearly the same as above, except we get our
322 * information from different registers and bailout
323 * to a different point.
324 */
325 START_EXCEPTION(InstructionTLBError44x)
326 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
327 mtspr SPRN_SPRG_WSCRATCH1, r11
328 mtspr SPRN_SPRG_WSCRATCH2, r12
329 mtspr SPRN_SPRG_WSCRATCH3, r13
330 mfcr r11
331 mtspr SPRN_SPRG_WSCRATCH4, r11
332 mfspr r10, SPRN_SRR0 /* Get faulting address */
334 /* If we are faulting a kernel address, we have to use the
335 * kernel page tables.
336 */
337 lis r11, PAGE_OFFSET@h
338 cmplw r10, r11
339 blt+ 3f
340 lis r11, swapper_pg_dir@h
341 ori r11, r11, swapper_pg_dir@l
343 mfspr r12,SPRN_MMUCR
344 rlwinm r12,r12,0,0,23 /* Clear TID */
346 b 4f
348 /* Get the PGD for the current thread */
349 3:
350 mfspr r11,SPRN_SPRG_THREAD
351 lwz r11,PGDIR(r11)
353 /* Load PID into MMUCR TID */
354 mfspr r12,SPRN_MMUCR
355 mfspr r13,SPRN_PID /* Get PID */
356 rlwimi r12,r13,0,24,31 /* Set TID */
358 4:
359 mtspr SPRN_MMUCR,r12
361 /* Make up the required permissions */
362 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
364 /* Compute pgdir/pmd offset */
365 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
366 lwzx r11, r12, r11 /* Get pgd/pmd entry */
367 rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
368 beq 2f /* Bail if no table */
370 /* Compute pte address */
371 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
372 lwz r11, 0(r12) /* Get high word of pte entry */
373 lwz r12, 4(r12) /* Get low word of pte entry */
375 lis r10,tlb_44x_index@ha
377 andc. r13,r13,r12 /* Check permission */
379 /* Load the next available TLB index */
380 lwz r13,tlb_44x_index@l(r10)
382 bne 2f /* Bail if permission mismach */
384 /* Increment, rollover, and store TLB index */
385 addi r13,r13,1
387 /* Compare with watermark (instruction gets patched) */
388 .globl tlb_44x_patch_hwater_I
389 tlb_44x_patch_hwater_I:
390 cmpwi 0,r13,1 /* reserve entries */
391 ble 5f
392 li r13,0
393 5:
394 /* Store the next available TLB index */
395 stw r13,tlb_44x_index@l(r10)
397 /* Re-load the faulting address */
398 mfspr r10,SPRN_SRR0
400 /* Jump to common TLB load point */
401 b finish_tlb_load_44x
403 2:
404 /* The bailout. Restore registers to pre-exception conditions
405 * and call the heavyweights to help us out.
406 */
407 mfspr r11, SPRN_SPRG_RSCRATCH4
408 mtcr r11
409 mfspr r13, SPRN_SPRG_RSCRATCH3
410 mfspr r12, SPRN_SPRG_RSCRATCH2
411 mfspr r11, SPRN_SPRG_RSCRATCH1
412 mfspr r10, SPRN_SPRG_RSCRATCH0
413 b InstructionStorage
415 /*
416 * Both the instruction and data TLB miss get to this
417 * point to load the TLB.
418 * r10 - EA of fault
419 * r11 - PTE high word value
420 * r12 - PTE low word value
421 * r13 - TLB index
422 * MMUCR - loaded with proper value when we get here
423 * Upon exit, we reload everything and RFI.
424 */
425 finish_tlb_load_44x:
426 /* Combine RPN & ERPN an write WS 0 */
427 rlwimi r11,r12,0,0,31-PAGE_SHIFT
428 tlbwe r11,r13,PPC44x_TLB_XLAT
430 /*
431 * Create WS1. This is the faulting address (EPN),
432 * page size, and valid flag.
433 */
434 li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
435 /* Insert valid and page size */
436 rlwimi r10,r11,0,PPC44x_PTE_ADD_MASK_BIT,31
437 tlbwe r10,r13,PPC44x_TLB_PAGEID /* Write PAGEID */
439 /* And WS 2 */
440 li r10,0xf85 /* Mask to apply from PTE */
441 rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */
442 and r11,r12,r10 /* Mask PTE bits to keep */
443 andi. r10,r12,_PAGE_USER /* User page ? */
444 beq 1f /* nope, leave U bits empty */
445 rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */
446 1: tlbwe r11,r13,PPC44x_TLB_ATTRIB /* Write ATTRIB */
448 /* Done...restore registers and get out of here.
449 */
450 mfspr r11, SPRN_SPRG_RSCRATCH4
451 mtcr r11
452 mfspr r13, SPRN_SPRG_RSCRATCH3
453 mfspr r12, SPRN_SPRG_RSCRATCH2
454 mfspr r11, SPRN_SPRG_RSCRATCH1
455 mfspr r10, SPRN_SPRG_RSCRATCH0
456 rfi /* Force context change */
458 /* TLB error interrupts for 476
459 */
460 #ifdef CONFIG_PPC_47x
461 START_EXCEPTION(DataTLBError47x)
462 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
463 mtspr SPRN_SPRG_WSCRATCH1,r11
464 mtspr SPRN_SPRG_WSCRATCH2,r12
465 mtspr SPRN_SPRG_WSCRATCH3,r13
466 mfcr r11
467 mtspr SPRN_SPRG_WSCRATCH4,r11
468 mfspr r10,SPRN_DEAR /* Get faulting address */
470 /* If we are faulting a kernel address, we have to use the
471 * kernel page tables.
472 */
473 lis r11,PAGE_OFFSET@h
474 cmplw cr0,r10,r11
475 blt+ 3f
476 lis r11,swapper_pg_dir@h
477 ori r11,r11, swapper_pg_dir@l
478 li r12,0 /* MMUCR = 0 */
479 b 4f
481 /* Get the PGD for the current thread and setup MMUCR */
482 3: mfspr r11,SPRN_SPRG3
483 lwz r11,PGDIR(r11)
484 mfspr r12,SPRN_PID /* Get PID */
485 4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */
487 /* Mask of required permission bits. Note that while we
488 * do copy ESR:ST to _PAGE_RW position as trying to write
489 * to an RO page is pretty common, we don't do it with
490 * _PAGE_DIRTY. We could do it, but it's a fairly rare
491 * event so I'd rather take the overhead when it happens
492 * rather than adding an instruction here. We should measure
493 * whether the whole thing is worth it in the first place
494 * as we could avoid loading SPRN_ESR completely in the first
495 * place...
496 *
497 * TODO: Is it worth doing that mfspr & rlwimi in the first
498 * place or can we save a couple of instructions here ?
499 */
500 mfspr r12,SPRN_ESR
501 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
502 rlwimi r13,r12,10,30,30
504 /* Load the PTE */
505 /* Compute pgdir/pmd offset */
506 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
507 lwzx r11,r12,r11 /* Get pgd/pmd entry */
509 /* Word 0 is EPN,V,TS,DSIZ */
510 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
511 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
512 li r12,0
513 tlbwe r10,r12,0
515 /* XXX can we do better ? Need to make sure tlbwe has established
516 * latch V bit in MMUCR0 before the PTE is loaded further down */
517 #ifdef CONFIG_SMP
518 isync
519 #endif
521 rlwinm. r12,r11,0,0,20 /* Extract pt base address */
522 /* Compute pte address */
523 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
524 beq 2f /* Bail if no table */
525 lwz r11,0(r12) /* Get high word of pte entry */
527 /* XXX can we do better ? maybe insert a known 0 bit from r11 into the
528 * bottom of r12 to create a data dependency... We can also use r10
529 * as destination nowadays
530 */
531 #ifdef CONFIG_SMP
532 lwsync
533 #endif
534 lwz r12,4(r12) /* Get low word of pte entry */
536 andc. r13,r13,r12 /* Check permission */
538 /* Jump to common tlb load */
539 beq finish_tlb_load_47x
541 2: /* The bailout. Restore registers to pre-exception conditions
542 * and call the heavyweights to help us out.
543 */
544 mfspr r11,SPRN_SPRG_RSCRATCH4
545 mtcr r11
546 mfspr r13,SPRN_SPRG_RSCRATCH3
547 mfspr r12,SPRN_SPRG_RSCRATCH2
548 mfspr r11,SPRN_SPRG_RSCRATCH1
549 mfspr r10,SPRN_SPRG_RSCRATCH0
550 b DataStorage
552 /* Instruction TLB Error Interrupt */
553 /*
554 * Nearly the same as above, except we get our
555 * information from different registers and bailout
556 * to a different point.
557 */
558 START_EXCEPTION(InstructionTLBError47x)
559 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
560 mtspr SPRN_SPRG_WSCRATCH1,r11
561 mtspr SPRN_SPRG_WSCRATCH2,r12
562 mtspr SPRN_SPRG_WSCRATCH3,r13
563 mfcr r11
564 mtspr SPRN_SPRG_WSCRATCH4,r11
565 mfspr r10,SPRN_SRR0 /* Get faulting address */
567 /* If we are faulting a kernel address, we have to use the
568 * kernel page tables.
569 */
570 lis r11,PAGE_OFFSET@h
571 cmplw cr0,r10,r11
572 blt+ 3f
573 lis r11,swapper_pg_dir@h
574 ori r11,r11, swapper_pg_dir@l
575 li r12,0 /* MMUCR = 0 */
576 b 4f
578 /* Get the PGD for the current thread and setup MMUCR */
579 3: mfspr r11,SPRN_SPRG_THREAD
580 lwz r11,PGDIR(r11)
581 mfspr r12,SPRN_PID /* Get PID */
582 4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */
584 /* Make up the required permissions */
585 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
587 /* Load PTE */
588 /* Compute pgdir/pmd offset */
589 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
590 lwzx r11,r12,r11 /* Get pgd/pmd entry */
592 /* Word 0 is EPN,V,TS,DSIZ */
593 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
594 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
595 li r12,0
596 tlbwe r10,r12,0
598 /* XXX can we do better ? Need to make sure tlbwe has established
599 * latch V bit in MMUCR0 before the PTE is loaded further down */
600 #ifdef CONFIG_SMP
601 isync
602 #endif
604 rlwinm. r12,r11,0,0,20 /* Extract pt base address */
605 /* Compute pte address */
606 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
607 beq 2f /* Bail if no table */
609 lwz r11,0(r12) /* Get high word of pte entry */
610 /* XXX can we do better ? maybe insert a known 0 bit from r11 into the
611 * bottom of r12 to create a data dependency... We can also use r10
612 * as destination nowadays
613 */
614 #ifdef CONFIG_SMP
615 lwsync
616 #endif
617 lwz r12,4(r12) /* Get low word of pte entry */
619 andc. r13,r13,r12 /* Check permission */
621 /* Jump to common TLB load point */
622 beq finish_tlb_load_47x
624 2: /* The bailout. Restore registers to pre-exception conditions
625 * and call the heavyweights to help us out.
626 */
627 mfspr r11, SPRN_SPRG_RSCRATCH4
628 mtcr r11
629 mfspr r13, SPRN_SPRG_RSCRATCH3
630 mfspr r12, SPRN_SPRG_RSCRATCH2
631 mfspr r11, SPRN_SPRG_RSCRATCH1
632 mfspr r10, SPRN_SPRG_RSCRATCH0
633 b InstructionStorage
635 /*
636 * Both the instruction and data TLB miss get to this
637 * point to load the TLB.
638 * r10 - free to use
639 * r11 - PTE high word value
640 * r12 - PTE low word value
641 * r13 - free to use
642 * MMUCR - loaded with proper value when we get here
643 * Upon exit, we reload everything and RFI.
644 */
645 finish_tlb_load_47x:
646 /* Combine RPN & ERPN an write WS 1 */
647 rlwimi r11,r12,0,0,31-PAGE_SHIFT
648 tlbwe r11,r13,1
650 /* And make up word 2 */
651 li r10,0xf85 /* Mask to apply from PTE */
652 rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */
653 and r11,r12,r10 /* Mask PTE bits to keep */
654 andi. r10,r12,_PAGE_USER /* User page ? */
655 beq 1f /* nope, leave U bits empty */
656 rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */
657 1: tlbwe r11,r13,2
659 /* Done...restore registers and get out of here.
660 */
661 mfspr r11, SPRN_SPRG_RSCRATCH4
662 mtcr r11
663 mfspr r13, SPRN_SPRG_RSCRATCH3
664 mfspr r12, SPRN_SPRG_RSCRATCH2
665 mfspr r11, SPRN_SPRG_RSCRATCH1
666 mfspr r10, SPRN_SPRG_RSCRATCH0
667 rfi
669 #endif /* CONFIG_PPC_47x */
671 /* Debug Interrupt */
672 /*
673 * This statement needs to exist at the end of the IVPR
674 * definition just in case you end up taking a debug
675 * exception within another exception.
676 */
677 DEBUG_CRIT_EXCEPTION
679 /*
680 * Global functions
681 */
683 /*
684 * Adjust the machine check IVOR on 440A cores
685 */
686 _GLOBAL(__fixup_440A_mcheck)
687 li r3,MachineCheckA@l
688 mtspr SPRN_IVOR1,r3
689 sync
690 blr
692 /*
693 * extern void giveup_altivec(struct task_struct *prev)
694 *
695 * The 44x core does not have an AltiVec unit.
696 */
697 _GLOBAL(giveup_altivec)
698 blr
700 /*
701 * extern void giveup_fpu(struct task_struct *prev)
702 *
703 * The 44x core does not have an FPU.
704 */
705 #ifndef CONFIG_PPC_FPU
706 _GLOBAL(giveup_fpu)
707 blr
708 #endif
710 _GLOBAL(set_context)
712 #ifdef CONFIG_BDI_SWITCH
713 /* Context switch the PTE pointer for the Abatron BDI2000.
714 * The PGDIR is the second parameter.
715 */
716 lis r5, abatron_pteptrs@h
717 ori r5, r5, abatron_pteptrs@l
718 stw r4, 0x4(r5)
719 #endif
720 mtspr SPRN_PID,r3
721 isync /* Force context change */
722 blr
724 /*
725 * Init CPU state. This is called at boot time or for secondary CPUs
726 * to setup initial TLB entries, setup IVORs, etc...
727 *
728 */
729 _GLOBAL(init_cpu_state)
730 mflr r22
731 #ifdef CONFIG_PPC_47x
732 /* We use the PVR to differenciate 44x cores from 476 */
733 mfspr r3,SPRN_PVR
734 srwi r3,r3,16
735 cmplwi cr0,r3,PVR_476@h
736 beq head_start_47x
737 cmplwi cr0,r3,PVR_476_ISS@h
738 beq head_start_47x
739 #endif /* CONFIG_PPC_47x */
741 /*
742 * In case the firmware didn't do it, we apply some workarounds
743 * that are good for all 440 core variants here
744 */
745 mfspr r3,SPRN_CCR0
746 rlwinm r3,r3,0,0,27 /* disable icache prefetch */
747 isync
748 mtspr SPRN_CCR0,r3
749 isync
750 sync
752 /*
753 * Set up the initial MMU state for 44x
754 *
755 * We are still executing code at the virtual address
756 * mappings set by the firmware for the base of RAM.
757 *
758 * We first invalidate all TLB entries but the one
759 * we are running from. We then load the KERNELBASE
760 * mappings so we can begin to use kernel addresses
761 * natively and so the interrupt vector locations are
762 * permanently pinned (necessary since Book E
763 * implementations always have translation enabled).
764 *
765 * TODO: Use the known TLB entry we are running from to
766 * determine which physical region we are located
767 * in. This can be used to determine where in RAM
768 * (on a shared CPU system) or PCI memory space
769 * (on a DRAMless system) we are located.
770 * For now, we assume a perfect world which means
771 * we are located at the base of DRAM (physical 0).
772 */
774 /*
775 * Search TLB for entry that we are currently using.
776 * Invalidate all entries but the one we are using.
777 */
778 /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
779 mfspr r3,SPRN_PID /* Get PID */
780 mfmsr r4 /* Get MSR */
781 andi. r4,r4,MSR_IS@l /* TS=1? */
782 beq wmmucr /* If not, leave STS=0 */
783 oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */
784 wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */
785 sync
787 bl invstr /* Find our address */
788 invstr: mflr r5 /* Make it accessible */
789 tlbsx r23,0,r5 /* Find entry we are in */
790 li r4,0 /* Start at TLB entry 0 */
791 li r3,0 /* Set PAGEID inval value */
792 1: cmpw r23,r4 /* Is this our entry? */
793 beq skpinv /* If so, skip the inval */
794 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
795 skpinv: addi r4,r4,1 /* Increment */
796 cmpwi r4,64 /* Are we done? */
797 bne 1b /* If not, repeat */
798 isync /* If so, context change */
800 /*
801 * Configure and load pinned entry into TLB slot 63.
802 */
804 lis r3,PAGE_OFFSET@h
805 ori r3,r3,PAGE_OFFSET@l
807 /* Kernel is at the base of RAM */
808 li r4, 0 /* Load the kernel physical address */
810 /* Load the kernel PID = 0 */
811 li r0,0
812 mtspr SPRN_PID,r0
813 sync
815 /* Initialize MMUCR */
816 li r5,0
817 mtspr SPRN_MMUCR,r5
818 sync
820 /* pageid fields */
821 clrrwi r3,r3,10 /* Mask off the effective page number */
822 ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
824 /* xlat fields */
825 clrrwi r4,r4,10 /* Mask off the real page number */
826 /* ERPN is 0 for first 4GB page */
828 /* attrib fields */
829 /* Added guarded bit to protect against speculative loads/stores */
830 li r5,0
831 ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
833 li r0,63 /* TLB slot 63 */
835 tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
836 tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
837 tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
839 /* Force context change */
840 mfmsr r0
841 mtspr SPRN_SRR1, r0
842 lis r0,3f@h
843 ori r0,r0,3f@l
844 mtspr SPRN_SRR0,r0
845 sync
846 rfi
848 /* If necessary, invalidate original entry we used */
849 3: cmpwi r23,63
850 beq 4f
851 li r6,0
852 tlbwe r6,r23,PPC44x_TLB_PAGEID
853 isync
855 4:
856 #ifdef CONFIG_PPC_EARLY_DEBUG_44x
857 /* Add UART mapping for early debug. */
859 /* pageid fields */
860 lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h
861 ori r3,r3,PPC44x_TLB_VALID|PPC44x_TLB_TS|PPC44x_TLB_64K
863 /* xlat fields */
864 lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
865 ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
867 /* attrib fields */
868 li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G)
869 li r0,62 /* TLB slot 0 */
871 tlbwe r3,r0,PPC44x_TLB_PAGEID
872 tlbwe r4,r0,PPC44x_TLB_XLAT
873 tlbwe r5,r0,PPC44x_TLB_ATTRIB
875 /* Force context change */
876 isync
877 #endif /* CONFIG_PPC_EARLY_DEBUG_44x */
879 /* Establish the interrupt vector offsets */
880 SET_IVOR(0, CriticalInput);
881 SET_IVOR(1, MachineCheck);
882 SET_IVOR(2, DataStorage);
883 SET_IVOR(3, InstructionStorage);
884 SET_IVOR(4, ExternalInput);
885 SET_IVOR(5, Alignment);
886 SET_IVOR(6, Program);
887 SET_IVOR(7, FloatingPointUnavailable);
888 SET_IVOR(8, SystemCall);
889 SET_IVOR(9, AuxillaryProcessorUnavailable);
890 SET_IVOR(10, Decrementer);
891 SET_IVOR(11, FixedIntervalTimer);
892 SET_IVOR(12, WatchdogTimer);
893 SET_IVOR(13, DataTLBError44x);
894 SET_IVOR(14, InstructionTLBError44x);
895 SET_IVOR(15, DebugCrit);
897 b head_start_common
900 #ifdef CONFIG_PPC_47x
902 #ifdef CONFIG_SMP
904 /* Entry point for secondary 47x processors */
905 _GLOBAL(start_secondary_47x)
906 mr r24,r3 /* CPU number */
908 bl init_cpu_state
910 /* Now we need to bolt the rest of kernel memory which
911 * is done in C code. We must be careful because our task
912 * struct or our stack can (and will probably) be out
913 * of reach of the initial 256M TLB entry, so we use a
914 * small temporary stack in .bss for that. This works
915 * because only one CPU at a time can be in this code
916 */
917 lis r1,temp_boot_stack@h
918 ori r1,r1,temp_boot_stack@l
919 addi r1,r1,1024-STACK_FRAME_OVERHEAD
920 li r0,0
921 stw r0,0(r1)
922 bl mmu_init_secondary
924 /* Now we can get our task struct and real stack pointer */
926 /* Get current_thread_info and current */
927 lis r1,secondary_ti@ha
928 lwz r1,secondary_ti@l(r1)
929 lwz r2,TI_TASK(r1)
931 /* Current stack pointer */
932 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
933 li r0,0
934 stw r0,0(r1)
936 /* Kernel stack for exception entry in SPRG3 */
937 addi r4,r2,THREAD /* init task's THREAD */
938 mtspr SPRN_SPRG3,r4
940 b start_secondary
942 #endif /* CONFIG_SMP */
944 /*
945 * Set up the initial MMU state for 44x
946 *
947 * We are still executing code at the virtual address
948 * mappings set by the firmware for the base of RAM.
949 */
951 head_start_47x:
952 /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
953 mfspr r3,SPRN_PID /* Get PID */
954 mfmsr r4 /* Get MSR */
955 andi. r4,r4,MSR_IS@l /* TS=1? */
956 beq 1f /* If not, leave STS=0 */
957 oris r3,r3,PPC47x_MMUCR_STS@h /* Set STS=1 */
958 1: mtspr SPRN_MMUCR,r3 /* Put MMUCR */
959 sync
961 /* Find the entry we are running from */
962 bl 1f
963 1: mflr r23
964 tlbsx r23,0,r23
965 tlbre r24,r23,0
966 tlbre r25,r23,1
967 tlbre r26,r23,2
969 /*
970 * Cleanup time
971 */
973 /* Initialize MMUCR */
974 li r5,0
975 mtspr SPRN_MMUCR,r5
976 sync
978 clear_all_utlb_entries:
980 #; Set initial values.
982 addis r3,0,0x8000
983 addi r4,0,0
984 addi r5,0,0
985 b clear_utlb_entry
987 #; Align the loop to speed things up.
989 .align 6
991 clear_utlb_entry:
993 tlbwe r4,r3,0
994 tlbwe r5,r3,1
995 tlbwe r5,r3,2
996 addis r3,r3,0x2000
997 cmpwi r3,0
998 bne clear_utlb_entry
999 addis r3,0,0x8000
1000 addis r4,r4,0x100
1001 cmpwi r4,0
1002 bne clear_utlb_entry
1004 #; Restore original entry.
1006 oris r23,r23,0x8000 /* specify the way */
1007 tlbwe r24,r23,0
1008 tlbwe r25,r23,1
1009 tlbwe r26,r23,2
1011 /*
1012 * Configure and load pinned entry into TLB for the kernel core
1013 */
1015 lis r3,PAGE_OFFSET@h
1016 ori r3,r3,PAGE_OFFSET@l
1018 /* Load the kernel PID = 0 */
1019 li r0,0
1020 mtspr SPRN_PID,r0
1021 sync
1023 /* Word 0 */
1024 clrrwi r3,r3,12 /* Mask off the effective page number */
1025 ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M
1027 /* Word 1 - use r25. RPN is the same as the original entry */
1029 /* Word 2 */
1030 li r5,0
1031 ori r5,r5,PPC47x_TLB2_S_RWX
1032 #ifdef CONFIG_SMP
1033 ori r5,r5,PPC47x_TLB2_M
1034 #endif
1036 /* We write to way 0 and bolted 0 */
1037 lis r0,0x8800
1038 tlbwe r3,r0,0
1039 tlbwe r25,r0,1
1040 tlbwe r5,r0,2
1042 /*
1043 * Configure SSPCR, ISPCR and USPCR for now to search everything, we can fix
1044 * them up later
1045 */
1046 LOAD_REG_IMMEDIATE(r3, 0x9abcdef0)
1047 mtspr SPRN_SSPCR,r3
1048 mtspr SPRN_USPCR,r3
1049 LOAD_REG_IMMEDIATE(r3, 0x12345670)
1050 mtspr SPRN_ISPCR,r3
1052 /* Force context change */
1053 mfmsr r0
1054 mtspr SPRN_SRR1, r0
1055 lis r0,3f@h
1056 ori r0,r0,3f@l
1057 mtspr SPRN_SRR0,r0
1058 sync
1059 rfi
1061 /* Invalidate original entry we used */
1062 3:
1063 rlwinm r24,r24,0,21,19 /* clear the "valid" bit */
1064 tlbwe r24,r23,0
1065 addi r24,0,0
1066 tlbwe r24,r23,1
1067 tlbwe r24,r23,2
1068 isync /* Clear out the shadow TLB entries */
1070 #ifdef CONFIG_PPC_EARLY_DEBUG_44x
1071 /* Add UART mapping for early debug. */
1073 /* Word 0 */
1074 lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h
1075 ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_TS | PPC47x_TLB0_1M
1077 /* Word 1 */
1078 lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
1079 ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
1081 /* Word 2 */
1082 li r5,(PPC47x_TLB2_S_RW | PPC47x_TLB2_IMG)
1084 /* Bolted in way 0, bolt slot 5, we -hope- we don't hit the same
1085 * congruence class as the kernel, we need to make sure of it at
1086 * some point
1087 */
1088 lis r0,0x8d00
1089 tlbwe r3,r0,0
1090 tlbwe r4,r0,1
1091 tlbwe r5,r0,2
1093 /* Force context change */
1094 isync
1095 #endif /* CONFIG_PPC_EARLY_DEBUG_44x */
1097 /* Establish the interrupt vector offsets */
1098 SET_IVOR(0, CriticalInput);
1099 SET_IVOR(1, MachineCheckA);
1100 SET_IVOR(2, DataStorage);
1101 SET_IVOR(3, InstructionStorage);
1102 SET_IVOR(4, ExternalInput);
1103 SET_IVOR(5, Alignment);
1104 SET_IVOR(6, Program);
1105 SET_IVOR(7, FloatingPointUnavailable);
1106 SET_IVOR(8, SystemCall);
1107 SET_IVOR(9, AuxillaryProcessorUnavailable);
1108 SET_IVOR(10, Decrementer);
1109 SET_IVOR(11, FixedIntervalTimer);
1110 SET_IVOR(12, WatchdogTimer);
1111 SET_IVOR(13, DataTLBError47x);
1112 SET_IVOR(14, InstructionTLBError47x);
1113 SET_IVOR(15, DebugCrit);
1115 /* We configure icbi to invalidate 128 bytes at a time since the
1116 * current 32-bit kernel code isn't too happy with icache != dcache
1117 * block size
1118 */
1119 mfspr r3,SPRN_CCR0
1120 oris r3,r3,0x0020
1121 mtspr SPRN_CCR0,r3
1122 isync
1124 #endif /* CONFIG_PPC_47x */
1126 /*
1127 * Here we are back to code that is common between 44x and 47x
1128 *
1129 * We proceed to further kernel initialization and return to the
1130 * main kernel entry
1131 */
1132 head_start_common:
1133 /* Establish the interrupt vector base */
1134 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
1135 mtspr SPRN_IVPR,r4
1137 /*
1138 * If the kernel was loaded at a non-zero 256 MB page, we need to
1139 * mask off the most significant 4 bits to get the relative address
1140 * from the start of physical memory
1141 */
1142 rlwinm r22,r22,0,4,31
1143 addis r22,r22,PAGE_OFFSET@h
1144 mtlr r22
1145 isync
1146 blr
1148 /*
1149 * We put a few things here that have to be page-aligned. This stuff
1150 * goes at the beginning of the data segment, which is page-aligned.
1151 */
1152 .data
1153 .align PAGE_SHIFT
1154 .globl sdata
1155 sdata:
1156 .globl empty_zero_page
1157 empty_zero_page:
1158 .space PAGE_SIZE
1160 /*
1161 * To support >32-bit physical addresses, we use an 8KB pgdir.
1162 */
1163 .globl swapper_pg_dir
1164 swapper_pg_dir:
1165 .space PGD_TABLE_SIZE
1167 /*
1168 * Room for two PTE pointers, usually the kernel and current user pointers
1169 * to their respective root page table.
1170 */
1171 abatron_pteptrs:
1172 .space 8
1174 #ifdef CONFIG_SMP
1175 .align 12
1176 temp_boot_stack:
1177 .space 1024
1178 #endif /* CONFIG_SMP */