arch/powerpc/mm/tlb_hash64.c

   1 /*
   2  * This file contains the routines for flushing entries from the
   3  * TLB and MMU hash table.
   4  *
   5  *  Derived from arch/ppc64/mm/init.c:
   6  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   7  *
   8  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
   9  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  10  *    Copyright (C) 1996 Paul Mackerras
  11  *
  12  *  Derived from "arch/i386/mm/init.c"
  13  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  14  *
  15  *  Dave Engebretsen <engebret@us.ibm.com>
  16  *      Rework for PPC64 port.
  17  *
  18  *  This program is free software; you can redistribute it and/or
  19  *  modify it under the terms of the GNU General Public License
  20  *  as published by the Free Software Foundation; either version
  21  *  2 of the License, or (at your option) any later version.
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/init.h>
  27 #include <linux/percpu.h>
  28 #include <linux/hardirq.h>
  29 #include <asm/pgalloc.h>
  30 #include <asm/tlbflush.h>
  31 #include <asm/tlb.h>
  32 #include <asm/bug.h>
  33
  34 DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
  35
  36 /*
  37  * A linux PTE was changed and the corresponding hash table entry
  38  * neesd to be flushed. This function will either perform the flush
  39  * immediately or will batch it up if the current CPU has an active
  40  * batch on it.
  41  */
  42 void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
  43                      pte_t *ptep, unsigned long pte, int huge)
  44 {
  45         struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch);
  46         unsigned long vsid, vaddr;
  47         unsigned int psize;
  48         int ssize;
  49         real_pte_t rpte;
  50         int i;
  51
  52         i = batch->index;
  53
  54         /* Get page size (maybe move back to caller).
  55          *
  56          * NOTE: when using special 64K mappings in 4K environment like
  57          * for SPEs, we obtain the page size from the slice, which thus
  58          * must still exist (and thus the VMA not reused) at the time
  59          * of this call
  60          */
  61         if (huge) {
  62 #ifdef CONFIG_HUGETLB_PAGE
  63                 psize = get_slice_psize(mm, addr);
  64                 /* Mask the address for the correct page size */
  65                 addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1);
  66 #else
  67                 BUG();
  68                 psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
  69 #endif
  70         } else {
  71                 psize = pte_pagesize_index(mm, addr, pte);
  72                 /* Mask the address for the standard page size.  If we
  73                  * have a 64k page kernel, but the hardware does not
  74                  * support 64k pages, this might be different from the
  75                  * hardware page size encoded in the slice table. */
  76                 addr &= PAGE_MASK;
  77         }
  78
  79
  80         /* Build full vaddr */
  81         if (!is_kernel_addr(addr)) {
  82                 ssize = user_segment_size(addr);
  83                 vsid = get_vsid(mm->context.id, addr, ssize);
  84                 WARN_ON(vsid == 0);
  85         } else {
  86                 vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
  87                 ssize = mmu_kernel_ssize;
  88         }
  89         vaddr = hpt_va(addr, vsid, ssize);
  90         rpte = __real_pte(__pte(pte), ptep);
  91
  92         /*
  93          * Check if we have an active batch on this CPU. If not, just
  94          * flush now and return. For now, we don global invalidates
  95          * in that case, might be worth testing the mm cpu mask though
  96          * and decide to use local invalidates instead...
  97          */
  98         if (!batch->active) {
  99                 flush_hash_page(vaddr, rpte, psize, ssize, 0);
 100                 put_cpu_var(ppc64_tlb_batch);
 101                 return;
 102         }
 103
 104         /*
 105          * This can happen when we are in the middle of a TLB batch and
 106          * we encounter memory pressure (eg copy_page_range when it tries
 107          * to allocate a new pte). If we have to reclaim memory and end
 108          * up scanning and resetting referenced bits then our batch context
 109          * will change mid stream.
 110          *
 111          * We also need to ensure only one page size is present in a given
 112          * batch
 113          */
 114         if (i != 0 && (mm != batch->mm || batch->psize != psize ||
 115                        batch->ssize != ssize)) {
 116                 __flush_tlb_pending(batch);
 117                 i = 0;
 118         }
 119         if (i == 0) {
 120                 batch->mm = mm;
 121                 batch->psize = psize;
 122                 batch->ssize = ssize;
 123         }
 124         batch->pte[i] = rpte;
 125         batch->vaddr[i] = vaddr;
 126         batch->index = ++i;
 127         if (i >= PPC64_TLB_BATCH_NR)
 128                 __flush_tlb_pending(batch);
 129         put_cpu_var(ppc64_tlb_batch);
 130 }
 131
 132 /*
 133  * This function is called when terminating an mmu batch or when a batch
 134  * is full. It will perform the flush of all the entries currently stored
 135  * in a batch.
 136  *
 137  * Must be called from within some kind of spinlock/non-preempt region...
 138  */
 139 void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
 140 {
 141         const struct cpumask *tmp;
 142         int i, local = 0;
 143
 144         i = batch->index;
 145         tmp = cpumask_of(smp_processor_id());
 146         if (cpumask_equal(mm_cpumask(batch->mm), tmp))
 147                 local = 1;
 148         if (i == 1)
 149                 flush_hash_page(batch->vaddr[0], batch->pte[0],
 150                                 batch->psize, batch->ssize, local);
 151         else
 152                 flush_hash_range(i, local);
 153         batch->index = 0;
 154 }
 155
 156 void tlb_flush(struct mmu_gather *tlb)
 157 {
 158         struct ppc64_tlb_batch *tlbbatch = &get_cpu_var(ppc64_tlb_batch);
 159
 160         /* If there's a TLB batch pending, then we must flush it because the
 161          * pages are going to be freed and we really don't want to have a CPU
 162          * access a freed page because it has a stale TLB
 163          */
 164         if (tlbbatch->index)
 165                 __flush_tlb_pending(tlbbatch);
 166
 167         put_cpu_var(ppc64_tlb_batch);
 168 }
 169
 170 /**
 171  * __flush_hash_table_range - Flush all HPTEs for a given address range
 172  *                            from the hash table (and the TLB). But keeps
 173  *                            the linux PTEs intact.
 174  *
 175  * @mm          : mm_struct of the target address space (generally init_mm)
 176  * @start       : starting address
 177  * @end         : ending address (not included in the flush)
 178  *
 179  * This function is mostly to be used by some IO hotplug code in order
 180  * to remove all hash entries from a given address range used to map IO
 181  * space on a removed PCI-PCI bidge without tearing down the full mapping
 182  * since 64K pages may overlap with other bridges when using 64K pages
 183  * with 4K HW pages on IO space.
 184  *
 185  * Because of that usage pattern, it's only available with CONFIG_HOTPLUG
 186  * and is implemented for small size rather than speed.
 187  */
 188 #ifdef CONFIG_HOTPLUG
 189
 190 void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
 191                               unsigned long end)
 192 {
 193         unsigned long flags;
 194
 195         start = _ALIGN_DOWN(start, PAGE_SIZE);
 196         end = _ALIGN_UP(end, PAGE_SIZE);
 197
 198         BUG_ON(!mm->pgd);
 199
 200         /* Note: Normally, we should only ever use a batch within a
 201          * PTE locked section. This violates the rule, but will work
 202          * since we don't actually modify the PTEs, we just flush the
 203          * hash while leaving the PTEs intact (including their reference
 204          * to being hashed). This is not the most performance oriented
 205          * way to do things but is fine for our needs here.
 206          */
 207         local_irq_save(flags);
 208         arch_enter_lazy_mmu_mode();
 209         for (; start < end; start += PAGE_SIZE) {
 210                 pte_t *ptep = find_linux_pte(mm->pgd, start);
 211                 unsigned long pte;
 212
 213                 if (ptep == NULL)
 214                         continue;
 215                 pte = pte_val(*ptep);
 216                 if (!(pte & _PAGE_HASHPTE))
 217                         continue;
 218                 hpte_need_flush(mm, start, ptep, pte, 0);
 219         }
 220         arch_leave_lazy_mmu_mode();
 221         local_irq_restore(flags);
 222 }
 223
 224 #endif /* CONFIG_HOTPLUG */