| blob | dc4a5f385e41711317789f93771d1258d8ef890b |
1 /*
2 * Low level TLB miss handlers for Book3E
3 *
4 * Copyright (C) 2008-2009
5 * Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
13 #include <asm/processor.h>
14 #include <asm/reg.h>
15 #include <asm/page.h>
16 #include <asm/mmu.h>
17 #include <asm/ppc_asm.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/cputable.h>
20 #include <asm/pgtable.h>
21 #include <asm/exception-64e.h>
22 #include <asm/ppc-opcode.h>
24 #ifdef CONFIG_PPC_64K_PAGES
25 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1)
26 #else
27 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE)
28 #endif
29 #define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE)
30 #define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
31 #define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
33 /**********************************************************************
34 * *
35 * TLB miss handling for Book3E with a bolted linear mapping *
36 * No virtual page table, no nested TLB misses *
37 * *
38 **********************************************************************/
40 .macro tlb_prolog_bolted addr
41 mtspr SPRN_SPRG_TLB_SCRATCH,r13
42 mfspr r13,SPRN_SPRG_PACA
43 std r10,PACA_EXTLB+EX_TLB_R10(r13)
44 mfcr r10
45 std r11,PACA_EXTLB+EX_TLB_R11(r13)
46 std r16,PACA_EXTLB+EX_TLB_R16(r13)
47 mfspr r16,\addr /* get faulting address */
48 std r14,PACA_EXTLB+EX_TLB_R14(r13)
49 ld r14,PACAPGD(r13)
50 std r15,PACA_EXTLB+EX_TLB_R15(r13)
51 std r10,PACA_EXTLB+EX_TLB_CR(r13)
52 TLB_MISS_PROLOG_STATS_BOLTED
53 .endm
55 .macro tlb_epilog_bolted
56 ld r14,PACA_EXTLB+EX_TLB_CR(r13)
57 ld r10,PACA_EXTLB+EX_TLB_R10(r13)
58 ld r11,PACA_EXTLB+EX_TLB_R11(r13)
59 mtcr r14
60 ld r14,PACA_EXTLB+EX_TLB_R14(r13)
61 ld r15,PACA_EXTLB+EX_TLB_R15(r13)
62 TLB_MISS_RESTORE_STATS_BOLTED
63 ld r16,PACA_EXTLB+EX_TLB_R16(r13)
64 mfspr r13,SPRN_SPRG_TLB_SCRATCH
65 .endm
67 /* Data TLB miss */
68 START_EXCEPTION(data_tlb_miss_bolted)
69 tlb_prolog_bolted SPRN_DEAR
71 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
73 /* We do the user/kernel test for the PID here along with the RW test
74 */
75 /* We pre-test some combination of permissions to avoid double
76 * faults:
77 *
78 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
79 * ESR_ST is 0x00800000
80 * _PAGE_BAP_SW is 0x00000010
81 * So the shift is >> 19. This tests for supervisor writeability.
82 * If the page happens to be supervisor writeable and not user
83 * writeable, we will take a new fault later, but that should be
84 * a rare enough case.
85 *
86 * We also move ESR_ST in _PAGE_DIRTY position
87 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
88 *
89 * MAS1 is preset for all we need except for TID that needs to
90 * be cleared for kernel translations
91 */
93 mfspr r11,SPRN_ESR
95 srdi r15,r16,60 /* get region */
96 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
97 bne- dtlb_miss_fault_bolted
99 rlwinm r10,r11,32-19,27,27
100 rlwimi r10,r11,32-16,19,19
101 cmpwi r15,0
102 ori r10,r10,_PAGE_PRESENT
103 oris r11,r10,_PAGE_ACCESSED@h
105 TLB_MISS_STATS_SAVE_INFO_BOLTED
106 bne tlb_miss_kernel_bolted
108 tlb_miss_common_bolted:
109 /*
110 * This is the guts of the TLB miss handler for bolted-linear.
111 * We are entered with:
112 *
113 * r16 = faulting address
114 * r15 = crap (free to use)
115 * r14 = page table base
116 * r13 = PACA
117 * r11 = PTE permission mask
118 * r10 = crap (free to use)
119 */
120 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
121 cmpldi cr0,r14,0
122 clrrdi r15,r15,3
123 beq tlb_miss_fault_bolted
125 BEGIN_MMU_FTR_SECTION
126 /* Set the TLB reservation and search for existing entry. Then load
127 * the entry.
128 */
129 PPC_TLBSRX_DOT(0,r16)
130 ldx r14,r14,r15
131 beq normal_tlb_miss_done
132 MMU_FTR_SECTION_ELSE
133 ldx r14,r14,r15
134 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
136 #ifndef CONFIG_PPC_64K_PAGES
137 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
138 clrrdi r15,r15,3
140 cmpldi cr0,r14,0
141 beq tlb_miss_fault_bolted
143 ldx r14,r14,r15
144 #endif /* CONFIG_PPC_64K_PAGES */
146 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
147 clrrdi r15,r15,3
149 cmpldi cr0,r14,0
150 beq tlb_miss_fault_bolted
152 ldx r14,r14,r15
154 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
155 clrrdi r15,r15,3
157 cmpldi cr0,r14,0
158 beq tlb_miss_fault_bolted
160 ldx r14,r14,r15
162 /* Check if required permissions are met */
163 andc. r15,r11,r14
164 rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
165 bne- tlb_miss_fault_bolted
167 /* Now we build the MAS:
168 *
169 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
170 * MAS 1 : Almost fully setup
171 * - PID already updated by caller if necessary
172 * - TSIZE need change if !base page size, not
173 * yet implemented for now
174 * MAS 2 : Defaults not useful, need to be redone
175 * MAS 3+7 : Needs to be done
176 */
177 clrrdi r11,r16,12 /* Clear low crap in EA */
178 clrldi r15,r15,12 /* Clear crap at the top */
179 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
180 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
181 mtspr SPRN_MAS2,r11
182 andi. r11,r14,_PAGE_DIRTY
183 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
185 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
186 bne 1f
187 li r11,MAS3_SW|MAS3_UW
188 andc r15,r15,r11
189 1:
190 mtspr SPRN_MAS7_MAS3,r15
191 tlbwe
193 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
194 tlb_epilog_bolted
195 rfi
197 itlb_miss_kernel_bolted:
198 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
199 oris r11,r11,_PAGE_ACCESSED@h
200 tlb_miss_kernel_bolted:
201 mfspr r10,SPRN_MAS1
202 ld r14,PACA_KERNELPGD(r13)
203 cmpldi cr0,r15,8 /* Check for vmalloc region */
204 rlwinm r10,r10,0,16,1 /* Clear TID */
205 mtspr SPRN_MAS1,r10
206 beq+ tlb_miss_common_bolted
208 tlb_miss_fault_bolted:
209 /* We need to check if it was an instruction miss */
210 andi. r10,r11,_PAGE_EXEC|_PAGE_BAP_SX
211 bne itlb_miss_fault_bolted
212 dtlb_miss_fault_bolted:
213 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
214 tlb_epilog_bolted
215 b exc_data_storage_book3e
216 itlb_miss_fault_bolted:
217 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
218 tlb_epilog_bolted
219 b exc_instruction_storage_book3e
221 /* Instruction TLB miss */
222 START_EXCEPTION(instruction_tlb_miss_bolted)
223 tlb_prolog_bolted SPRN_SRR0
225 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
226 srdi r15,r16,60 /* get region */
227 TLB_MISS_STATS_SAVE_INFO_BOLTED
228 bne- itlb_miss_fault_bolted
230 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
232 /* We do the user/kernel test for the PID here along with the RW test
233 */
235 cmpldi cr0,r15,0 /* Check for user region */
236 oris r11,r11,_PAGE_ACCESSED@h
237 beq tlb_miss_common_bolted
238 b itlb_miss_kernel_bolted
240 /**********************************************************************
241 * *
242 * TLB miss handling for Book3E with TLB reservation and HES support *
243 * *
244 **********************************************************************/
247 /* Data TLB miss */
248 START_EXCEPTION(data_tlb_miss)
249 TLB_MISS_PROLOG
251 /* Now we handle the fault proper. We only save DEAR in normal
252 * fault case since that's the only interesting values here.
253 * We could probably also optimize by not saving SRR0/1 in the
254 * linear mapping case but I'll leave that for later
255 */
256 mfspr r14,SPRN_ESR
257 mfspr r16,SPRN_DEAR /* get faulting address */
258 srdi r15,r16,60 /* get region */
259 cmpldi cr0,r15,0xc /* linear mapping ? */
260 TLB_MISS_STATS_SAVE_INFO
261 beq tlb_load_linear /* yes -> go to linear map load */
263 /* The page tables are mapped virtually linear. At this point, though,
264 * we don't know whether we are trying to fault in a first level
265 * virtual address or a virtual page table address. We can get that
266 * from bit 0x1 of the region ID which we have set for a page table
267 */
268 andi. r10,r15,0x1
269 bne- virt_page_table_tlb_miss
271 std r14,EX_TLB_ESR(r12); /* save ESR */
272 std r16,EX_TLB_DEAR(r12); /* save DEAR */
274 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
275 li r11,_PAGE_PRESENT
276 oris r11,r11,_PAGE_ACCESSED@h
278 /* We do the user/kernel test for the PID here along with the RW test
279 */
280 cmpldi cr0,r15,0 /* Check for user region */
282 /* We pre-test some combination of permissions to avoid double
283 * faults:
284 *
285 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
286 * ESR_ST is 0x00800000
287 * _PAGE_BAP_SW is 0x00000010
288 * So the shift is >> 19. This tests for supervisor writeability.
289 * If the page happens to be supervisor writeable and not user
290 * writeable, we will take a new fault later, but that should be
291 * a rare enough case.
292 *
293 * We also move ESR_ST in _PAGE_DIRTY position
294 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
295 *
296 * MAS1 is preset for all we need except for TID that needs to
297 * be cleared for kernel translations
298 */
299 rlwimi r11,r14,32-19,27,27
300 rlwimi r11,r14,32-16,19,19
301 beq normal_tlb_miss
302 /* XXX replace the RMW cycles with immediate loads + writes */
303 1: mfspr r10,SPRN_MAS1
304 cmpldi cr0,r15,8 /* Check for vmalloc region */
305 rlwinm r10,r10,0,16,1 /* Clear TID */
306 mtspr SPRN_MAS1,r10
307 beq+ normal_tlb_miss
309 /* We got a crappy address, just fault with whatever DEAR and ESR
310 * are here
311 */
312 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
313 TLB_MISS_EPILOG_ERROR
314 b exc_data_storage_book3e
316 /* Instruction TLB miss */
317 START_EXCEPTION(instruction_tlb_miss)
318 TLB_MISS_PROLOG
320 /* If we take a recursive fault, the second level handler may need
321 * to know whether we are handling a data or instruction fault in
322 * order to get to the right store fault handler. We provide that
323 * info by writing a crazy value in ESR in our exception frame
324 */
325 li r14,-1 /* store to exception frame is done later */
327 /* Now we handle the fault proper. We only save DEAR in the non
328 * linear mapping case since we know the linear mapping case will
329 * not re-enter. We could indeed optimize and also not save SRR0/1
330 * in the linear mapping case but I'll leave that for later
331 *
332 * Faulting address is SRR0 which is already in r16
333 */
334 srdi r15,r16,60 /* get region */
335 cmpldi cr0,r15,0xc /* linear mapping ? */
336 TLB_MISS_STATS_SAVE_INFO
337 beq tlb_load_linear /* yes -> go to linear map load */
339 /* We do the user/kernel test for the PID here along with the RW test
340 */
341 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
342 oris r11,r11,_PAGE_ACCESSED@h
344 cmpldi cr0,r15,0 /* Check for user region */
345 std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */
346 beq normal_tlb_miss
348 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
349 oris r11,r11,_PAGE_ACCESSED@h
350 /* XXX replace the RMW cycles with immediate loads + writes */
351 mfspr r10,SPRN_MAS1
352 cmpldi cr0,r15,8 /* Check for vmalloc region */
353 rlwinm r10,r10,0,16,1 /* Clear TID */
354 mtspr SPRN_MAS1,r10
355 beq+ normal_tlb_miss
357 /* We got a crappy address, just fault */
358 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
359 TLB_MISS_EPILOG_ERROR
360 b exc_instruction_storage_book3e
362 /*
363 * This is the guts of the first-level TLB miss handler for direct
364 * misses. We are entered with:
365 *
366 * r16 = faulting address
367 * r15 = region ID
368 * r14 = crap (free to use)
369 * r13 = PACA
370 * r12 = TLB exception frame in PACA
371 * r11 = PTE permission mask
372 * r10 = crap (free to use)
373 */
374 normal_tlb_miss:
375 /* So we first construct the page table address. We do that by
376 * shifting the bottom of the address (not the region ID) by
377 * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and
378 * or'ing the fourth high bit.
379 *
380 * NOTE: For 64K pages, we do things slightly differently in
381 * order to handle the weird page table format used by linux
382 */
383 ori r10,r15,0x1
384 #ifdef CONFIG_PPC_64K_PAGES
385 /* For the top bits, 16 bytes per PTE */
386 rldicl r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4
387 /* Now create the bottom bits as 0 in position 0x8000 and
388 * the rest calculated for 8 bytes per PTE
389 */
390 rldicl r15,r16,64-(PAGE_SHIFT-3),64-15
391 /* Insert the bottom bits in */
392 rlwimi r14,r15,0,16,31
393 #else
394 rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
395 #endif
396 sldi r15,r10,60
397 clrrdi r14,r14,3
398 or r10,r15,r14
400 BEGIN_MMU_FTR_SECTION
401 /* Set the TLB reservation and search for existing entry. Then load
402 * the entry.
403 */
404 PPC_TLBSRX_DOT(0,r16)
405 ld r14,0(r10)
406 beq normal_tlb_miss_done
407 MMU_FTR_SECTION_ELSE
408 ld r14,0(r10)
409 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
411 finish_normal_tlb_miss:
412 /* Check if required permissions are met */
413 andc. r15,r11,r14
414 bne- normal_tlb_miss_access_fault
416 /* Now we build the MAS:
417 *
418 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
419 * MAS 1 : Almost fully setup
420 * - PID already updated by caller if necessary
421 * - TSIZE need change if !base page size, not
422 * yet implemented for now
423 * MAS 2 : Defaults not useful, need to be redone
424 * MAS 3+7 : Needs to be done
425 *
426 * TODO: mix up code below for better scheduling
427 */
428 clrrdi r11,r16,12 /* Clear low crap in EA */
429 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
430 mtspr SPRN_MAS2,r11
432 /* Check page size, if not standard, update MAS1 */
433 rldicl r11,r14,64-8,64-8
434 #ifdef CONFIG_PPC_64K_PAGES
435 cmpldi cr0,r11,BOOK3E_PAGESZ_64K
436 #else
437 cmpldi cr0,r11,BOOK3E_PAGESZ_4K
438 #endif
439 beq- 1f
440 mfspr r11,SPRN_MAS1
441 rlwimi r11,r14,31,21,24
442 rlwinm r11,r11,0,21,19
443 mtspr SPRN_MAS1,r11
444 1:
445 /* Move RPN in position */
446 rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
447 clrldi r15,r11,12 /* Clear crap at the top */
448 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
449 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
451 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
452 andi. r11,r14,_PAGE_DIRTY
453 bne 1f
454 li r11,MAS3_SW|MAS3_UW
455 andc r15,r15,r11
456 1:
457 BEGIN_MMU_FTR_SECTION
458 srdi r16,r15,32
459 mtspr SPRN_MAS3,r15
460 mtspr SPRN_MAS7,r16
461 MMU_FTR_SECTION_ELSE
462 mtspr SPRN_MAS7_MAS3,r15
463 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
465 tlbwe
467 normal_tlb_miss_done:
468 /* We don't bother with restoring DEAR or ESR since we know we are
469 * level 0 and just going back to userland. They are only needed
470 * if you are going to take an access fault
471 */
472 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
473 TLB_MISS_EPILOG_SUCCESS
474 rfi
476 normal_tlb_miss_access_fault:
477 /* We need to check if it was an instruction miss */
478 andi. r10,r11,_PAGE_EXEC
479 bne 1f
480 ld r14,EX_TLB_DEAR(r12)
481 ld r15,EX_TLB_ESR(r12)
482 mtspr SPRN_DEAR,r14
483 mtspr SPRN_ESR,r15
484 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
485 TLB_MISS_EPILOG_ERROR
486 b exc_data_storage_book3e
487 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
488 TLB_MISS_EPILOG_ERROR
489 b exc_instruction_storage_book3e
492 /*
493 * This is the guts of the second-level TLB miss handler for direct
494 * misses. We are entered with:
495 *
496 * r16 = virtual page table faulting address
497 * r15 = region (top 4 bits of address)
498 * r14 = crap (free to use)
499 * r13 = PACA
500 * r12 = TLB exception frame in PACA
501 * r11 = crap (free to use)
502 * r10 = crap (free to use)
503 *
504 * Note that this should only ever be called as a second level handler
505 * with the current scheme when using SW load.
506 * That means we can always get the original fault DEAR at
507 * EX_TLB_DEAR-EX_TLB_SIZE(r12)
508 *
509 * It can be re-entered by the linear mapping miss handler. However, to
510 * avoid too much complication, it will restart the whole fault at level
511 * 0 so we don't care too much about clobbers
512 *
513 * XXX That code was written back when we couldn't clobber r14. We can now,
514 * so we could probably optimize things a bit
515 */
516 virt_page_table_tlb_miss:
517 /* Are we hitting a kernel page table ? */
518 andi. r10,r15,0x8
520 /* The cool thing now is that r10 contains 0 for user and 8 for kernel,
521 * and we happen to have the swapper_pg_dir at offset 8 from the user
522 * pgdir in the PACA :-).
523 */
524 add r11,r10,r13
526 /* If kernel, we need to clear MAS1 TID */
527 beq 1f
528 /* XXX replace the RMW cycles with immediate loads + writes */
529 mfspr r10,SPRN_MAS1
530 rlwinm r10,r10,0,16,1 /* Clear TID */
531 mtspr SPRN_MAS1,r10
532 1:
533 BEGIN_MMU_FTR_SECTION
534 /* Search if we already have a TLB entry for that virtual address, and
535 * if we do, bail out.
536 */
537 PPC_TLBSRX_DOT(0,r16)
538 beq virt_page_table_tlb_miss_done
539 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
541 /* Now, we need to walk the page tables. First check if we are in
542 * range.
543 */
544 rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4
545 bne- virt_page_table_tlb_miss_fault
547 /* Get the PGD pointer */
548 ld r15,PACAPGD(r11)
549 cmpldi cr0,r15,0
550 beq- virt_page_table_tlb_miss_fault
552 /* Get to PGD entry */
553 rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3
554 clrrdi r10,r11,3
555 ldx r15,r10,r15
556 cmpdi cr0,r15,0
557 bge virt_page_table_tlb_miss_fault
559 #ifndef CONFIG_PPC_64K_PAGES
560 /* Get to PUD entry */
561 rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
562 clrrdi r10,r11,3
563 ldx r15,r10,r15
564 cmpdi cr0,r15,0
565 bge virt_page_table_tlb_miss_fault
566 #endif /* CONFIG_PPC_64K_PAGES */
568 /* Get to PMD entry */
569 rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
570 clrrdi r10,r11,3
571 ldx r15,r10,r15
572 cmpdi cr0,r15,0
573 bge virt_page_table_tlb_miss_fault
575 /* Ok, we're all right, we can now create a kernel translation for
576 * a 4K or 64K page from r16 -> r15.
577 */
578 /* Now we build the MAS:
579 *
580 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
581 * MAS 1 : Almost fully setup
582 * - PID already updated by caller if necessary
583 * - TSIZE for now is base page size always
584 * MAS 2 : Use defaults
585 * MAS 3+7 : Needs to be done
586 *
587 * So we only do MAS 2 and 3 for now...
588 */
589 clrldi r11,r15,4 /* remove region ID from RPN */
590 ori r10,r11,1 /* Or-in SR */
592 BEGIN_MMU_FTR_SECTION
593 srdi r16,r10,32
594 mtspr SPRN_MAS3,r10
595 mtspr SPRN_MAS7,r16
596 MMU_FTR_SECTION_ELSE
597 mtspr SPRN_MAS7_MAS3,r10
598 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
600 tlbwe
602 BEGIN_MMU_FTR_SECTION
603 virt_page_table_tlb_miss_done:
605 /* We have overriden MAS2:EPN but currently our primary TLB miss
606 * handler will always restore it so that should not be an issue,
607 * if we ever optimize the primary handler to not write MAS2 on
608 * some cases, we'll have to restore MAS2:EPN here based on the
609 * original fault's DEAR. If we do that we have to modify the
610 * ITLB miss handler to also store SRR0 in the exception frame
611 * as DEAR.
612 *
613 * However, one nasty thing we did is we cleared the reservation
614 * (well, potentially we did). We do a trick here thus if we
615 * are not a level 0 exception (we interrupted the TLB miss) we
616 * offset the return address by -4 in order to replay the tlbsrx
617 * instruction there
618 */
619 subf r10,r13,r12
620 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
621 bne- 1f
622 ld r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
623 addi r10,r11,-4
624 std r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
625 1:
626 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
627 /* Return to caller, normal case */
628 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK);
629 TLB_MISS_EPILOG_SUCCESS
630 rfi
632 virt_page_table_tlb_miss_fault:
633 /* If we fault here, things are a little bit tricky. We need to call
634 * either data or instruction store fault, and we need to retrieve
635 * the original fault address and ESR (for data).
636 *
637 * The thing is, we know that in normal circumstances, this is
638 * always called as a second level tlb miss for SW load or as a first
639 * level TLB miss for HW load, so we should be able to peek at the
640 * relevant information in the first exception frame in the PACA.
641 *
642 * However, we do need to double check that, because we may just hit
643 * a stray kernel pointer or a userland attack trying to hit those
644 * areas. If that is the case, we do a data fault. (We can't get here
645 * from an instruction tlb miss anyway).
646 *
647 * Note also that when going to a fault, we must unwind the previous
648 * level as well. Since we are doing that, we don't need to clear or
649 * restore the TLB reservation neither.
650 */
651 subf r10,r13,r12
652 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
653 bne- virt_page_table_tlb_miss_whacko_fault
655 /* We dig the original DEAR and ESR from slot 0 */
656 ld r15,EX_TLB_DEAR+PACA_EXTLB(r13)
657 ld r16,EX_TLB_ESR+PACA_EXTLB(r13)
659 /* We check for the "special" ESR value for instruction faults */
660 cmpdi cr0,r16,-1
661 beq 1f
662 mtspr SPRN_DEAR,r15
663 mtspr SPRN_ESR,r16
664 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT);
665 TLB_MISS_EPILOG_ERROR
666 b exc_data_storage_book3e
667 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT);
668 TLB_MISS_EPILOG_ERROR
669 b exc_instruction_storage_book3e
671 virt_page_table_tlb_miss_whacko_fault:
672 /* The linear fault will restart everything so ESR and DEAR will
673 * not have been clobbered, let's just fault with what we have
674 */
675 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT);
676 TLB_MISS_EPILOG_ERROR
677 b exc_data_storage_book3e
680 /**************************************************************
681 * *
682 * TLB miss handling for Book3E with hw page table support *
683 * *
684 **************************************************************/
687 /* Data TLB miss */
688 START_EXCEPTION(data_tlb_miss_htw)
689 TLB_MISS_PROLOG
691 /* Now we handle the fault proper. We only save DEAR in normal
692 * fault case since that's the only interesting values here.
693 * We could probably also optimize by not saving SRR0/1 in the
694 * linear mapping case but I'll leave that for later
695 */
696 mfspr r14,SPRN_ESR
697 mfspr r16,SPRN_DEAR /* get faulting address */
698 srdi r11,r16,60 /* get region */
699 cmpldi cr0,r11,0xc /* linear mapping ? */
700 TLB_MISS_STATS_SAVE_INFO
701 beq tlb_load_linear /* yes -> go to linear map load */
703 /* We do the user/kernel test for the PID here along with the RW test
704 */
705 cmpldi cr0,r11,0 /* Check for user region */
706 ld r15,PACAPGD(r13) /* Load user pgdir */
707 beq htw_tlb_miss
709 /* XXX replace the RMW cycles with immediate loads + writes */
710 1: mfspr r10,SPRN_MAS1
711 cmpldi cr0,r11,8 /* Check for vmalloc region */
712 rlwinm r10,r10,0,16,1 /* Clear TID */
713 mtspr SPRN_MAS1,r10
714 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
715 beq+ htw_tlb_miss
717 /* We got a crappy address, just fault with whatever DEAR and ESR
718 * are here
719 */
720 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
721 TLB_MISS_EPILOG_ERROR
722 b exc_data_storage_book3e
724 /* Instruction TLB miss */
725 START_EXCEPTION(instruction_tlb_miss_htw)
726 TLB_MISS_PROLOG
728 /* If we take a recursive fault, the second level handler may need
729 * to know whether we are handling a data or instruction fault in
730 * order to get to the right store fault handler. We provide that
731 * info by keeping a crazy value for ESR in r14
732 */
733 li r14,-1 /* store to exception frame is done later */
735 /* Now we handle the fault proper. We only save DEAR in the non
736 * linear mapping case since we know the linear mapping case will
737 * not re-enter. We could indeed optimize and also not save SRR0/1
738 * in the linear mapping case but I'll leave that for later
739 *
740 * Faulting address is SRR0 which is already in r16
741 */
742 srdi r11,r16,60 /* get region */
743 cmpldi cr0,r11,0xc /* linear mapping ? */
744 TLB_MISS_STATS_SAVE_INFO
745 beq tlb_load_linear /* yes -> go to linear map load */
747 /* We do the user/kernel test for the PID here along with the RW test
748 */
749 cmpldi cr0,r11,0 /* Check for user region */
750 ld r15,PACAPGD(r13) /* Load user pgdir */
751 beq htw_tlb_miss
753 /* XXX replace the RMW cycles with immediate loads + writes */
754 1: mfspr r10,SPRN_MAS1
755 cmpldi cr0,r11,8 /* Check for vmalloc region */
756 rlwinm r10,r10,0,16,1 /* Clear TID */
757 mtspr SPRN_MAS1,r10
758 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
759 beq+ htw_tlb_miss
761 /* We got a crappy address, just fault */
762 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
763 TLB_MISS_EPILOG_ERROR
764 b exc_instruction_storage_book3e
767 /*
768 * This is the guts of the second-level TLB miss handler for direct
769 * misses. We are entered with:
770 *
771 * r16 = virtual page table faulting address
772 * r15 = PGD pointer
773 * r14 = ESR
774 * r13 = PACA
775 * r12 = TLB exception frame in PACA
776 * r11 = crap (free to use)
777 * r10 = crap (free to use)
778 *
779 * It can be re-entered by the linear mapping miss handler. However, to
780 * avoid too much complication, it will save/restore things for us
781 */
782 htw_tlb_miss:
783 /* Search if we already have a TLB entry for that virtual address, and
784 * if we do, bail out.
785 *
786 * MAS1:IND should be already set based on MAS4
787 */
788 PPC_TLBSRX_DOT(0,r16)
789 beq htw_tlb_miss_done
791 /* Now, we need to walk the page tables. First check if we are in
792 * range.
793 */
794 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
795 bne- htw_tlb_miss_fault
797 /* Get the PGD pointer */
798 cmpldi cr0,r15,0
799 beq- htw_tlb_miss_fault
801 /* Get to PGD entry */
802 rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3
803 clrrdi r10,r11,3
804 ldx r15,r10,r15
805 cmpdi cr0,r15,0
806 bge htw_tlb_miss_fault
808 #ifndef CONFIG_PPC_64K_PAGES
809 /* Get to PUD entry */
810 rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
811 clrrdi r10,r11,3
812 ldx r15,r10,r15
813 cmpdi cr0,r15,0
814 bge htw_tlb_miss_fault
815 #endif /* CONFIG_PPC_64K_PAGES */
817 /* Get to PMD entry */
818 rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
819 clrrdi r10,r11,3
820 ldx r15,r10,r15
821 cmpdi cr0,r15,0
822 bge htw_tlb_miss_fault
824 /* Ok, we're all right, we can now create an indirect entry for
825 * a 1M or 256M page.
826 *
827 * The last trick is now that because we use "half" pages for
828 * the HTW (1M IND is 2K and 256M IND is 32K) we need to account
829 * for an added LSB bit to the RPN. For 64K pages, there is no
830 * problem as we already use 32K arrays (half PTE pages), but for
831 * 4K page we need to extract a bit from the virtual address and
832 * insert it into the "PA52" bit of the RPN.
833 */
834 #ifndef CONFIG_PPC_64K_PAGES
835 rlwimi r15,r16,32-9,20,20
836 #endif
837 /* Now we build the MAS:
838 *
839 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
840 * MAS 1 : Almost fully setup
841 * - PID already updated by caller if necessary
842 * - TSIZE for now is base ind page size always
843 * MAS 2 : Use defaults
844 * MAS 3+7 : Needs to be done
845 */
846 #ifdef CONFIG_PPC_64K_PAGES
847 ori r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT)
848 #else
849 ori r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
850 #endif
852 BEGIN_MMU_FTR_SECTION
853 srdi r16,r10,32
854 mtspr SPRN_MAS3,r10
855 mtspr SPRN_MAS7,r16
856 MMU_FTR_SECTION_ELSE
857 mtspr SPRN_MAS7_MAS3,r10
858 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
860 tlbwe
862 htw_tlb_miss_done:
863 /* We don't bother with restoring DEAR or ESR since we know we are
864 * level 0 and just going back to userland. They are only needed
865 * if you are going to take an access fault
866 */
867 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK)
868 TLB_MISS_EPILOG_SUCCESS
869 rfi
871 htw_tlb_miss_fault:
872 /* We need to check if it was an instruction miss. We know this
873 * though because r14 would contain -1
874 */
875 cmpdi cr0,r14,-1
876 beq 1f
877 mtspr SPRN_DEAR,r16
878 mtspr SPRN_ESR,r14
879 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT)
880 TLB_MISS_EPILOG_ERROR
881 b exc_data_storage_book3e
882 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT)
883 TLB_MISS_EPILOG_ERROR
884 b exc_instruction_storage_book3e
886 /*
887 * This is the guts of "any" level TLB miss handler for kernel linear
888 * mapping misses. We are entered with:
889 *
890 *
891 * r16 = faulting address
892 * r15 = crap (free to use)
893 * r14 = ESR (data) or -1 (instruction)
894 * r13 = PACA
895 * r12 = TLB exception frame in PACA
896 * r11 = crap (free to use)
897 * r10 = crap (free to use)
898 *
899 * In addition we know that we will not re-enter, so in theory, we could
900 * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later.
901 *
902 * We also need to be careful about MAS registers here & TLB reservation,
903 * as we know we'll have clobbered them if we interrupt the main TLB miss
904 * handlers in which case we probably want to do a full restart at level
905 * 0 rather than saving / restoring the MAS.
906 *
907 * Note: If we care about performance of that core, we can easily shuffle
908 * a few things around
909 */
910 tlb_load_linear:
911 /* For now, we assume the linear mapping is contiguous and stops at
912 * linear_map_top. We also assume the size is a multiple of 1G, thus
913 * we only use 1G pages for now. That might have to be changed in a
914 * final implementation, especially when dealing with hypervisors
915 */
916 ld r11,PACATOC(r13)
917 ld r11,linear_map_top@got(r11)
918 ld r10,0(r11)
919 cmpld cr0,r10,r16
920 bge tlb_load_linear_fault
922 /* MAS1 need whole new setup. */
923 li r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT)
924 oris r15,r15,MAS1_VALID@h /* MAS1 needs V and TSIZE */
925 mtspr SPRN_MAS1,r15
927 /* Already somebody there ? */
928 PPC_TLBSRX_DOT(0,r16)
929 beq tlb_load_linear_done
931 /* Now we build the remaining MAS. MAS0 and 2 should be fine
932 * with their defaults, which leaves us with MAS 3 and 7. The
933 * mapping is linear, so we just take the address, clear the
934 * region bits, and or in the permission bits which are currently
935 * hard wired
936 */
937 clrrdi r10,r16,30 /* 1G page index */
938 clrldi r10,r10,4 /* clear region bits */
939 ori r10,r10,MAS3_SR|MAS3_SW|MAS3_SX
941 BEGIN_MMU_FTR_SECTION
942 srdi r16,r10,32
943 mtspr SPRN_MAS3,r10
944 mtspr SPRN_MAS7,r16
945 MMU_FTR_SECTION_ELSE
946 mtspr SPRN_MAS7_MAS3,r10
947 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
949 tlbwe
951 tlb_load_linear_done:
952 /* We use the "error" epilog for success as we do want to
953 * restore to the initial faulting context, whatever it was.
954 * We do that because we can't resume a fault within a TLB
955 * miss handler, due to MAS and TLB reservation being clobbered.
956 */
957 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR)
958 TLB_MISS_EPILOG_ERROR
959 rfi
961 tlb_load_linear_fault:
962 /* We keep the DEAR and ESR around, this shouldn't have happened */
963 cmpdi cr0,r14,-1
964 beq 1f
965 TLB_MISS_EPILOG_ERROR_SPECIAL
966 b exc_data_storage_book3e
967 1: TLB_MISS_EPILOG_ERROR_SPECIAL
968 b exc_instruction_storage_book3e
971 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS
972 .tlb_stat_inc:
973 1: ldarx r8,0,r9
974 addi r8,r8,1
975 stdcx. r8,0,r9
976 bne- 1b
977 blr
978 #endif