arch/powerpc/platforms/cell/spu_priv1_mmio.c

   1 /*
   2  * spu hypervisor abstraction for direct hardware access.
   3  *
   4  *  (C) Copyright IBM Deutschland Entwicklung GmbH 2005
   5  *  Copyright 2006 Sony Corp.
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; version 2 of the License.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 #include <linux/interrupt.h>
  22 #include <linux/list.h>
  23 #include <linux/ptrace.h>
  24 #include <linux/wait.h>
  25 #include <linux/mm.h>
  26 #include <linux/io.h>
  27 #include <linux/mutex.h>
  28 #include <linux/device.h>
  29 #include <linux/sched.h>
  30
  31 #include <asm/spu.h>
  32 #include <asm/spu_priv1.h>
  33 #include <asm/firmware.h>
  34 #include <asm/prom.h>
  35
  36 #include "interrupt.h"
  37 #include "spu_priv1_mmio.h"
  38
  39 static void int_mask_and(struct spu *spu, int class, u64 mask)
  40 {
  41         u64 old_mask;
  42
  43         old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
  44         out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask);
  45 }
  46
  47 static void int_mask_or(struct spu *spu, int class, u64 mask)
  48 {
  49         u64 old_mask;
  50
  51         old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
  52         out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask);
  53 }
  54
  55 static void int_mask_set(struct spu *spu, int class, u64 mask)
  56 {
  57         out_be64(&spu->priv1->int_mask_RW[class], mask);
  58 }
  59
  60 static u64 int_mask_get(struct spu *spu, int class)
  61 {
  62         return in_be64(&spu->priv1->int_mask_RW[class]);
  63 }
  64
  65 static void int_stat_clear(struct spu *spu, int class, u64 stat)
  66 {
  67         out_be64(&spu->priv1->int_stat_RW[class], stat);
  68 }
  69
  70 static u64 int_stat_get(struct spu *spu, int class)
  71 {
  72         return in_be64(&spu->priv1->int_stat_RW[class]);
  73 }
  74
  75 static void cpu_affinity_set(struct spu *spu, int cpu)
  76 {
  77         u64 target;
  78         u64 route;
  79
  80         if (nr_cpus_node(spu->node)) {
  81                 const struct cpumask *spumask = cpumask_of_node(spu->node),
  82                         *cpumask = cpumask_of_node(cpu_to_node(cpu));
  83
  84                 if (!cpumask_intersects(spumask, cpumask))
  85                         return;
  86         }
  87
  88         target = iic_get_target_id(cpu);
  89         route = target << 48 | target << 32 | target << 16;
  90         out_be64(&spu->priv1->int_route_RW, route);
  91 }
  92
  93 static u64 mfc_dar_get(struct spu *spu)
  94 {
  95         return in_be64(&spu->priv1->mfc_dar_RW);
  96 }
  97
  98 static u64 mfc_dsisr_get(struct spu *spu)
  99 {
 100         return in_be64(&spu->priv1->mfc_dsisr_RW);
 101 }
 102
 103 static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
 104 {
 105         out_be64(&spu->priv1->mfc_dsisr_RW, dsisr);
 106 }
 107
 108 static void mfc_sdr_setup(struct spu *spu)
 109 {
 110         out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
 111 }
 112
 113 static void mfc_sr1_set(struct spu *spu, u64 sr1)
 114 {
 115         out_be64(&spu->priv1->mfc_sr1_RW, sr1);
 116 }
 117
 118 static u64 mfc_sr1_get(struct spu *spu)
 119 {
 120         return in_be64(&spu->priv1->mfc_sr1_RW);
 121 }
 122
 123 static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
 124 {
 125         out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id);
 126 }
 127
 128 static u64 mfc_tclass_id_get(struct spu *spu)
 129 {
 130         return in_be64(&spu->priv1->mfc_tclass_id_RW);
 131 }
 132
 133 static void tlb_invalidate(struct spu *spu)
 134 {
 135         out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul);
 136 }
 137
 138 static void resource_allocation_groupID_set(struct spu *spu, u64 id)
 139 {
 140         out_be64(&spu->priv1->resource_allocation_groupID_RW, id);
 141 }
 142
 143 static u64 resource_allocation_groupID_get(struct spu *spu)
 144 {
 145         return in_be64(&spu->priv1->resource_allocation_groupID_RW);
 146 }
 147
 148 static void resource_allocation_enable_set(struct spu *spu, u64 enable)
 149 {
 150         out_be64(&spu->priv1->resource_allocation_enable_RW, enable);
 151 }
 152
 153 static u64 resource_allocation_enable_get(struct spu *spu)
 154 {
 155         return in_be64(&spu->priv1->resource_allocation_enable_RW);
 156 }
 157
 158 const struct spu_priv1_ops spu_priv1_mmio_ops =
 159 {
 160         .int_mask_and = int_mask_and,
 161         .int_mask_or = int_mask_or,
 162         .int_mask_set = int_mask_set,
 163         .int_mask_get = int_mask_get,
 164         .int_stat_clear = int_stat_clear,
 165         .int_stat_get = int_stat_get,
 166         .cpu_affinity_set = cpu_affinity_set,
 167         .mfc_dar_get = mfc_dar_get,
 168         .mfc_dsisr_get = mfc_dsisr_get,
 169         .mfc_dsisr_set = mfc_dsisr_set,
 170         .mfc_sdr_setup = mfc_sdr_setup,
 171         .mfc_sr1_set = mfc_sr1_set,
 172         .mfc_sr1_get = mfc_sr1_get,
 173         .mfc_tclass_id_set = mfc_tclass_id_set,
 174         .mfc_tclass_id_get = mfc_tclass_id_get,
 175         .tlb_invalidate = tlb_invalidate,
 176         .resource_allocation_groupID_set = resource_allocation_groupID_set,
 177         .resource_allocation_groupID_get = resource_allocation_groupID_get,
 178         .resource_allocation_enable_set = resource_allocation_enable_set,
 179         .resource_allocation_enable_get = resource_allocation_enable_get,
 180 };