sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / Documentation / devicetree / bindings / cpufreq / cpufreq-st.txt
blobd91a02a3b6b0721a3e3ccb59367cc47f2f062c1f
1 Binding for ST's CPUFreq driver
2 ===============================
4 ST's CPUFreq driver attempts to read 'process' and 'version' attributes
5 from the SoC, then supplies the OPP framework with 'prop' and 'supported
6 hardware' information respectively.  The framework is then able to read
7 the DT and operate in the usual way.
9 For more information about the expected DT format [See: ../opp/opp.txt].
11 Frequency Scaling only
12 ----------------------
14 No vendor specific driver required for this.
16 Located in CPU's node:
18 - operating-points              : [See: ../power/opp.txt]
20 Example [safe]
21 --------------
23 cpus {
24         cpu@0 {
25                                  /* kHz     uV   */
26                 operating-points = <1500000 0
27                                     1200000 0
28                                     800000  0
29                                     500000  0>;
30         };
33 Dynamic Voltage and Frequency Scaling (DVFS)
34 --------------------------------------------
36 This requires the ST CPUFreq driver to supply 'process' and 'version' info.
38 Located in CPU's node:
40 - operating-points-v2           : [See ../power/opp.txt]
42 Example [unsafe]
43 ----------------
45 cpus {
46         cpu@0 {
47                 operating-points-v2     = <&cpu0_opp_table>;
48         };
51 cpu0_opp_table: opp_table {
52         compatible = "operating-points-v2";
54         /* ############################################################### */
55         /* # WARNING: Do not attempt to copy/replicate these nodes,      # */
56         /* #          they are only to be supplied by the bootloader !!! # */
57         /* ############################################################### */
58         opp0 {
59                 /*                         Major       Minor       Substrate */
60                 /*                         2           all         all       */
61                 opp-supported-hw        = <0x00000004  0xffffffff  0xffffffff>;
62                 opp-hz                  = /bits/ 64 <1500000000>;
63                 clock-latency-ns        = <10000000>;
65                 opp-microvolt-pcode0    = <1200000>;
66                 opp-microvolt-pcode1    = <1200000>;
67                 opp-microvolt-pcode2    = <1200000>;
68                 opp-microvolt-pcode3    = <1200000>;
69                 opp-microvolt-pcode4    = <1170000>;
70                 opp-microvolt-pcode5    = <1140000>;
71                 opp-microvolt-pcode6    = <1100000>;
72                 opp-microvolt-pcode7    = <1070000>;
73         };
75         opp1 {
76                 /*                         Major       Minor       Substrate */
77                 /*                         all         all         all       */
78                 opp-supported-hw        = <0xffffffff  0xffffffff  0xffffffff>;
79                 opp-hz                  = /bits/ 64 <1200000000>;
80                 clock-latency-ns        = <10000000>;
82                 opp-microvolt-pcode0    = <1110000>;
83                 opp-microvolt-pcode1    = <1150000>;
84                 opp-microvolt-pcode2    = <1100000>;
85                 opp-microvolt-pcode3    = <1080000>;
86                 opp-microvolt-pcode4    = <1040000>;
87                 opp-microvolt-pcode5    = <1020000>;
88                 opp-microvolt-pcode6    = <980000>;
89                 opp-microvolt-pcode7    = <930000>;
90         };