4 The Mediatek DPI function block is a sink of the display subsystem and
5 provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
9 - compatible: "mediatek,<chip>-dpi"
10 - reg: Physical base address and length of the controller's registers
11 - interrupts: The interrupt signal from the function block.
12 - clocks: device clocks
13 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
14 - clock-names: must contain "pixel", "engine", and "pll"
15 - port: Output port node with endpoint definitions as described in
16 Documentation/devicetree/bindings/graph.txt. This port should be connected
17 to the input port of an attached HDMI or LVDS encoder chip.
22 compatible = "mediatek,mt8173-dpi";
23 reg = <0 0x1401d000 0 0x1000>;
24 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
25 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
26 <&mmsys CLK_MM_DPI_ENGINE>,
27 <&apmixedsys CLK_APMIXED_TVDPLL>;
28 clock-names = "pixel", "engine", "pll";
32 remote-endpoint = <&hdmi0_in>;