sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / Documentation / devicetree / bindings / display / rockchip / dw_mipi_dsi_rockchip.txt
blob1753f0cc6fad6c799351ed35e412dd7ed97514ab
1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
2 ================================
4 Required properties:
5 - #address-cells: Should be <1>.
6 - #size-cells: Should be <0>.
7 - compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
8 - reg: Represent the physical address range of the controller.
9 - interrupts: Represent the controller's interrupt to the CPU(s).
10 - clocks, clock-names: Phandles to the controller's pll reference
11   clock(ref) and APB clock(pclk), as described in [1].
12 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
13 - ports: contain a port node with endpoint definitions as defined in [2].
14   For vopb,set the reg = <0> and set the reg = <1> for vopl.
16 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
19 Example:
20         mipi_dsi: mipi@ff960000 {
21                 #address-cells = <1>;
22                 #size-cells = <0>;
23                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
24                 reg = <0xff960000 0x4000>;
25                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
26                 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
27                 clock-names = "ref", "pclk";
28                 rockchip,grf = <&grf>;
29                 status = "okay";
31                 ports {
32                         #address-cells = <1>;
33                         #size-cells = <0>;
34                         reg = <1>;
36                         mipi_in: port {
37                                 #address-cells = <1>;
38                                 #size-cells = <0>;
39                                 mipi_in_vopb: endpoint@0 {
40                                         reg = <0>;
41                                         remote-endpoint = <&vopb_out_mipi>;
42                                 };
43                                 mipi_in_vopl: endpoint@1 {
44                                         reg = <1>;
45                                         remote-endpoint = <&vopl_out_mipi>;
46                                 };
47                         };
48                 };
50                 panel {
51                         compatible ="boe,tv080wum-nl0";
52                         reg = <0>;
54                         enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
55                         pinctrl-names = "default";
56                         pinctrl-0 = <&lcd_en>;
57                         backlight = <&backlight>;
58                         status = "okay";
59                 };
60         };