1 TB10x Top Level Interrupt Controller
2 ====================================
4 The Abilis TB10x SOC contains a custom interrupt controller. It performs
5 one-to-one mapping of external interrupt sources to CPU interrupts and
6 provides support for reconfigurable trigger modes.
11 - compatible: Should be "abilis,tb10x-ictl"
12 - reg: specifies physical base address and size of register range.
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
15 source connected to this controller. The value shall be 2.
16 - interrupt-parent: Specifies the parent interrupt controller.
17 - interrupts: Specifies the list of interrupt lines which are handled by
18 the interrupt controller in the parent controller's notation. Interrupts
19 are mapped one-to-one to parent interrupts.
24 intc: interrupt-controller { /* Parent interrupt controller */
26 #interrupt-cells = <1>; /* For example below */
30 tb10x_ictl: pic@2000 { /* TB10x interrupt controller */
31 compatible = "abilis,tb10x-ictl";
34 #interrupt-cells = <2>;
35 interrupt-parent = <&intc>;
36 interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
37 20 21 22 23 24 25 26 27 28 29 30 31>;