1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
10 node of the VIPP represents as a top level node of the pipeline and defines
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
18 in Documentation/devicetree/bindings/dma/dma.txt) per port. Each port
19 requires a DMA channel with the identifier string set to "port" followed by
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
24 Required port properties:
26 - direction: should be either "input" or "output" depending on the direction
32 compatible = "xlnx,video";
33 dmas = <&vdma_1 1>, <&vdma_3 1>;
34 dma-names = "port0", "port1";
44 remote-endpoint = <&scaler0_out>;
51 remote-endpoint = <&switch_out1>;