Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt

   1 PXA3xx NAND DT bindings
   2
   3 Required properties:
   4
   5  - compatible:          Should be set to one of the following:
   6                         marvell,pxa3xx-nand
   7                         marvell,armada370-nand
   8  - reg:                 The register base for the controller
   9  - interrupts:          The interrupt to map
  10  - #address-cells:      Set to <1> if the node includes partitions
  11
  12 Optional properties:
  13
  14  - dmas:                        dma data channel, see dma.txt binding doc
  15  - marvell,nand-enable-arbiter: Set to enable the bus arbiter
  16  - marvell,nand-keep-config:    Set to keep the NAND controller config as set
  17                                 by the bootloader
  18  - num-cs:                      Number of chipselect lines to use
  19  - nand-on-flash-bbt:           boolean to enable on flash bbt option if
  20                                 not present false
  21  - nand-ecc-strength:           number of bits to correct per ECC step
  22  - nand-ecc-step-size:          number of data bytes covered by a single ECC step
  23
  24 The following ECC strength and step size are currently supported:
  25
  26  - nand-ecc-strength = <1>, nand-ecc-step-size = <512>
  27  - nand-ecc-strength = <4>, nand-ecc-step-size = <512>
  28  - nand-ecc-strength = <8>, nand-ecc-step-size = <512>
  29
  30 Example:
  31
  32         nand0: nand@43100000 {
  33                 compatible = "marvell,pxa3xx-nand";
  34                 reg = <0x43100000 90>;
  35                 interrupts = <45>;
  36                 dmas = <&pdma 97 0>;
  37                 dma-names = "data";
  38                 #address-cells = <1>;
  39
  40                 marvell,nand-enable-arbiter;
  41                 marvell,nand-keep-config;
  42                 num-cs = <1>;
  43
  44                 /* partitions (optional) */
  45         };
  46