1 * Qualcomm NAND controller
4 - compatible: should be "qcom,ipq806x-nand"
5 - reg: MMIO address range
6 - clocks: must contain core clock and always on clock
7 - clock-names: must contain "core" for the core clock and "aon" for the
9 - dmas: DMA specifier, consisting of a phandle to the ADM DMA
10 controller node and the channel number to be used for
11 NAND. Refer to dma.txt and qcom_adm.txt for more details
12 - dma-names: must be "rxtx"
13 - qcom,cmd-crci: must contain the ADM command type CRCI block instance
14 number specified for the NAND controller on the given
16 - qcom,data-crci: must contain the ADM data type CRCI block instance
17 number specified for the NAND controller on the given
19 - #address-cells: <1> - subnodes give the chip-select number
24 Each controller may contain one or more subnodes to represent enabled
25 chip-selects which (may) contain NAND flash chips. Their properties are as
29 - compatible: should contain "qcom,nandcs"
30 - reg: a single integer representing the chip-select
31 number (e.g., 0, 1, 2, etc.)
32 - #address-cells: see partition.txt
33 - #size-cells: see partition.txt
34 - nand-ecc-strength: see nand.txt
35 - nand-ecc-step-size: must be 512. see nand.txt for more details.
38 - nand-bus-width: see nand.txt
40 Each nandcs device node may optionally contain a 'partitions' sub-node, which
41 further contains sub-nodes describing the flash partition mapping. See
42 partition.txt for more detail.
47 compatible = "qcom,ebi2-nandc";
48 reg = <0x1ac00000 0x800>;
50 clocks = <&gcc EBI2_CLK>,
52 clock-names = "core", "aon";
63 compatible = "qcom,nandcs";
66 nand-ecc-strength = <4>;
67 nand-ecc-step-size = <512>;
71 compatible = "fixed-partitions";
82 reg = <0x58a0000 0x4000000>;