sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / Documentation / devicetree / bindings / net / brcm,mdio-mux-iproc.txt
blobdfe287a5d6f292cdf5b866dddeb80e95bff31c6d
1 Properties for an MDIO bus multiplexer found in Broadcom iProc based SoCs.
3 This MDIO bus multiplexer defines buses that could be internal as well as
4 external to SoCs and could accept MDIO transaction compatible to C-22 or
5 C-45 Clause. When child bus is selected, one needs to select these two
6 properties as well to generate desired MDIO transaction on appropriate bus.
8 Required properties in addition to the generic multiplexer properties:
10 MDIO multiplexer node:
11 - compatible: brcm,mdio-mux-iproc.
13 Every non-ethernet PHY requires a compatible so that it could be probed based
14 on this compatible string.
16 Additional information regarding generic multiplexer properties can be found
17 at- Documentation/devicetree/bindings/net/mdio-mux.txt
20 for example:
21                 mdio_mux_iproc: mdio-mux@6602023c {
22                         compatible = "brcm,mdio-mux-iproc";
23                         reg = <0x6602023c 0x14>;
24                         #address-cells = <1>;
25                         #size-cells = <0>;
27                         mdio@0 {
28                                 reg = <0x0>;
29                                 #address-cells = <1>;
30                                 #size-cells = <0>;
32                                 pci_phy0: pci-phy@0 {
33                                         compatible = "brcm,ns2-pcie-phy";
34                                         reg = <0x0>;
35                                         #phy-cells = <0>;
36                                 };
37                         };
39                         mdio@7 {
40                                 reg = <0x7>;
41                                 #address-cells = <1>;
42                                 #size-cells = <0>;
44                                 pci_phy1: pci-phy@0 {
45                                         compatible = "brcm,ns2-pcie-phy";
46                                         reg = <0x0>;
47                                         #phy-cells = <0>;
48                                 };
49                         };
50                         mdio@10 {
51                                 reg = <0x10>;
52                                 #address-cells = <1>;
53                                 #size-cells = <0>;
55                                 gphy0: eth-phy@10 {
56                                         reg = <0x10>;
57                                 };
58                         };
59                 };