Documentation/devicetree/bindings/pci/qcom,pcie.txt

   1 * Qualcomm PCI express root complex
   2
   3 - compatible:
   4         Usage: required
   5         Value type: <stringlist>
   6         Definition: Value should contain
   7                         - "qcom,pcie-ipq8064" for ipq8064
   8                         - "qcom,pcie-apq8064" for apq8064
   9                         - "qcom,pcie-apq8084" for apq8084
  10                         - "qcom,pcie-msm8996" for msm8996 or apq8096
  11
  12 - reg:
  13         Usage: required
  14         Value type: <prop-encoded-array>
  15         Definition: Register ranges as listed in the reg-names property
  16
  17 - reg-names:
  18         Usage: required
  19         Value type: <stringlist>
  20         Definition: Must include the following entries
  21                         - "parf"   Qualcomm specific registers
  22                         - "dbi"    Designware PCIe registers
  23                         - "elbi"   External local bus interface registers
  24                         - "config" PCIe configuration space
  25
  26 - device_type:
  27         Usage: required
  28         Value type: <string>
  29         Definition: Should be "pci". As specified in designware-pcie.txt
  30
  31 - #address-cells:
  32         Usage: required
  33         Value type: <u32>
  34         Definition: Should be 3. As specified in designware-pcie.txt
  35
  36 - #size-cells:
  37         Usage: required
  38         Value type: <u32>
  39         Definition: Should be 2. As specified in designware-pcie.txt
  40
  41 - ranges:
  42         Usage: required
  43         Value type: <prop-encoded-array>
  44         Definition: As specified in designware-pcie.txt
  45
  46 - interrupts:
  47         Usage: required
  48         Value type: <prop-encoded-array>
  49         Definition: MSI interrupt
  50
  51 - interrupt-names:
  52         Usage: required
  53         Value type: <stringlist>
  54         Definition: Should contain "msi"
  55
  56 - #interrupt-cells:
  57         Usage: required
  58         Value type: <u32>
  59         Definition: Should be 1. As specified in designware-pcie.txt
  60
  61 - interrupt-map-mask:
  62         Usage: required
  63         Value type: <prop-encoded-array>
  64         Definition: As specified in designware-pcie.txt
  65
  66 - interrupt-map:
  67         Usage: required
  68         Value type: <prop-encoded-array>
  69         Definition: As specified in designware-pcie.txt
  70
  71 - clocks:
  72         Usage: required
  73         Value type: <prop-encoded-array>
  74         Definition: List of phandle and clock specifier pairs as listed
  75                     in clock-names property
  76
  77 - clock-names:
  78         Usage: required
  79         Value type: <stringlist>
  80         Definition: Should contain the following entries
  81                         - "iface"       Configuration AHB clock
  82
  83 - clock-names:
  84         Usage: required for ipq/apq8064
  85         Value type: <stringlist>
  86         Definition: Should contain the following entries
  87                         - "core"        Clocks the pcie hw block
  88                         - "phy"         Clocks the pcie PHY block
  89 - clock-names:
  90         Usage: required for apq8084
  91         Value type: <stringlist>
  92         Definition: Should contain the following entries
  93                         - "aux"         Auxiliary (AUX) clock
  94                         - "bus_master"  Master AXI clock
  95                         - "bus_slave"   Slave AXI clock
  96
  97 - clock-names:
  98         Usage: required for msm8996/apq8096
  99         Value type: <stringlist>
 100         Definition: Should contain the following entries
 101                         - "pipe"        Pipe Clock driving internal logic
 102                         - "aux"         Auxiliary (AUX) clock
 103                         - "cfg"         Configuration clock
 104                         - "bus_master"  Master AXI clock
 105                         - "bus_slave"   Slave AXI clock
 106
 107 - resets:
 108         Usage: required
 109         Value type: <prop-encoded-array>
 110         Definition: List of phandle and reset specifier pairs as listed
 111                     in reset-names property
 112
 113 - reset-names:
 114         Usage: required for ipq/apq8064
 115         Value type: <stringlist>
 116         Definition: Should contain the following entries
 117                         - "axi"  AXI reset
 118                         - "ahb"  AHB reset
 119                         - "por"  POR reset
 120                         - "pci"  PCI reset
 121                         - "phy"  PHY reset
 122
 123 - reset-names:
 124         Usage: required for apq8084
 125         Value type: <stringlist>
 126         Definition: Should contain the following entries
 127                         - "core" Core reset
 128
 129 - power-domains:
 130         Usage: required for apq8084 and msm8996/apq8096
 131         Value type: <prop-encoded-array>
 132         Definition: A phandle and power domain specifier pair to the
 133                     power domain which is responsible for collapsing
 134                     and restoring power to the peripheral
 135
 136 - vdda-supply:
 137         Usage: required
 138         Value type: <phandle>
 139         Definition: A phandle to the core analog power supply
 140
 141 - vdda_phy-supply:
 142         Usage: required for ipq/apq8064
 143         Value type: <phandle>
 144         Definition: A phandle to the analog power supply for PHY
 145
 146 - vdda_refclk-supply:
 147         Usage: required for ipq/apq8064
 148         Value type: <phandle>
 149         Definition: A phandle to the analog power supply for IC which generates
 150                     reference clock
 151
 152 - phys:
 153         Usage: required for apq8084
 154         Value type: <phandle>
 155         Definition: List of phandle(s) as listed in phy-names property
 156
 157 - phy-names:
 158         Usage: required for apq8084
 159         Value type: <stringlist>
 160         Definition: Should contain "pciephy"
 161
 162 - <name>-gpios:
 163         Usage: optional
 164         Value type: <prop-encoded-array>
 165         Definition: List of phandle and gpio specifier pairs. Should contain
 166                         - "perst-gpios" PCIe endpoint reset signal line
 167                         - "wake-gpios"  PCIe endpoint wake signal line
 168
 169 * Example for ipq/apq8064
 170         pcie@1b500000 {
 171                 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
 172                 reg = <0x1b500000 0x1000
 173                        0x1b502000 0x80
 174                        0x1b600000 0x100
 175                        0x0ff00000 0x100000>;
 176                 reg-names = "dbi", "elbi", "parf", "config";
 177                 device_type = "pci";
 178                 linux,pci-domain = <0>;
 179                 bus-range = <0x00 0xff>;
 180                 num-lanes = <1>;
 181                 #address-cells = <3>;
 182                 #size-cells = <2>;
 183                 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
 184                           0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
 185                 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
 186                 interrupt-names = "msi";
 187                 #interrupt-cells = <1>;
 188                 interrupt-map-mask = <0 0 0 0x7>;
 189                 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 190                                 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 191                                 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 192                                 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 193                 clocks = <&gcc PCIE_A_CLK>,
 194                          <&gcc PCIE_H_CLK>,
 195                          <&gcc PCIE_PHY_CLK>;
 196                 clock-names = "core", "iface", "phy";
 197                 resets = <&gcc PCIE_ACLK_RESET>,
 198                          <&gcc PCIE_HCLK_RESET>,
 199                          <&gcc PCIE_POR_RESET>,
 200                          <&gcc PCIE_PCI_RESET>,
 201                          <&gcc PCIE_PHY_RESET>;
 202                 reset-names = "axi", "ahb", "por", "pci", "phy";
 203                 pinctrl-0 = <&pcie_pins_default>;
 204                 pinctrl-names = "default";
 205         };
 206
 207 * Example for apq8084
 208         pcie0@fc520000 {
 209                 compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
 210                 reg = <0xfc520000 0x2000>,
 211                       <0xff000000 0x1000>,
 212                       <0xff001000 0x1000>,
 213                       <0xff002000 0x2000>;
 214                 reg-names = "parf", "dbi", "elbi", "config";
 215                 device_type = "pci";
 216                 linux,pci-domain = <0>;
 217                 bus-range = <0x00 0xff>;
 218                 num-lanes = <1>;
 219                 #address-cells = <3>;
 220                 #size-cells = <2>;
 221                 ranges = <0x81000000 0 0          0xff200000 0 0x00100000   /* I/O */
 222                           0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
 223                 interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
 224                 interrupt-names = "msi";
 225                 #interrupt-cells = <1>;
 226                 interrupt-map-mask = <0 0 0 0x7>;
 227                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 228                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 229                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 230                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 231                 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 232                          <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 233                          <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
 234                          <&gcc GCC_PCIE_0_AUX_CLK>;
 235                 clock-names = "iface", "master_bus", "slave_bus", "aux";
 236                 resets = <&gcc GCC_PCIE_0_BCR>;
 237                 reset-names = "core";
 238                 power-domains = <&gcc PCIE0_GDSC>;
 239                 vdda-supply = <&pma8084_l3>;
 240                 phys = <&pciephy0>;
 241                 phy-names = "pciephy";
 242                 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
 243                 pinctrl-0 = <&pcie0_pins_default>;
 244                 pinctrl-names = "default";
 245         };