drivers/acpi/pci_mcfg.c

   1 /*
   2  * Copyright (C) 2016 Broadcom
   3  *      Author: Jayachandran C <jchandra@broadcom.com>
   4  * Copyright (C) 2016 Semihalf
   5  *      Author: Tomasz Nowicki <tn@semihalf.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License, version 2, as
   9  * published by the Free Software Foundation (the "GPL").
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License version 2 (GPLv2) for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * version 2 (GPLv2) along with this source code.
  18  */
  19
  20 #define pr_fmt(fmt) "ACPI: " fmt
  21
  22 #include <linux/kernel.h>
  23 #include <linux/pci.h>
  24 #include <linux/pci-acpi.h>
  25 #include <linux/pci-ecam.h>
  26
  27 /* Structure to hold entries from the MCFG table */
  28 struct mcfg_entry {
  29         struct list_head        list;
  30         phys_addr_t             addr;
  31         u16                     segment;
  32         u8                      bus_start;
  33         u8                      bus_end;
  34 };
  35
  36 #ifdef CONFIG_PCI_QUIRKS
  37 struct mcfg_fixup {
  38         char oem_id[ACPI_OEM_ID_SIZE + 1];
  39         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
  40         u32 oem_revision;
  41         u16 segment;
  42         struct resource bus_range;
  43         struct pci_ecam_ops *ops;
  44         struct resource cfgres;
  45 };
  46
  47 #define MCFG_BUS_RANGE(start, end)      DEFINE_RES_NAMED((start),       \
  48                                                 ((end) - (start) + 1),  \
  49                                                 NULL, IORESOURCE_BUS)
  50 #define MCFG_BUS_ANY                    MCFG_BUS_RANGE(0x0, 0xff)
  51
  52 static struct mcfg_fixup mcfg_quirks[] = {
  53 /*      { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
  54
  55 #define QCOM_ECAM32(seg) \
  56         { "QCOM  ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
  57         QCOM_ECAM32(0),
  58         QCOM_ECAM32(1),
  59         QCOM_ECAM32(2),
  60         QCOM_ECAM32(3),
  61         QCOM_ECAM32(4),
  62         QCOM_ECAM32(5),
  63         QCOM_ECAM32(6),
  64         QCOM_ECAM32(7),
  65
  66 #define HISI_QUAD_DOM(table_id, seg, ops) \
  67         { "HISI  ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
  68         { "HISI  ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
  69         { "HISI  ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
  70         { "HISI  ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
  71         HISI_QUAD_DOM("HIP05   ",  0, &hisi_pcie_ops),
  72         HISI_QUAD_DOM("HIP06   ",  0, &hisi_pcie_ops),
  73         HISI_QUAD_DOM("HIP07   ",  0, &hisi_pcie_ops),
  74         HISI_QUAD_DOM("HIP07   ",  4, &hisi_pcie_ops),
  75         HISI_QUAD_DOM("HIP07   ",  8, &hisi_pcie_ops),
  76         HISI_QUAD_DOM("HIP07   ", 12, &hisi_pcie_ops),
  77
  78 #define THUNDER_PEM_RES(addr, node) \
  79         DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
  80 #define THUNDER_PEM_QUIRK(rev, node) \
  81         { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY,       \
  82           &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) },  \
  83         { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY,       \
  84           &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) },  \
  85         { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY,       \
  86           &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) },  \
  87         { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY,       \
  88           &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) },  \
  89         { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY,       \
  90           &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) },  \
  91         { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY,       \
  92           &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
  93         /* SoC pass2.x */
  94         THUNDER_PEM_QUIRK(1, 0),
  95         THUNDER_PEM_QUIRK(1, 1),
  96
  97 #define THUNDER_ECAM_QUIRK(rev, seg)                                    \
  98         { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY,                 \
  99         &pci_thunder_ecam_ops }
 100         /* SoC pass1.x */
 101         THUNDER_PEM_QUIRK(2, 0),        /* off-chip devices */
 102         THUNDER_PEM_QUIRK(2, 1),        /* off-chip devices */
 103         THUNDER_ECAM_QUIRK(2,  0),
 104         THUNDER_ECAM_QUIRK(2,  1),
 105         THUNDER_ECAM_QUIRK(2,  2),
 106         THUNDER_ECAM_QUIRK(2,  3),
 107         THUNDER_ECAM_QUIRK(2, 10),
 108         THUNDER_ECAM_QUIRK(2, 11),
 109         THUNDER_ECAM_QUIRK(2, 12),
 110         THUNDER_ECAM_QUIRK(2, 13),
 111
 112 #define XGENE_V1_ECAM_MCFG(rev, seg) \
 113         {"APM   ", "XGENE   ", rev, seg, MCFG_BUS_ANY, \
 114                 &xgene_v1_pcie_ecam_ops }
 115 #define XGENE_V2_ECAM_MCFG(rev, seg) \
 116         {"APM   ", "XGENE   ", rev, seg, MCFG_BUS_ANY, \
 117                 &xgene_v2_pcie_ecam_ops }
 118         /* X-Gene SoC with v1 PCIe controller */
 119         XGENE_V1_ECAM_MCFG(1, 0),
 120         XGENE_V1_ECAM_MCFG(1, 1),
 121         XGENE_V1_ECAM_MCFG(1, 2),
 122         XGENE_V1_ECAM_MCFG(1, 3),
 123         XGENE_V1_ECAM_MCFG(1, 4),
 124         XGENE_V1_ECAM_MCFG(2, 0),
 125         XGENE_V1_ECAM_MCFG(2, 1),
 126         XGENE_V1_ECAM_MCFG(2, 2),
 127         XGENE_V1_ECAM_MCFG(2, 3),
 128         XGENE_V1_ECAM_MCFG(2, 4),
 129         /* X-Gene SoC with v2.1 PCIe controller */
 130         XGENE_V2_ECAM_MCFG(3, 0),
 131         XGENE_V2_ECAM_MCFG(3, 1),
 132         /* X-Gene SoC with v2.2 PCIe controller */
 133         XGENE_V2_ECAM_MCFG(4, 0),
 134         XGENE_V2_ECAM_MCFG(4, 1),
 135         XGENE_V2_ECAM_MCFG(4, 2),
 136 };
 137
 138 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
 139 static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
 140 static u32 mcfg_oem_revision;
 141
 142 static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
 143                                   struct resource *bus_range)
 144 {
 145         if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
 146             !memcmp(f->oem_table_id, mcfg_oem_table_id,
 147                     ACPI_OEM_TABLE_ID_SIZE) &&
 148             f->oem_revision == mcfg_oem_revision &&
 149             f->segment == segment &&
 150             resource_contains(&f->bus_range, bus_range))
 151                 return 1;
 152
 153         return 0;
 154 }
 155 #endif
 156
 157 static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
 158                                   struct resource *cfgres,
 159                                   struct pci_ecam_ops **ecam_ops)
 160 {
 161 #ifdef CONFIG_PCI_QUIRKS
 162         u16 segment = root->segment;
 163         struct resource *bus_range = &root->secondary;
 164         struct mcfg_fixup *f;
 165         int i;
 166
 167         for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
 168                 if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
 169                         if (f->cfgres.start)
 170                                 *cfgres = f->cfgres;
 171                         if (f->ops)
 172                                 *ecam_ops =  f->ops;
 173                         dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
 174                                  cfgres, bus_range, *ecam_ops);
 175                         return;
 176                 }
 177         }
 178 #endif
 179 }
 180
 181 /* List to save MCFG entries */
 182 static LIST_HEAD(pci_mcfg_list);
 183
 184 int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
 185                     struct pci_ecam_ops **ecam_ops)
 186 {
 187         struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
 188         struct resource *bus_res = &root->secondary;
 189         u16 seg = root->segment;
 190         struct mcfg_entry *e;
 191         struct resource res;
 192
 193         /* Use address from _CBA if present, otherwise lookup MCFG */
 194         if (root->mcfg_addr)
 195                 goto skip_lookup;
 196
 197         /*
 198          * We expect exact match, unless MCFG entry end bus covers more than
 199          * specified by caller.
 200          */
 201         list_for_each_entry(e, &pci_mcfg_list, list) {
 202                 if (e->segment == seg && e->bus_start == bus_res->start &&
 203                     e->bus_end >= bus_res->end) {
 204                         root->mcfg_addr = e->addr;
 205                 }
 206
 207         }
 208
 209 skip_lookup:
 210         memset(&res, 0, sizeof(res));
 211         if (root->mcfg_addr) {
 212                 res.start = root->mcfg_addr + (bus_res->start << 20);
 213                 res.end = res.start + (resource_size(bus_res) << 20) - 1;
 214                 res.flags = IORESOURCE_MEM;
 215         }
 216
 217         /*
 218          * Allow quirks to override default ECAM ops and CFG resource
 219          * range.  This may even fabricate a CFG resource range in case
 220          * MCFG does not have it.  Invalid CFG start address means MCFG
 221          * firmware bug or we need another quirk in array.
 222          */
 223         pci_mcfg_apply_quirks(root, &res, &ops);
 224         if (!res.start)
 225                 return -ENXIO;
 226
 227         *cfgres = res;
 228         *ecam_ops = ops;
 229         return 0;
 230 }
 231
 232 static __init int pci_mcfg_parse(struct acpi_table_header *header)
 233 {
 234         struct acpi_table_mcfg *mcfg;
 235         struct acpi_mcfg_allocation *mptr;
 236         struct mcfg_entry *e, *arr;
 237         int i, n;
 238
 239         if (header->length < sizeof(struct acpi_table_mcfg))
 240                 return -EINVAL;
 241
 242         n = (header->length - sizeof(struct acpi_table_mcfg)) /
 243                                         sizeof(struct acpi_mcfg_allocation);
 244         mcfg = (struct acpi_table_mcfg *)header;
 245         mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
 246
 247         arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
 248         if (!arr)
 249                 return -ENOMEM;
 250
 251         for (i = 0, e = arr; i < n; i++, mptr++, e++) {
 252                 e->segment = mptr->pci_segment;
 253                 e->addr =  mptr->address;
 254                 e->bus_start = mptr->start_bus_number;
 255                 e->bus_end = mptr->end_bus_number;
 256                 list_add(&e->list, &pci_mcfg_list);
 257         }
 258
 259 #ifdef CONFIG_PCI_QUIRKS
 260         /* Save MCFG IDs and revision for quirks matching */
 261         memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
 262         memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
 263         mcfg_oem_revision = header->oem_revision;
 264 #endif
 265
 266         pr_info("MCFG table detected, %d entries\n", n);
 267         return 0;
 268 }
 269
 270 /* Interface called by ACPI - parse and save MCFG table */
 271 void __init pci_mmcfg_late_init(void)
 272 {
 273         int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
 274         if (err)
 275                 pr_err("Failed to parse MCFG (%d)\n", err);
 276 }