drivers/ata/ahci_qoriq.c

   1 /*
   2  * Freescale QorIQ AHCI SATA platform driver
   3  *
   4  * Copyright 2015 Freescale, Inc.
   5  *   Tang Yuantian <Yuantian.Tang@freescale.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2, or (at your option)
  10  * any later version.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/pm.h>
  16 #include <linux/ahci_platform.h>
  17 #include <linux/device.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/libata.h>
  23 #include "ahci.h"
  24
  25 #define DRV_NAME "ahci-qoriq"
  26
  27 /* port register definition */
  28 #define PORT_PHY1       0xA8
  29 #define PORT_PHY2       0xAC
  30 #define PORT_PHY3       0xB0
  31 #define PORT_PHY4       0xB4
  32 #define PORT_PHY5       0xB8
  33 #define PORT_AXICC      0xBC
  34 #define PORT_TRANS      0xC8
  35
  36 /* port register default value */
  37 #define AHCI_PORT_PHY_1_CFG     0xa003fffe
  38 #define AHCI_PORT_TRANS_CFG     0x08000029
  39 #define AHCI_PORT_AXICC_CFG     0x3fffffff
  40
  41 /* for ls1021a */
  42 #define LS1021A_PORT_PHY2       0x28183414
  43 #define LS1021A_PORT_PHY3       0x0e080e06
  44 #define LS1021A_PORT_PHY4       0x064a080b
  45 #define LS1021A_PORT_PHY5       0x2aa86470
  46 #define LS1021A_AXICC_ADDR      0xC0
  47
  48 #define SATA_ECC_DISABLE        0x00020000
  49 #define LS1046A_SATA_ECC_DIS    0x80000000
  50
  51 enum ahci_qoriq_type {
  52         AHCI_LS1021A,
  53         AHCI_LS1043A,
  54         AHCI_LS2080A,
  55         AHCI_LS1046A,
  56 };
  57
  58 struct ahci_qoriq_priv {
  59         struct ccsr_ahci *reg_base;
  60         enum ahci_qoriq_type type;
  61         void __iomem *ecc_addr;
  62 };
  63
  64 static const struct of_device_id ahci_qoriq_of_match[] = {
  65         { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
  66         { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
  67         { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
  68         { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
  69         {},
  70 };
  71 MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
  72
  73 static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
  74                           unsigned long deadline)
  75 {
  76         const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
  77         void __iomem *port_mmio = ahci_port_base(link->ap);
  78         u32 px_cmd, px_is, px_val;
  79         struct ata_port *ap = link->ap;
  80         struct ahci_port_priv *pp = ap->private_data;
  81         struct ahci_host_priv *hpriv = ap->host->private_data;
  82         struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
  83         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  84         struct ata_taskfile tf;
  85         bool online;
  86         int rc;
  87         bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
  88
  89         DPRINTK("ENTER\n");
  90
  91         ahci_stop_engine(ap);
  92
  93         /*
  94          * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
  95          * A-009042: The device detection initialization sequence
  96          * mistakenly resets some registers.
  97          *
  98          * Workaround for this is:
  99          * The software should read and store PxCMD and PxIS values
 100          * before issuing the device detection initialization sequence.
 101          * After the sequence is complete, software should restore the
 102          * PxCMD and PxIS with the stored values.
 103          */
 104         if (ls1021a_workaround) {
 105                 px_cmd = readl(port_mmio + PORT_CMD);
 106                 px_is = readl(port_mmio + PORT_IRQ_STAT);
 107         }
 108
 109         /* clear D2H reception area to properly wait for D2H FIS */
 110         ata_tf_init(link->device, &tf);
 111         tf.command = ATA_BUSY;
 112         ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 113
 114         rc = sata_link_hardreset(link, timing, deadline, &online,
 115                                  ahci_check_ready);
 116
 117         /* restore the PxCMD and PxIS on ls1021 */
 118         if (ls1021a_workaround) {
 119                 px_val = readl(port_mmio + PORT_CMD);
 120                 if (px_val != px_cmd)
 121                         writel(px_cmd, port_mmio + PORT_CMD);
 122
 123                 px_val = readl(port_mmio + PORT_IRQ_STAT);
 124                 if (px_val != px_is)
 125                         writel(px_is, port_mmio + PORT_IRQ_STAT);
 126         }
 127
 128         hpriv->start_engine(ap);
 129
 130         if (online)
 131                 *class = ahci_dev_classify(ap);
 132
 133         DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
 134         return rc;
 135 }
 136
 137 static struct ata_port_operations ahci_qoriq_ops = {
 138         .inherits       = &ahci_ops,
 139         .hardreset      = ahci_qoriq_hardreset,
 140 };
 141
 142 static const struct ata_port_info ahci_qoriq_port_info = {
 143         .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
 144         .pio_mask       = ATA_PIO4,
 145         .udma_mask      = ATA_UDMA6,
 146         .port_ops       = &ahci_qoriq_ops,
 147 };
 148
 149 static struct scsi_host_template ahci_qoriq_sht = {
 150         AHCI_SHT(DRV_NAME),
 151 };
 152
 153 static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
 154 {
 155         struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
 156         void __iomem *reg_base = hpriv->mmio;
 157
 158         switch (qpriv->type) {
 159         case AHCI_LS1021A:
 160                 writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
 161                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 162                 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
 163                 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
 164                 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
 165                 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
 166                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 167                 writel(AHCI_PORT_AXICC_CFG, reg_base + LS1021A_AXICC_ADDR);
 168                 break;
 169
 170         case AHCI_LS1043A:
 171                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 172                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 173                 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 174                 break;
 175
 176         case AHCI_LS2080A:
 177                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 178                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 179                 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 180                 break;
 181
 182         case AHCI_LS1046A:
 183                 writel(LS1046A_SATA_ECC_DIS, qpriv->ecc_addr);
 184                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 185                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 186                 writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 187                 break;
 188         }
 189
 190         return 0;
 191 }
 192
 193 static int ahci_qoriq_probe(struct platform_device *pdev)
 194 {
 195         struct device_node *np = pdev->dev.of_node;
 196         struct device *dev = &pdev->dev;
 197         struct ahci_host_priv *hpriv;
 198         struct ahci_qoriq_priv *qoriq_priv;
 199         const struct of_device_id *of_id;
 200         struct resource *res;
 201         int rc;
 202
 203         hpriv = ahci_platform_get_resources(pdev);
 204         if (IS_ERR(hpriv))
 205                 return PTR_ERR(hpriv);
 206
 207         of_id = of_match_node(ahci_qoriq_of_match, np);
 208         if (!of_id)
 209                 return -ENODEV;
 210
 211         qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
 212         if (!qoriq_priv)
 213                 return -ENOMEM;
 214
 215         qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
 216
 217         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 218                         "sata-ecc");
 219         if (res) {
 220                 qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
 221                 if (IS_ERR(qoriq_priv->ecc_addr))
 222                         return PTR_ERR(qoriq_priv->ecc_addr);
 223         }
 224
 225         rc = ahci_platform_enable_resources(hpriv);
 226         if (rc)
 227                 return rc;
 228
 229         hpriv->plat_data = qoriq_priv;
 230         rc = ahci_qoriq_phy_init(hpriv);
 231         if (rc)
 232                 goto disable_resources;
 233
 234         rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
 235                                      &ahci_qoriq_sht);
 236         if (rc)
 237                 goto disable_resources;
 238
 239         return 0;
 240
 241 disable_resources:
 242         ahci_platform_disable_resources(hpriv);
 243
 244         return rc;
 245 }
 246
 247 #ifdef CONFIG_PM_SLEEP
 248 static int ahci_qoriq_resume(struct device *dev)
 249 {
 250         struct ata_host *host = dev_get_drvdata(dev);
 251         struct ahci_host_priv *hpriv = host->private_data;
 252         int rc;
 253
 254         rc = ahci_platform_enable_resources(hpriv);
 255         if (rc)
 256                 return rc;
 257
 258         rc = ahci_qoriq_phy_init(hpriv);
 259         if (rc)
 260                 goto disable_resources;
 261
 262         rc = ahci_platform_resume_host(dev);
 263         if (rc)
 264                 goto disable_resources;
 265
 266         /* We resumed so update PM runtime state */
 267         pm_runtime_disable(dev);
 268         pm_runtime_set_active(dev);
 269         pm_runtime_enable(dev);
 270
 271         return 0;
 272
 273 disable_resources:
 274         ahci_platform_disable_resources(hpriv);
 275
 276         return rc;
 277 }
 278 #endif
 279
 280 static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
 281                          ahci_qoriq_resume);
 282
 283 static struct platform_driver ahci_qoriq_driver = {
 284         .probe = ahci_qoriq_probe,
 285         .remove = ata_platform_remove_one,
 286         .driver = {
 287                 .name = DRV_NAME,
 288                 .of_match_table = ahci_qoriq_of_match,
 289                 .pm = &ahci_qoriq_pm_ops,
 290         },
 291 };
 292 module_platform_driver(ahci_qoriq_driver);
 293
 294 MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
 295 MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
 296 MODULE_LICENSE("GPL");