drivers/char/tpm/tpm_tis_core.h

   1 /*
   2  * Copyright (C) 2005, 2006 IBM Corporation
   3  * Copyright (C) 2014, 2015 Intel Corporation
   4  *
   5  * Authors:
   6  * Leendert van Doorn <leendert@watson.ibm.com>
   7  * Kylene Hall <kjhall@us.ibm.com>
   8  *
   9  * Maintained by: <tpmdd-devel@lists.sourceforge.net>
  10  *
  11  * Device driver for TCG/TCPA TPM (trusted platform module).
  12  * Specifications at www.trustedcomputinggroup.org
  13  *
  14  * This device driver implements the TPM interface as defined in
  15  * the TCG TPM Interface Spec version 1.2, revision 1.0.
  16  *
  17  * This program is free software; you can redistribute it and/or
  18  * modify it under the terms of the GNU General Public License as
  19  * published by the Free Software Foundation, version 2 of the
  20  * License.
  21  */
  22
  23 #ifndef __TPM_TIS_CORE_H__
  24 #define __TPM_TIS_CORE_H__
  25
  26 #include "tpm.h"
  27
  28 enum tis_access {
  29         TPM_ACCESS_VALID = 0x80,
  30         TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
  31         TPM_ACCESS_REQUEST_PENDING = 0x04,
  32         TPM_ACCESS_REQUEST_USE = 0x02,
  33 };
  34
  35 enum tis_status {
  36         TPM_STS_VALID = 0x80,
  37         TPM_STS_COMMAND_READY = 0x40,
  38         TPM_STS_GO = 0x20,
  39         TPM_STS_DATA_AVAIL = 0x10,
  40         TPM_STS_DATA_EXPECT = 0x08,
  41 };
  42
  43 enum tis_int_flags {
  44         TPM_GLOBAL_INT_ENABLE = 0x80000000,
  45         TPM_INTF_BURST_COUNT_STATIC = 0x100,
  46         TPM_INTF_CMD_READY_INT = 0x080,
  47         TPM_INTF_INT_EDGE_FALLING = 0x040,
  48         TPM_INTF_INT_EDGE_RISING = 0x020,
  49         TPM_INTF_INT_LEVEL_LOW = 0x010,
  50         TPM_INTF_INT_LEVEL_HIGH = 0x008,
  51         TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
  52         TPM_INTF_STS_VALID_INT = 0x002,
  53         TPM_INTF_DATA_AVAIL_INT = 0x001,
  54 };
  55
  56 enum tis_defaults {
  57         TIS_MEM_LEN = 0x5000,
  58         TIS_SHORT_TIMEOUT = 750,        /* ms */
  59         TIS_LONG_TIMEOUT = 2000,        /* 2 sec */
  60 };
  61
  62 /* Some timeout values are needed before it is known whether the chip is
  63  * TPM 1.0 or TPM 2.0.
  64  */
  65 #define TIS_TIMEOUT_A_MAX       max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A)
  66 #define TIS_TIMEOUT_B_MAX       max(TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B)
  67 #define TIS_TIMEOUT_C_MAX       max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C)
  68 #define TIS_TIMEOUT_D_MAX       max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D)
  69
  70 #define TPM_ACCESS(l)                   (0x0000 | ((l) << 12))
  71 #define TPM_INT_ENABLE(l)               (0x0008 | ((l) << 12))
  72 #define TPM_INT_VECTOR(l)               (0x000C | ((l) << 12))
  73 #define TPM_INT_STATUS(l)               (0x0010 | ((l) << 12))
  74 #define TPM_INTF_CAPS(l)                (0x0014 | ((l) << 12))
  75 #define TPM_STS(l)                      (0x0018 | ((l) << 12))
  76 #define TPM_STS3(l)                     (0x001b | ((l) << 12))
  77 #define TPM_DATA_FIFO(l)                (0x0024 | ((l) << 12))
  78
  79 #define TPM_DID_VID(l)                  (0x0F00 | ((l) << 12))
  80 #define TPM_RID(l)                      (0x0F04 | ((l) << 12))
  81
  82 enum tpm_tis_flags {
  83         TPM_TIS_ITPM_POSSIBLE           = BIT(0),
  84 };
  85
  86 struct tpm_tis_data {
  87         u16 manufacturer_id;
  88         int locality;
  89         int irq;
  90         bool irq_tested;
  91         unsigned int flags;
  92         wait_queue_head_t int_queue;
  93         wait_queue_head_t read_queue;
  94         const struct tpm_tis_phy_ops *phy_ops;
  95 };
  96
  97 struct tpm_tis_phy_ops {
  98         int (*read_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
  99                           u8 *result);
 100         int (*write_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
 101                            u8 *value);
 102         int (*read16)(struct tpm_tis_data *data, u32 addr, u16 *result);
 103         int (*read32)(struct tpm_tis_data *data, u32 addr, u32 *result);
 104         int (*write32)(struct tpm_tis_data *data, u32 addr, u32 src);
 105 };
 106
 107 static inline int tpm_tis_read_bytes(struct tpm_tis_data *data, u32 addr,
 108                                      u16 len, u8 *result)
 109 {
 110         return data->phy_ops->read_bytes(data, addr, len, result);
 111 }
 112
 113 static inline int tpm_tis_read8(struct tpm_tis_data *data, u32 addr, u8 *result)
 114 {
 115         return data->phy_ops->read_bytes(data, addr, 1, result);
 116 }
 117
 118 static inline int tpm_tis_read16(struct tpm_tis_data *data, u32 addr,
 119                                  u16 *result)
 120 {
 121         return data->phy_ops->read16(data, addr, result);
 122 }
 123
 124 static inline int tpm_tis_read32(struct tpm_tis_data *data, u32 addr,
 125                                  u32 *result)
 126 {
 127         return data->phy_ops->read32(data, addr, result);
 128 }
 129
 130 static inline int tpm_tis_write_bytes(struct tpm_tis_data *data, u32 addr,
 131                                       u16 len, u8 *value)
 132 {
 133         return data->phy_ops->write_bytes(data, addr, len, value);
 134 }
 135
 136 static inline int tpm_tis_write8(struct tpm_tis_data *data, u32 addr, u8 value)
 137 {
 138         return data->phy_ops->write_bytes(data, addr, 1, &value);
 139 }
 140
 141 static inline int tpm_tis_write32(struct tpm_tis_data *data, u32 addr,
 142                                   u32 value)
 143 {
 144         return data->phy_ops->write32(data, addr, value);
 145 }
 146
 147 void tpm_tis_remove(struct tpm_chip *chip);
 148 int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
 149                       const struct tpm_tis_phy_ops *phy_ops,
 150                       acpi_handle acpi_dev_handle);
 151
 152 #ifdef CONFIG_PM_SLEEP
 153 int tpm_tis_resume(struct device *dev);
 154 #endif
 155
 156 #endif