drivers/clk/hisilicon/clk-hip04.c

   1 /*
   2  * Hisilicon HiP04 clock driver
   3  *
   4  * Copyright (c) 2013-2014 Hisilicon Limited.
   5  * Copyright (c) 2013-2014 Linaro Limited.
   6  *
   7  * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, write to the Free Software Foundation, Inc.,
  21  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  22  *
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/clk-provider.h>
  27 #include <linux/io.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_device.h>
  31 #include <linux/slab.h>
  32
  33 #include <dt-bindings/clock/hip04-clock.h>
  34
  35 #include "clk.h"
  36
  37 /* fixed rate clocks */
  38 static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = {
  39         { HIP04_OSC50M,   "osc50m",   NULL, 0, 50000000, },
  40         { HIP04_CLK_50M,  "clk50m",   NULL, 0, 50000000, },
  41         { HIP04_CLK_168M, "clk168m",  NULL, 0, 168750000, },
  42 };
  43
  44 static void __init hip04_clk_init(struct device_node *np)
  45 {
  46         struct hisi_clock_data *clk_data;
  47
  48         clk_data = hisi_clk_init(np, HIP04_NR_CLKS);
  49         if (!clk_data)
  50                 return;
  51
  52         hisi_clk_register_fixed_rate(hip04_fixed_rate_clks,
  53                                      ARRAY_SIZE(hip04_fixed_rate_clks),
  54                                      clk_data);
  55 }
  56 CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init);