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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / clk / imx / clk-imx35.c
blob203cad6c9aab0385ffff2afad7d6c459a57757db
1 /*
2 * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9 #include <linux/mm.h>
10 #include <linux/delay.h>
11 #include <linux/clk.h>
12 #include <linux/io.h>
13 #include <linux/clkdev.h>
14 #include <linux/of.h>
15 #include <linux/err.h>
16 #include <soc/imx/revision.h>
17 #include <soc/imx/timer.h>
18 #include <asm/irq.h>
19
20 #include "clk.h"
21
22 #define MX35_CCM_BASE_ADDR 0x53f80000
23 #define MX35_GPT1_BASE_ADDR 0x53f90000
24 #define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
25
26 #define MXC_CCM_PDR0 0x04
27 #define MX35_CCM_PDR2 0x0c
28 #define MX35_CCM_PDR3 0x10
29 #define MX35_CCM_PDR4 0x14
30 #define MX35_CCM_MPCTL 0x1c
31 #define MX35_CCM_PPCTL 0x20
32 #define MX35_CCM_CGR0 0x2c
33 #define MX35_CCM_CGR1 0x30
34 #define MX35_CCM_CGR2 0x34
35 #define MX35_CCM_CGR3 0x38
36
37 struct arm_ahb_div {
38 unsigned char arm, ahb, sel;
39 };
40
41 static struct arm_ahb_div clk_consumer[] = {
42 { .arm = 1, .ahb = 4, .sel = 0},
43 { .arm = 1, .ahb = 3, .sel = 1},
44 { .arm = 2, .ahb = 2, .sel = 0},
45 { .arm = 0, .ahb = 0, .sel = 0},
46 { .arm = 0, .ahb = 0, .sel = 0},
47 { .arm = 0, .ahb = 0, .sel = 0},
48 { .arm = 4, .ahb = 1, .sel = 0},
49 { .arm = 1, .ahb = 5, .sel = 0},
50 { .arm = 1, .ahb = 8, .sel = 0},
51 { .arm = 1, .ahb = 6, .sel = 1},
52 { .arm = 2, .ahb = 4, .sel = 0},
53 { .arm = 0, .ahb = 0, .sel = 0},
54 { .arm = 0, .ahb = 0, .sel = 0},
55 { .arm = 0, .ahb = 0, .sel = 0},
56 { .arm = 4, .ahb = 2, .sel = 0},
57 { .arm = 0, .ahb = 0, .sel = 0},
58 };
59
60 static char hsp_div_532[] = { 4, 8, 3, 0 };
61 static char hsp_div_400[] = { 3, 6, 3, 0 };
62
63 static struct clk_onecell_data clk_data;
64
65 static const char *std_sel[] = {"ppll", "arm"};
66 static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
67
68 enum mx35_clks {
69 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb,
70 /* 9 */ ipg, arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div,
71 /* 15 */ esdhc_sel, esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel,
72 /* 20 */ spdif_div_pre, spdif_div_post, ssi_sel, ssi1_div_pre,
73 /* 24 */ ssi1_div_post, ssi2_div_pre, ssi2_div_post, usb_sel, usb_div,
74 /* 29 */ nfc_div, asrc_gate, pata_gate, audmux_gate, can1_gate,
75 /* 34 */ can2_gate, cspi1_gate, cspi2_gate, ect_gate, edio_gate,
76 /* 39 */ emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate,
77 /* 44 */ esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate,
78 /* 49 */ gpio3_gate, gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate,
79 /* 54 */ iomuxc_gate, ipu_gate, kpp_gate, mlb_gate, mshc_gate,
80 /* 59 */ owire_gate, pwm_gate, rngc_gate, rtc_gate, rtic_gate, scc_gate,
81 /* 65 */ sdma_gate, spba_gate, spdif_gate, ssi1_gate, ssi2_gate,
82 /* 70 */ uart1_gate, uart2_gate, uart3_gate, usbotg_gate, wdog_gate,
83 /* 75 */ max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
84 /* 81 */ gpu2d_gate, ckil, clk_max
85 };
86
87 static struct clk *clk[clk_max];
88
89 static struct clk ** const uart_clks[] __initconst = {
90 &clk[ipg],
91 &clk[uart1_gate],
92 &clk[uart2_gate],
93 &clk[uart3_gate],
94 NULL
95 };
96
97 static void __init _mx35_clocks_init(void)
98 {
99 void __iomem *base;
100 u32 pdr0, consumer_sel, hsp_sel;
101 struct arm_ahb_div *aad;
102 unsigned char *hsp_div;
103
104 base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K);
105 BUG_ON(!base);
106
107 pdr0 = __raw_readl(base + MXC_CCM_PDR0);
108 consumer_sel = (pdr0 >> 16) & 0xf;
109 aad = &clk_consumer[consumer_sel];
110 if (!aad->arm) {
111 pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel);
112 /*
113 * We are basically stuck. Continue with a default entry and hope we
114 * get far enough to actually show the above message
115 */
116 aad = &clk_consumer[0];
117 }
118
119 clk[ckih] = imx_clk_fixed("ckih", 24000000);
120 clk[ckil] = imx_clk_fixed("ckil", 32768);
121 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL);
122 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL);
123
124 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4);
125
126 if (aad->sel)
127 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm);
128 else
129 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm);
130
131 if (clk_get_rate(clk[arm]) > 400000000)
132 hsp_div = hsp_div_532;
133 else
134 hsp_div = hsp_div_400;
135
136 hsp_sel = (pdr0 >> 20) & 0x3;
137 if (!hsp_div[hsp_sel]) {
138 pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel);
139 hsp_sel = 0;
140 }
141
142 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]);
143
144 clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb);
145 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
146
147 clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6);
148 clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3);
149 clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel));
150
151 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel));
152 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6);
153
154 clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
155 clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6);
156 clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6);
157 clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6);
158
159 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel));
160 clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */
161 clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6);
162
163 clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel));
164 clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3);
165 clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6);
166 clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3);
167 clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6);
168
169 clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
170 clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6);
171
172 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
173
174 clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel));
175 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6);
176
177 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0);
178 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2);
179 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4);
180 clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6);
181 clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8);
182 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10);
183 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12);
184 clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14);
185 clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16);
186 clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18);
187 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20);
188 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22);
189 clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24);
190 clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26);
191 clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28);
192 clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30);
193
194 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0);
195 clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2);
196 clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4);
197 clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6);
198 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8);
199 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10);
200 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12);
201 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14);
202 clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16);
203 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18);
204 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20);
205 clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22);
206 clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24);
207 clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26);
208 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28);
209 clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30);
210
211 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0);
212 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2);
213 clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4);
214 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6);
215 clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8);
216 clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10);
217 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12);
218 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14);
219 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16);
220 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18);
221 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20);
222 clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22);
223 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24);
224 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
225 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
226
227 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0);
228 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2);
229 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4);
230
231 imx_check_clocks(clk, ARRAY_SIZE(clk));
232
233 clk_prepare_enable(clk[spba_gate]);
234 clk_prepare_enable(clk[gpio1_gate]);
235 clk_prepare_enable(clk[gpio2_gate]);
236 clk_prepare_enable(clk[gpio3_gate]);
237 clk_prepare_enable(clk[iim_gate]);
238 clk_prepare_enable(clk[emi_gate]);
239 clk_prepare_enable(clk[max_gate]);
240 clk_prepare_enable(clk[iomuxc_gate]);
241
242 /*
243 * SCC is needed to boot via mmc after a watchdog reset. The clock code
244 * before conversion to common clk also enabled UART1 (which isn't
245 * handled here and not needed for mmc) and IIM (which is enabled
246 * unconditionally above).
247 */
248 clk_prepare_enable(clk[scc_gate]);
249
250 imx_register_uart_clocks(uart_clks);
251
252 imx_print_silicon_rev("i.MX35", mx35_revision());
253 }
254
255 int __init mx35_clocks_init(void)
256 {
257 _mx35_clocks_init();
258
259 clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
260 clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
261 clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
262 clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0");
263 clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0");
264 clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1");
265 clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1");
266 clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0");
267 clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1");
268 clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0");
269 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0");
270 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0");
271 clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1");
272 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1");
273 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1");
274 clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2");
275 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2");
276 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2");
277 /* i.mx35 has the i.mx27 type fec */
278 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
279 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
280 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
281 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0");
282 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1");
283 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2");
284 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
285 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
286 clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
287 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
288 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
289 clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
290 clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
291 /* i.mx35 has the i.mx21 type uart */
292 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
293 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
294 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1");
295 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
296 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
297 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
298 /* i.mx35 has the i.mx21 type rtc */
299 clk_register_clkdev(clk[ckil], "ref", "imx21-rtc");
300 clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc");
301 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
302 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
303 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0");
304 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
305 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
306 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1");
307 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
308 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
309 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2");
310 clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
311 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
312 clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27");
313 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
314 clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0");
315 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
316 clk_register_clkdev(clk[admux_gate], "audmux", NULL);
317
318 mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT, GPT_TYPE_IMX31);
319
320 return 0;
321 }
322
323 static void __init mx35_clocks_init_dt(struct device_node *ccm_node)
324 {
325 _mx35_clocks_init();
326
327 clk_data.clks = clk;
328 clk_data.clk_num = ARRAY_SIZE(clk);
329 of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
330 }
331 CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);
Linux with added FPC-III support