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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / clk / imx / clk-imx51-imx53.c
blob1e3c9ea5f9dcf9e909e4412eaf5a2185659d9c84
1 /*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9 #include <linux/mm.h>
10 #include <linux/delay.h>
11 #include <linux/clk.h>
12 #include <linux/io.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
15 #include <linux/err.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <soc/imx/revision.h>
20 #include <dt-bindings/clock/imx5-clock.h>
21
22 #include "clk.h"
23
24 #define MX51_DPLL1_BASE 0x83f80000
25 #define MX51_DPLL2_BASE 0x83f84000
26 #define MX51_DPLL3_BASE 0x83f88000
27
28 #define MX53_DPLL1_BASE 0x63f80000
29 #define MX53_DPLL2_BASE 0x63f84000
30 #define MX53_DPLL3_BASE 0x63f88000
31 #define MX53_DPLL4_BASE 0x63f8c000
32
33 #define MXC_CCM_CCR (ccm_base + 0x00)
34 #define MXC_CCM_CCDR (ccm_base + 0x04)
35 #define MXC_CCM_CSR (ccm_base + 0x08)
36 #define MXC_CCM_CCSR (ccm_base + 0x0c)
37 #define MXC_CCM_CACRR (ccm_base + 0x10)
38 #define MXC_CCM_CBCDR (ccm_base + 0x14)
39 #define MXC_CCM_CBCMR (ccm_base + 0x18)
40 #define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
41 #define MXC_CCM_CSCMR2 (ccm_base + 0x20)
42 #define MXC_CCM_CSCDR1 (ccm_base + 0x24)
43 #define MXC_CCM_CS1CDR (ccm_base + 0x28)
44 #define MXC_CCM_CS2CDR (ccm_base + 0x2c)
45 #define MXC_CCM_CDCDR (ccm_base + 0x30)
46 #define MXC_CCM_CHSCDR (ccm_base + 0x34)
47 #define MXC_CCM_CSCDR2 (ccm_base + 0x38)
48 #define MXC_CCM_CSCDR3 (ccm_base + 0x3c)
49 #define MXC_CCM_CSCDR4 (ccm_base + 0x40)
50 #define MXC_CCM_CWDR (ccm_base + 0x44)
51 #define MXC_CCM_CDHIPR (ccm_base + 0x48)
52 #define MXC_CCM_CDCR (ccm_base + 0x4c)
53 #define MXC_CCM_CTOR (ccm_base + 0x50)
54 #define MXC_CCM_CLPCR (ccm_base + 0x54)
55 #define MXC_CCM_CISR (ccm_base + 0x58)
56 #define MXC_CCM_CIMR (ccm_base + 0x5c)
57 #define MXC_CCM_CCOSR (ccm_base + 0x60)
58 #define MXC_CCM_CGPR (ccm_base + 0x64)
59 #define MXC_CCM_CCGR0 (ccm_base + 0x68)
60 #define MXC_CCM_CCGR1 (ccm_base + 0x6c)
61 #define MXC_CCM_CCGR2 (ccm_base + 0x70)
62 #define MXC_CCM_CCGR3 (ccm_base + 0x74)
63 #define MXC_CCM_CCGR4 (ccm_base + 0x78)
64 #define MXC_CCM_CCGR5 (ccm_base + 0x7c)
65 #define MXC_CCM_CCGR6 (ccm_base + 0x80)
66 #define MXC_CCM_CCGR7 (ccm_base + 0x84)
67
68 /* Low-power Audio Playback Mode clock */
69 static const char *lp_apm_sel[] = { "osc", };
70
71 /* This is used multiple times */
72 static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
73 static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
74 static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
75 static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
76 static const char *per_root_sel[] = { "per_podf", "ipg", };
77 static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
78 static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
79 static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
80 static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
81 static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
82 static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
83 static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
84 static const char *emi_slow_sel[] = { "main_bus", "ahb", };
85 static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
86 static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
87 static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
88 static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
89 static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
90 static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
91 static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
92 static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
93 static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
94 static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", };
95 static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
96 static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
97 static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
98 static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
99 static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
100 static const char *mx53_cko1_sel[] = {
101 "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw",
102 "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy",
103 "di_pred", "dummy", "dummy", "ahb",
104 "ipg", "per_root", "ckil", "dummy",};
105 static const char *mx53_cko2_sel[] = {
106 "dummy"/* dptc_core */, "dummy"/* dptc_perich */,
107 "dummy", "esdhc_a_podf",
108 "usboh3_podf", "dummy"/* wrck_clk_root */,
109 "ecspi_podf", "dummy"/* pll1_ref_clk */,
110 "esdhc_b_podf", "dummy"/* ddr_clk_root */,
111 "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */,
112 "vpu_sel", "ipu_sel",
113 "osc", "ckih1",
114 "dummy", "esdhc_c_sel",
115 "ssi1_root_podf", "ssi2_root_podf",
116 "dummy", "dummy",
117 "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */,
118 "dummy"/* tve_out */, "usb_phy_sel",
119 "tve_sel", "lp_apm",
120 "uart_root", "dummy"/* spdif0_clk_root */,
121 "dummy", "dummy", };
122 static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
123 static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
124 static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
125 static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
126 static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
127 static const char *step_sels[] = { "lp_apm", };
128 static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
129 static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_clk */, "dummy" /* fec_phy_clk */ };
130
131 static struct clk *clk[IMX5_CLK_END];
132 static struct clk_onecell_data clk_data;
133
134 static struct clk ** const uart_clks[] __initconst = {
135 &clk[IMX5_CLK_UART1_IPG_GATE],
136 &clk[IMX5_CLK_UART1_PER_GATE],
137 &clk[IMX5_CLK_UART2_IPG_GATE],
138 &clk[IMX5_CLK_UART2_PER_GATE],
139 &clk[IMX5_CLK_UART3_IPG_GATE],
140 &clk[IMX5_CLK_UART3_PER_GATE],
141 &clk[IMX5_CLK_UART4_IPG_GATE],
142 &clk[IMX5_CLK_UART4_PER_GATE],
143 &clk[IMX5_CLK_UART5_IPG_GATE],
144 &clk[IMX5_CLK_UART5_PER_GATE],
145 NULL
146 };
147
148 static void __init mx5_clocks_common_init(void __iomem *ccm_base)
149 {
150 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
151 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
152 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
153 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0);
154 clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0);
155
156 clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
157 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
158 clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
159 main_bus_sel, ARRAY_SIZE(main_bus_sel));
160 clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
161 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
162 clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
163 clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
164 clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
165 clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
166 per_root_sel, ARRAY_SIZE(per_root_sel));
167 clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
168 clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
169 clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
170 clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
171 clk[IMX5_CLK_TMAX1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
172 clk[IMX5_CLK_TMAX2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
173 clk[IMX5_CLK_TMAX3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
174 clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
175 clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
176 clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
177 clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
178 clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
179 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
180 clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
181 clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
182
183 clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
184 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
185 clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
186 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
187 clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
188 clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
189 clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
190 clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
191 clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
192 clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
193
194 clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
195 emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
196 clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
197 clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
198 clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
199 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
200 clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
201 clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
202 clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
203 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
204 clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
205 clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
206 clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
207 clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
208 clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
209 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
210 clk[IMX5_CLK_STEP_SEL] = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels));
211 clk[IMX5_CLK_CPU_PODF_SEL] = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels));
212 clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3);
213 clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
214 clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
215 clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
216 clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
217 clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
218 clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
219 clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
220 clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
221 clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
222 clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
223 clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
224 clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
225 clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
226 clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
227 clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
228 clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
229 clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
230 clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
231 clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
232 clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
233 clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
234 clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
235 clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
236 clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
237 clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
238 clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
239 clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
240 clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
241 clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
242 clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
243 clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
244 clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
245 clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
246 clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
247 clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
248 clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
249 clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
250 clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
251 clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
252 clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
253 clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
254 clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
255 clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
256 clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
257 clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
258 clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
259 clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
260 clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
261 clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
262 clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
263 clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
264 clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
265
266 clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
267 clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
268 clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
269 clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
270 clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
271 clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
272 clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
273 clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
274 clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
275 clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
276 clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
277 clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
278 clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
279 clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
280 clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
281 clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
282 clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
283 clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
284 clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
285 clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
286 clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
287 clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
288 clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
289 clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
290 clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
291 clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
292 clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
293 clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
294 clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
295 clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
296 clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
297 clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
298 spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
299 clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
300 clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
301 clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
302 clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
303
304 clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
305 clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
306
307 /* Set SDHC parents to be PLL2 */
308 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
309 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
310
311 /* move usb phy clk to 24MHz */
312 clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
313
314 clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]);
315 clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */
316 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]);
317 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */
318 clk_prepare_enable(clk[IMX5_CLK_SPBA]);
319 clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */
320 clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */
321 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]);
322 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]);
323 clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]);
324 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]);
325 clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
326 clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
327 clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
328
329 imx_register_uart_clocks(uart_clks);
330 }
331
332 static void __init mx50_clocks_init(struct device_node *np)
333 {
334 void __iomem *ccm_base;
335 void __iomem *pll_base;
336 unsigned long r;
337
338 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
339 WARN_ON(!pll_base);
340 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
341
342 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
343 WARN_ON(!pll_base);
344 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
345
346 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
347 WARN_ON(!pll_base);
348 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
349
350 ccm_base = of_iomap(np, 0);
351 WARN_ON(!ccm_base);
352
353 mx5_clocks_common_init(ccm_base);
354
355 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
356 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
357 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
358 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
359 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
360 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
361 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
362 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
363 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
364
365 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
366 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
367 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
368 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
369
370 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
371 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
372 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
373 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
374
375 imx_check_clocks(clk, ARRAY_SIZE(clk));
376
377 clk_data.clks = clk;
378 clk_data.clk_num = ARRAY_SIZE(clk);
379 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
380
381 /* set SDHC root clock to 200MHZ*/
382 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
383 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
384
385 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
386 imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
387 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
388
389 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
390 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
391 }
392 CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
393
394 static void __init mx51_clocks_init(struct device_node *np)
395 {
396 void __iomem *ccm_base;
397 void __iomem *pll_base;
398 u32 val;
399
400 pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
401 WARN_ON(!pll_base);
402 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
403
404 pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
405 WARN_ON(!pll_base);
406 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
407
408 pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
409 WARN_ON(!pll_base);
410 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
411
412 ccm_base = of_iomap(np, 0);
413 WARN_ON(!ccm_base);
414
415 mx5_clocks_common_init(ccm_base);
416
417 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
418 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
419 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
420 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
421 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
422 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
423 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
424 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
425 clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
426 mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
427 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
428 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
429 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
430 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
431 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
432 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
433 clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
434 clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
435 clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
436 clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
437 clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
438 clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
439 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
440 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
441 clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
442 spdif_sel, ARRAY_SIZE(spdif_sel));
443 clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
444 clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
445 clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
446 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
447 clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
448
449 imx_check_clocks(clk, ARRAY_SIZE(clk));
450
451 clk_data.clks = clk;
452 clk_data.clk_num = ARRAY_SIZE(clk);
453 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
454
455 /* set the usboh3 parent to pll2_sw */
456 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
457
458 /* set SDHC root clock to 166.25MHZ*/
459 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
460 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
461
462 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
463 imx_print_silicon_rev("i.MX51", mx51_revision());
464 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
465
466 /*
467 * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
468 * longer supported. Set to one for better power saving.
469 *
470 * The effect of not setting these bits is that MIPI clocks can't be
471 * enabled without the IPU clock being enabled aswell.
472 */
473 val = readl(MXC_CCM_CCDR);
474 val |= 1 << 18;
475 writel(val, MXC_CCM_CCDR);
476
477 val = readl(MXC_CCM_CLPCR);
478 val |= 1 << 23;
479 writel(val, MXC_CCM_CLPCR);
480 }
481 CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
482
483 static void __init mx53_clocks_init(struct device_node *np)
484 {
485 void __iomem *ccm_base;
486 void __iomem *pll_base;
487 unsigned long r;
488
489 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
490 WARN_ON(!pll_base);
491 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
492
493 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
494 WARN_ON(!pll_base);
495 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
496
497 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
498 WARN_ON(!pll_base);
499 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
500
501 pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
502 WARN_ON(!pll_base);
503 clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base);
504
505 ccm_base = of_iomap(np, 0);
506 WARN_ON(!ccm_base);
507
508 mx5_clocks_common_init(ccm_base);
509
510 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
511 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
512 clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
513 clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
514 clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
515 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
516 clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
517 clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
518 clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
519 clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
520 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
521 clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
522 clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
523 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
524 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT);
525 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
526 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT);
527 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
528 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
529 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
530 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
531 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
532 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
533 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
534 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
535 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
536 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
537 clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
538 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
539 clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
540 clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
541 clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
542 clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
543 clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
544 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
545 clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
546
547 clk[IMX5_CLK_FIRI_SEL] = imx_clk_mux("firi_sel", MXC_CCM_CSCMR2, 12, 2,
548 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
549 clk[IMX5_CLK_FIRI_PRED] = imx_clk_divider("firi_pred", "firi_sel", MXC_CCM_CSCDR3, 6, 3);
550 clk[IMX5_CLK_FIRI_PODF] = imx_clk_divider("firi_podf", "firi_pred", MXC_CCM_CSCDR3, 0, 6);
551 clk[IMX5_CLK_FIRI_SERIAL_GATE] = imx_clk_gate2("firi_serial_gate", "firi_podf", MXC_CCM_CCGR1, 28);
552 clk[IMX5_CLK_FIRI_IPG_GATE] = imx_clk_gate2("firi_ipg_gate", "ipg", MXC_CCM_CCGR1, 26);
553
554 clk[IMX5_CLK_CSI0_MCLK1_SEL] = imx_clk_mux("csi0_mclk1_sel", MXC_CCM_CSCMR2, 22, 2,
555 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
556 clk[IMX5_CLK_CSI0_MCLK1_PRED] = imx_clk_divider("csi0_mclk1_pred", "csi0_mclk1_sel", MXC_CCM_CSCDR4, 6, 3);
557 clk[IMX5_CLK_CSI0_MCLK1_PODF] = imx_clk_divider("csi0_mclk1_podf", "csi0_mclk1_pred", MXC_CCM_CSCDR4, 0, 6);
558 clk[IMX5_CLK_CSI0_MCLK1_GATE] = imx_clk_gate2("csi0_mclk1_serial_gate", "csi0_mclk1_podf", MXC_CCM_CCGR6, 4);
559
560 clk[IMX5_CLK_IEEE1588_SEL] = imx_clk_mux("ieee1588_sel", MXC_CCM_CSCMR2, 14, 2,
561 ieee1588_sels, ARRAY_SIZE(ieee1588_sels));
562 clk[IMX5_CLK_IEEE1588_PRED] = imx_clk_divider("ieee1588_pred", "ieee1588_sel", MXC_CCM_CSCDR2, 6, 3);
563 clk[IMX5_CLK_IEEE1588_PODF] = imx_clk_divider("ieee1588_podf", "ieee1588_pred", MXC_CCM_CSCDR2, 0, 6);
564 clk[IMX5_CLK_IEEE1588_GATE] = imx_clk_gate2("ieee1588_serial_gate", "ieee1588_podf", MXC_CCM_CCGR7, 6);
565
566 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
567 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
568 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
569 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
570
571 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
572 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
573 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
574 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
575 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
576 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
577 clk[IMX5_CLK_ARM] = imx_clk_cpu("arm", "cpu_podf",
578 clk[IMX5_CLK_CPU_PODF],
579 clk[IMX5_CLK_CPU_PODF_SEL],
580 clk[IMX5_CLK_PLL1_SW],
581 clk[IMX5_CLK_STEP_SEL]);
582
583 imx_check_clocks(clk, ARRAY_SIZE(clk));
584
585 clk_data.clks = clk;
586 clk_data.clk_num = ARRAY_SIZE(clk);
587 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
588
589 /* set SDHC root clock to 200MHZ*/
590 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
591 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
592
593 /* move can bus clk to 24MHz */
594 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
595
596 /* make sure step clock is running from 24MHz */
597 clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]);
598
599 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
600 imx_print_silicon_rev("i.MX53", mx53_revision());
601 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
602
603 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
604 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
605 }
606 CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
Linux with added FPC-III support