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sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / clk / mediatek / clk-mt8173.c
blob0ac3aee87726eb4ab9dbb083ce55e22a8e408266
1 /*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: James Liao <jamesjj.liao@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18
19 #include "clk-mtk.h"
20 #include "clk-gate.h"
21
22 #include <dt-bindings/clock/mt8173-clk.h>
23
24 /*
25 * For some clocks, we don't care what their actual rates are. And these
26 * clocks may change their rate on different products or different scenarios.
27 * So we model these clocks' rate as 0, to denote it's not an actual rate.
28 */
29 #define DUMMY_RATE 0
30
31 static DEFINE_SPINLOCK(mt8173_clk_lock);
32
33 static const struct mtk_fixed_clk fixed_clks[] __initconst = {
34 FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE),
35 FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
36 FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE),
37 FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", DUMMY_RATE),
38 FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", DUMMY_RATE),
39 FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE),
40 };
41
42 static const struct mtk_fixed_factor top_divs[] __initconst = {
43 FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2),
44 FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3),
45
46 FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2),
47 FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3),
48 FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5),
49 FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7),
50
51 FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
52 FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
53
54 FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2),
55 FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3),
56 FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5),
57 FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7),
58 FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26),
59
60 FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
61 FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
62 FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),
63
64 FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),
65 FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),
66
67 FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1),
68 FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1),
69
70 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
71 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
72
73 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1),
74 FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),
75 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),
76 FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),
77 FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16),
78
79 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
80 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
81 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
82
83 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
84 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
85
86 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
87 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
88 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
89 FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1),
90 FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
91 FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
92
93 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1),
94 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2),
95 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4),
96 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8),
97 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16),
98 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1),
99 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2),
100 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4),
101 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1),
102 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
103 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4),
104 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1),
105 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
106 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4),
107
108 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
109 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
110 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4),
111 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
112 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
113
114 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1),
115 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
116 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
117 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
118 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1),
119 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2),
120 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
121 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8),
122 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1),
123 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2),
124 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4),
125 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8),
126 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1),
127 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1),
128 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2),
129
130 FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
131 FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
132
133 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),
134 FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2),
135 FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4),
136 };
137
138 static const char * const axi_parents[] __initconst = {
139 "clk26m",
140 "syspll1_d2",
141 "syspll_d5",
142 "syspll1_d4",
143 "univpll_d5",
144 "univpll2_d2",
145 "dmpll_d2",
146 "dmpll_d4"
147 };
148
149 static const char * const mem_parents[] __initconst = {
150 "clk26m",
151 "dmpll_ck"
152 };
153
154 static const char * const ddrphycfg_parents[] __initconst = {
155 "clk26m",
156 "syspll1_d8"
157 };
158
159 static const char * const mm_parents[] __initconst = {
160 "clk26m",
161 "vencpll_d2",
162 "main_h364m",
163 "syspll1_d2",
164 "syspll_d5",
165 "syspll1_d4",
166 "univpll1_d2",
167 "univpll2_d2",
168 "dmpll_d2"
169 };
170
171 static const char * const pwm_parents[] __initconst = {
172 "clk26m",
173 "univpll2_d4",
174 "univpll3_d2",
175 "univpll1_d4"
176 };
177
178 static const char * const vdec_parents[] __initconst = {
179 "clk26m",
180 "vcodecpll_ck",
181 "tvdpll_445p5m",
182 "univpll_d3",
183 "vencpll_d2",
184 "syspll_d3",
185 "univpll1_d2",
186 "mmpll_d2",
187 "dmpll_d2",
188 "dmpll_d4"
189 };
190
191 static const char * const venc_parents[] __initconst = {
192 "clk26m",
193 "vcodecpll_ck",
194 "tvdpll_445p5m",
195 "univpll_d3",
196 "vencpll_d2",
197 "syspll_d3",
198 "univpll1_d2",
199 "univpll2_d2",
200 "dmpll_d2",
201 "dmpll_d4"
202 };
203
204 static const char * const mfg_parents[] __initconst = {
205 "clk26m",
206 "mmpll_ck",
207 "dmpll_ck",
208 "clk26m",
209 "clk26m",
210 "clk26m",
211 "clk26m",
212 "clk26m",
213 "clk26m",
214 "syspll_d3",
215 "syspll1_d2",
216 "syspll_d5",
217 "univpll_d3",
218 "univpll1_d2",
219 "univpll_d5",
220 "univpll2_d2"
221 };
222
223 static const char * const camtg_parents[] __initconst = {
224 "clk26m",
225 "univpll_d26",
226 "univpll2_d2",
227 "syspll3_d2",
228 "syspll3_d4",
229 "univpll1_d4"
230 };
231
232 static const char * const uart_parents[] __initconst = {
233 "clk26m",
234 "univpll2_d8"
235 };
236
237 static const char * const spi_parents[] __initconst = {
238 "clk26m",
239 "syspll3_d2",
240 "syspll1_d4",
241 "syspll4_d2",
242 "univpll3_d2",
243 "univpll2_d4",
244 "univpll1_d8"
245 };
246
247 static const char * const usb20_parents[] __initconst = {
248 "clk26m",
249 "univpll1_d8",
250 "univpll3_d4"
251 };
252
253 static const char * const usb30_parents[] __initconst = {
254 "clk26m",
255 "univpll3_d2",
256 "usb_syspll_125m",
257 "univpll2_d4"
258 };
259
260 static const char * const msdc50_0_h_parents[] __initconst = {
261 "clk26m",
262 "syspll1_d2",
263 "syspll2_d2",
264 "syspll4_d2",
265 "univpll_d5",
266 "univpll1_d4"
267 };
268
269 static const char * const msdc50_0_parents[] __initconst = {
270 "clk26m",
271 "msdcpll_ck",
272 "msdcpll_d2",
273 "univpll1_d4",
274 "syspll2_d2",
275 "syspll_d7",
276 "msdcpll_d4",
277 "vencpll_d4",
278 "tvdpll_ck",
279 "univpll_d2",
280 "univpll1_d2",
281 "mmpll_ck",
282 "msdcpll2_ck",
283 "msdcpll2_d2",
284 "msdcpll2_d4"
285 };
286
287 static const char * const msdc30_1_parents[] __initconst = {
288 "clk26m",
289 "univpll2_d2",
290 "msdcpll_d4",
291 "univpll1_d4",
292 "syspll2_d2",
293 "syspll_d7",
294 "univpll_d7",
295 "vencpll_d4"
296 };
297
298 static const char * const msdc30_2_parents[] __initconst = {
299 "clk26m",
300 "univpll2_d2",
301 "msdcpll_d4",
302 "univpll1_d4",
303 "syspll2_d2",
304 "syspll_d7",
305 "univpll_d7",
306 "vencpll_d2"
307 };
308
309 static const char * const msdc30_3_parents[] __initconst = {
310 "clk26m",
311 "msdcpll2_ck",
312 "msdcpll2_d2",
313 "univpll2_d2",
314 "msdcpll2_d4",
315 "msdcpll_d4",
316 "univpll1_d4",
317 "syspll2_d2",
318 "syspll_d7",
319 "univpll_d7",
320 "vencpll_d4",
321 "msdcpll_ck",
322 "msdcpll_d2",
323 "msdcpll_d4"
324 };
325
326 static const char * const audio_parents[] __initconst = {
327 "clk26m",
328 "syspll3_d4",
329 "syspll4_d4",
330 "syspll1_d16"
331 };
332
333 static const char * const aud_intbus_parents[] __initconst = {
334 "clk26m",
335 "syspll1_d4",
336 "syspll4_d2",
337 "univpll3_d2",
338 "univpll2_d8",
339 "dmpll_d4",
340 "dmpll_d8"
341 };
342
343 static const char * const pmicspi_parents[] __initconst = {
344 "clk26m",
345 "syspll1_d8",
346 "syspll3_d4",
347 "syspll1_d16",
348 "univpll3_d4",
349 "univpll_d26",
350 "dmpll_d8",
351 "dmpll_d16"
352 };
353
354 static const char * const scp_parents[] __initconst = {
355 "clk26m",
356 "syspll1_d2",
357 "univpll_d5",
358 "syspll_d5",
359 "dmpll_d2",
360 "dmpll_d4"
361 };
362
363 static const char * const atb_parents[] __initconst = {
364 "clk26m",
365 "syspll1_d2",
366 "univpll_d5",
367 "dmpll_d2"
368 };
369
370 static const char * const venc_lt_parents[] __initconst = {
371 "clk26m",
372 "univpll_d3",
373 "vcodecpll_ck",
374 "tvdpll_445p5m",
375 "vencpll_d2",
376 "syspll_d3",
377 "univpll1_d2",
378 "univpll2_d2",
379 "syspll1_d2",
380 "univpll_d5",
381 "vcodecpll_370p5",
382 "dmpll_ck"
383 };
384
385 static const char * const dpi0_parents[] __initconst = {
386 "clk26m",
387 "tvdpll_d2",
388 "tvdpll_d4",
389 "clk26m",
390 "clk26m",
391 "tvdpll_d8",
392 "tvdpll_d16"
393 };
394
395 static const char * const irda_parents[] __initconst = {
396 "clk26m",
397 "univpll2_d4",
398 "syspll2_d4"
399 };
400
401 static const char * const cci400_parents[] __initconst = {
402 "clk26m",
403 "vencpll_ck",
404 "armca7pll_754m",
405 "armca7pll_502m",
406 "univpll_d2",
407 "syspll_d2",
408 "msdcpll_ck",
409 "dmpll_ck"
410 };
411
412 static const char * const aud_1_parents[] __initconst = {
413 "clk26m",
414 "apll1_ck",
415 "univpll2_d4",
416 "univpll2_d8"
417 };
418
419 static const char * const aud_2_parents[] __initconst = {
420 "clk26m",
421 "apll2_ck",
422 "univpll2_d4",
423 "univpll2_d8"
424 };
425
426 static const char * const mem_mfg_in_parents[] __initconst = {
427 "clk26m",
428 "mmpll_ck",
429 "dmpll_ck",
430 "clk26m"
431 };
432
433 static const char * const axi_mfg_in_parents[] __initconst = {
434 "clk26m",
435 "axi_sel",
436 "dmpll_d2"
437 };
438
439 static const char * const scam_parents[] __initconst = {
440 "clk26m",
441 "syspll3_d2",
442 "univpll2_d4",
443 "dmpll_d4"
444 };
445
446 static const char * const spinfi_ifr_parents[] __initconst = {
447 "clk26m",
448 "univpll2_d8",
449 "univpll3_d4",
450 "syspll4_d2",
451 "univpll2_d4",
452 "univpll3_d2",
453 "syspll1_d4",
454 "univpll1_d4"
455 };
456
457 static const char * const hdmi_parents[] __initconst = {
458 "clk26m",
459 "hdmitx_dig_cts",
460 "hdmitxpll_d2",
461 "hdmitxpll_d3"
462 };
463
464 static const char * const dpilvds_parents[] __initconst = {
465 "clk26m",
466 "lvdspll",
467 "lvdspll_d2",
468 "lvdspll_d4",
469 "lvdspll_d8",
470 "fpc_ck"
471 };
472
473 static const char * const msdc50_2_h_parents[] __initconst = {
474 "clk26m",
475 "syspll1_d2",
476 "syspll2_d2",
477 "syspll4_d2",
478 "univpll_d5",
479 "univpll1_d4"
480 };
481
482 static const char * const hdcp_parents[] __initconst = {
483 "clk26m",
484 "syspll4_d2",
485 "syspll3_d4",
486 "univpll2_d4"
487 };
488
489 static const char * const hdcp_24m_parents[] __initconst = {
490 "clk26m",
491 "univpll_d26",
492 "univpll_d52",
493 "univpll2_d8"
494 };
495
496 static const char * const rtc_parents[] __initconst = {
497 "clkrtc_int",
498 "clkrtc_ext",
499 "clk26m",
500 "univpll3_d8"
501 };
502
503 static const char * const i2s0_m_ck_parents[] __initconst = {
504 "apll1_div1",
505 "apll2_div1"
506 };
507
508 static const char * const i2s1_m_ck_parents[] __initconst = {
509 "apll1_div2",
510 "apll2_div2"
511 };
512
513 static const char * const i2s2_m_ck_parents[] __initconst = {
514 "apll1_div3",
515 "apll2_div3"
516 };
517
518 static const char * const i2s3_m_ck_parents[] __initconst = {
519 "apll1_div4",
520 "apll2_div4"
521 };
522
523 static const char * const i2s3_b_ck_parents[] __initconst = {
524 "apll1_div5",
525 "apll2_div5"
526 };
527
528 static const struct mtk_composite top_muxes[] __initconst = {
529 /* CLK_CFG_0 */
530 MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
531 MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1),
532 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
533 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
534 /* CLK_CFG_1 */
535 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
536 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
537 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
538 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),
539 /* CLK_CFG_2 */
540 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),
541 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
542 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
543 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),
544 /* CLK_CFG_3 */
545 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7),
546 MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x0070, 8, 3, 15),
547 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23),
548 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31),
549 /* CLK_CFG_4 */
550 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x0080, 0, 3, 7),
551 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x0080, 8, 4, 15),
552 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0080, 16, 2, 23),
553 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31),
554 /* CLK_CFG_5 */
555 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0090, 0, 3, 7 /* 7:5 */),
556 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
557 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
558 MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31),
559 /* CLK_CFG_6 */
560 /*
561 * The dpi0_sel clock should not propagate rate changes to its parent
562 * clock so the dpi driver can have full control over PLL and divider.
563 */
564 MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7, 0),
565 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
566 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),
567 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
568 /* CLK_CFG_7 */
569 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
570 MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents, 0x00b0, 8, 2, 15),
571 MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 0x00b0, 16, 2, 23),
572 MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
573 /* CLK_CFG_12 */
574 MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x00c0, 0, 3, 7),
575 MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
576 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24, 3, 31),
577 /* CLK_CFG_13 */
578 MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
579 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
580 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, 16, 2, 23),
581 MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2),
582
583 DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
584 DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
585 DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8),
586 DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16),
587 DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),
588 DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0),
589
590 DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
591 DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
592 DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8),
593 DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16),
594 DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24),
595 DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4),
596
597 MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1),
598 MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1),
599 MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1),
600 MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1),
601 MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
602 };
603
604 static const struct mtk_gate_regs infra_cg_regs __initconst = {
605 .set_ofs = 0x0040,
606 .clr_ofs = 0x0044,
607 .sta_ofs = 0x0048,
608 };
609
610 #define GATE_ICG(_id, _name, _parent, _shift) { \
611 .id = _id, \
612 .name = _name, \
613 .parent_name = _parent, \
614 .regs = &infra_cg_regs, \
615 .shift = _shift, \
616 .ops = &mtk_clk_gate_ops_setclr, \
617 }
618
619 static const struct mtk_gate infra_clks[] __initconst = {
620 GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
621 GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
622 GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
623 GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
624 GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
625 GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
626 GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15),
627 GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
628 GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18),
629 GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22),
630 GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
631 };
632
633 static const struct mtk_fixed_factor infra_divs[] __initconst = {
634 FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
635 };
636
637 static const struct mtk_gate_regs peri0_cg_regs __initconst = {
638 .set_ofs = 0x0008,
639 .clr_ofs = 0x0010,
640 .sta_ofs = 0x0018,
641 };
642
643 static const struct mtk_gate_regs peri1_cg_regs __initconst = {
644 .set_ofs = 0x000c,
645 .clr_ofs = 0x0014,
646 .sta_ofs = 0x001c,
647 };
648
649 #define GATE_PERI0(_id, _name, _parent, _shift) { \
650 .id = _id, \
651 .name = _name, \
652 .parent_name = _parent, \
653 .regs = &peri0_cg_regs, \
654 .shift = _shift, \
655 .ops = &mtk_clk_gate_ops_setclr, \
656 }
657
658 #define GATE_PERI1(_id, _name, _parent, _shift) { \
659 .id = _id, \
660 .name = _name, \
661 .parent_name = _parent, \
662 .regs = &peri1_cg_regs, \
663 .shift = _shift, \
664 .ops = &mtk_clk_gate_ops_setclr, \
665 }
666
667 static const struct mtk_gate peri_gates[] __initconst = {
668 /* PERI0 */
669 GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
670 GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
671 GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
672 GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
673 GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
674 GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
675 GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
676 GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
677 GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
678 GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
679 GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10),
680 GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
681 GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
682 GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
683 GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
684 GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
685 GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
686 GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
687 GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
688 GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
689 GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
690 GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
691 GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
692 GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
693 GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
694 GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
695 GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
696 GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
697 GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
698 GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
699 GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30),
700 GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31),
701 /* PERI1 */
702 GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0),
703 GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1),
704 GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2),
705 };
706
707 static const char * const uart_ck_sel_parents[] __initconst = {
708 "clk26m",
709 "uart_sel",
710 };
711
712 static const struct mtk_composite peri_clks[] __initconst = {
713 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
714 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
715 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
716 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
717 };
718
719 static const struct mtk_gate_regs cg_regs_4_8_0 __initconst = {
720 .set_ofs = 0x0004,
721 .clr_ofs = 0x0008,
722 .sta_ofs = 0x0000,
723 };
724
725 #define GATE_IMG(_id, _name, _parent, _shift) { \
726 .id = _id, \
727 .name = _name, \
728 .parent_name = _parent, \
729 .regs = &cg_regs_4_8_0, \
730 .shift = _shift, \
731 .ops = &mtk_clk_gate_ops_setclr, \
732 }
733
734 static const struct mtk_gate img_clks[] __initconst = {
735 GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0),
736 GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5),
737 GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6),
738 GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "camtg_sel", 7),
739 GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "mm_sel", 8),
740 GATE_IMG(CLK_IMG_CAM_SV, "img_cam_sv", "mm_sel", 9),
741 GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11),
742 };
743
744 static const struct mtk_gate_regs mm0_cg_regs __initconst = {
745 .set_ofs = 0x0104,
746 .clr_ofs = 0x0108,
747 .sta_ofs = 0x0100,
748 };
749
750 static const struct mtk_gate_regs mm1_cg_regs __initconst = {
751 .set_ofs = 0x0114,
752 .clr_ofs = 0x0118,
753 .sta_ofs = 0x0110,
754 };
755
756 #define GATE_MM0(_id, _name, _parent, _shift) { \
757 .id = _id, \
758 .name = _name, \
759 .parent_name = _parent, \
760 .regs = &mm0_cg_regs, \
761 .shift = _shift, \
762 .ops = &mtk_clk_gate_ops_setclr, \
763 }
764
765 #define GATE_MM1(_id, _name, _parent, _shift) { \
766 .id = _id, \
767 .name = _name, \
768 .parent_name = _parent, \
769 .regs = &mm1_cg_regs, \
770 .shift = _shift, \
771 .ops = &mtk_clk_gate_ops_setclr, \
772 }
773
774 static const struct mtk_gate mm_clks[] __initconst = {
775 /* MM0 */
776 GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
777 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
778 GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
779 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
780 GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
781 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
782 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
783 GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
784 GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
785 GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
786 GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
787 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
788 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
789 GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
790 GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
791 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
792 GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
793 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
794 GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
795 GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
796 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
797 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
798 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
799 GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
800 GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
801 GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
802 GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
803 GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
804 GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
805 GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),
806 GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
807 /* MM1 */
808 GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
809 GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),
810 GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),
811 GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),
812 GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
813 GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),
814 GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
815 GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),
816 GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),
817 GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
818 GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10),
819 GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
820 GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12),
821 GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13),
822 GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14),
823 GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15),
824 GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16),
825 GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17),
826 GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
827 GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19),
828 GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20),
829 };
830
831 static const struct mtk_gate_regs vdec0_cg_regs __initconst = {
832 .set_ofs = 0x0000,
833 .clr_ofs = 0x0004,
834 .sta_ofs = 0x0000,
835 };
836
837 static const struct mtk_gate_regs vdec1_cg_regs __initconst = {
838 .set_ofs = 0x0008,
839 .clr_ofs = 0x000c,
840 .sta_ofs = 0x0008,
841 };
842
843 #define GATE_VDEC0(_id, _name, _parent, _shift) { \
844 .id = _id, \
845 .name = _name, \
846 .parent_name = _parent, \
847 .regs = &vdec0_cg_regs, \
848 .shift = _shift, \
849 .ops = &mtk_clk_gate_ops_setclr_inv, \
850 }
851
852 #define GATE_VDEC1(_id, _name, _parent, _shift) { \
853 .id = _id, \
854 .name = _name, \
855 .parent_name = _parent, \
856 .regs = &vdec1_cg_regs, \
857 .shift = _shift, \
858 .ops = &mtk_clk_gate_ops_setclr_inv, \
859 }
860
861 static const struct mtk_gate vdec_clks[] __initconst = {
862 GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
863 GATE_VDEC1(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", 0),
864 };
865
866 #define GATE_VENC(_id, _name, _parent, _shift) { \
867 .id = _id, \
868 .name = _name, \
869 .parent_name = _parent, \
870 .regs = &cg_regs_4_8_0, \
871 .shift = _shift, \
872 .ops = &mtk_clk_gate_ops_setclr_inv, \
873 }
874
875 static const struct mtk_gate venc_clks[] __initconst = {
876 GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0),
877 GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "venc_sel", 4),
878 GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "venc_sel", 8),
879 GATE_VENC(CLK_VENC_CKE3, "venc_cke3", "venc_sel", 12),
880 };
881
882 #define GATE_VENCLT(_id, _name, _parent, _shift) { \
883 .id = _id, \
884 .name = _name, \
885 .parent_name = _parent, \
886 .regs = &cg_regs_4_8_0, \
887 .shift = _shift, \
888 .ops = &mtk_clk_gate_ops_setclr_inv, \
889 }
890
891 static const struct mtk_gate venclt_clks[] __initconst = {
892 GATE_VENCLT(CLK_VENCLT_CKE0, "venclt_cke0", "mm_sel", 0),
893 GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
894 };
895
896 static struct clk_onecell_data *mt8173_top_clk_data __initdata;
897 static struct clk_onecell_data *mt8173_pll_clk_data __initdata;
898
899 static void __init mtk_clk_enable_critical(void)
900 {
901 if (!mt8173_top_clk_data || !mt8173_pll_clk_data)
902 return;
903
904 clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
905 clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA7PLL]);
906 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]);
907 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
908 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_CCI400_SEL]);
909 clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_RTC_SEL]);
910 }
911
912 static void __init mtk_topckgen_init(struct device_node *node)
913 {
914 struct clk_onecell_data *clk_data;
915 void __iomem *base;
916 int r;
917
918 base = of_iomap(node, 0);
919 if (!base) {
920 pr_err("%s(): ioremap failed\n", __func__);
921 return;
922 }
923
924 mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
925
926 mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data);
927 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
928 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
929 &mt8173_clk_lock, clk_data);
930
931 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
932 if (r)
933 pr_err("%s(): could not register clock provider: %d\n",
934 __func__, r);
935
936 mtk_clk_enable_critical();
937 }
938 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
939
940 static void __init mtk_infrasys_init(struct device_node *node)
941 {
942 struct clk_onecell_data *clk_data;
943 int r;
944
945 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
946
947 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
948 clk_data);
949 mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
950
951 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
952 if (r)
953 pr_err("%s(): could not register clock provider: %d\n",
954 __func__, r);
955
956 mtk_register_reset_controller(node, 2, 0x30);
957 }
958 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
959
960 static void __init mtk_pericfg_init(struct device_node *node)
961 {
962 struct clk_onecell_data *clk_data;
963 int r;
964 void __iomem *base;
965
966 base = of_iomap(node, 0);
967 if (!base) {
968 pr_err("%s(): ioremap failed\n", __func__);
969 return;
970 }
971
972 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
973
974 mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
975 clk_data);
976 mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
977 &mt8173_clk_lock, clk_data);
978
979 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
980 if (r)
981 pr_err("%s(): could not register clock provider: %d\n",
982 __func__, r);
983
984 mtk_register_reset_controller(node, 2, 0);
985 }
986 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
987
988 struct mtk_clk_usb {
989 int id;
990 const char *name;
991 const char *parent;
992 u32 reg_ofs;
993 };
994
995 #define APMIXED_USB(_id, _name, _parent, _reg_ofs) { \
996 .id = _id, \
997 .name = _name, \
998 .parent = _parent, \
999 .reg_ofs = _reg_ofs, \
1000 }
1001
1002 static const struct mtk_clk_usb apmixed_usb[] __initconst = {
1003 APMIXED_USB(CLK_APMIXED_REF2USB_TX, "ref2usb_tx", "clk26m", 0x8),
1004 };
1005
1006 #define MT8173_PLL_FMAX (3000UL * MHZ)
1007
1008 #define CON0_MT8173_RST_BAR BIT(24)
1009
1010 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1011 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
1012 _pcw_shift, _div_table) { \
1013 .id = _id, \
1014 .name = _name, \
1015 .reg = _reg, \
1016 .pwr_reg = _pwr_reg, \
1017 .en_mask = _en_mask, \
1018 .flags = _flags, \
1019 .rst_bar_mask = CON0_MT8173_RST_BAR, \
1020 .fmax = MT8173_PLL_FMAX, \
1021 .pcwbits = _pcwbits, \
1022 .pd_reg = _pd_reg, \
1023 .pd_shift = _pd_shift, \
1024 .tuner_reg = _tuner_reg, \
1025 .pcw_reg = _pcw_reg, \
1026 .pcw_shift = _pcw_shift, \
1027 .div_table = _div_table, \
1028 }
1029
1030 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1031 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
1032 _pcw_shift) \
1033 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1034 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
1035 NULL)
1036
1037 static const struct mtk_pll_div_table mmpll_div_table[] = {
1038 { .div = 0, .freq = MT8173_PLL_FMAX },
1039 { .div = 1, .freq = 1000000000 },
1040 { .div = 2, .freq = 702000000 },
1041 { .div = 3, .freq = 253500000 },
1042 { .div = 4, .freq = 126750000 },
1043 { } /* sentinel */
1044 };
1045
1046 static const struct mtk_pll_data plls[] = {
1047 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
1048 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
1049 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
1050 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
1051 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
1052 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
1053 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
1054 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
1055 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0),
1056 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0),
1057 PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000001, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
1058 PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000001, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
1059 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000001, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
1060 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000001, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
1061 };
1062
1063 static void __init mtk_apmixedsys_init(struct device_node *node)
1064 {
1065 struct clk_onecell_data *clk_data;
1066 void __iomem *base;
1067 struct clk *clk;
1068 int r, i;
1069
1070 base = of_iomap(node, 0);
1071 if (!base) {
1072 pr_err("%s(): ioremap failed\n", __func__);
1073 return;
1074 }
1075
1076 mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1077 if (!clk_data) {
1078 iounmap(base);
1079 return;
1080 }
1081
1082 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1083
1084 for (i = 0; i < ARRAY_SIZE(apmixed_usb); i++) {
1085 const struct mtk_clk_usb *cku = &apmixed_usb[i];
1086
1087 clk = mtk_clk_register_ref2usb_tx(cku->name, cku->parent,
1088 base + cku->reg_ofs);
1089
1090 if (IS_ERR(clk)) {
1091 pr_err("Failed to register clk %s: %ld\n", cku->name,
1092 PTR_ERR(clk));
1093 continue;
1094 }
1095
1096 clk_data->clks[cku->id] = clk;
1097 }
1098
1099 clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
1100 base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
1101 NULL);
1102 clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;
1103
1104 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1105 if (r)
1106 pr_err("%s(): could not register clock provider: %d\n",
1107 __func__, r);
1108
1109 mtk_clk_enable_critical();
1110 }
1111 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
1112 mtk_apmixedsys_init);
1113
1114 static void __init mtk_imgsys_init(struct device_node *node)
1115 {
1116 struct clk_onecell_data *clk_data;
1117 int r;
1118
1119 clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
1120
1121 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
1122 clk_data);
1123
1124 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1125
1126 if (r)
1127 pr_err("%s(): could not register clock provider: %d\n",
1128 __func__, r);
1129 }
1130 CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
1131
1132 static void __init mtk_mmsys_init(struct device_node *node)
1133 {
1134 struct clk_onecell_data *clk_data;
1135 int r;
1136
1137 clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
1138
1139 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
1140 clk_data);
1141
1142 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1143 if (r)
1144 pr_err("%s(): could not register clock provider: %d\n",
1145 __func__, r);
1146 }
1147 CLK_OF_DECLARE(mtk_mmsys, "mediatek,mt8173-mmsys", mtk_mmsys_init);
1148
1149 static void __init mtk_vdecsys_init(struct device_node *node)
1150 {
1151 struct clk_onecell_data *clk_data;
1152 int r;
1153
1154 clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
1155
1156 mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
1157 clk_data);
1158
1159 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1160 if (r)
1161 pr_err("%s(): could not register clock provider: %d\n",
1162 __func__, r);
1163 }
1164 CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8173-vdecsys", mtk_vdecsys_init);
1165
1166 static void __init mtk_vencsys_init(struct device_node *node)
1167 {
1168 struct clk_onecell_data *clk_data;
1169 int r;
1170
1171 clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
1172
1173 mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
1174 clk_data);
1175
1176 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1177 if (r)
1178 pr_err("%s(): could not register clock provider: %d\n",
1179 __func__, r);
1180 }
1181 CLK_OF_DECLARE(mtk_vencsys, "mediatek,mt8173-vencsys", mtk_vencsys_init);
1182
1183 static void __init mtk_vencltsys_init(struct device_node *node)
1184 {
1185 struct clk_onecell_data *clk_data;
1186 int r;
1187
1188 clk_data = mtk_alloc_clk_data(CLK_VENCLT_NR_CLK);
1189
1190 mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks),
1191 clk_data);
1192
1193 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1194 if (r)
1195 pr_err("%s(): could not register clock provider: %d\n",
1196 __func__, r);
1197 }
1198 CLK_OF_DECLARE(mtk_vencltsys, "mediatek,mt8173-vencltsys", mtk_vencltsys_init);
Linux with added FPC-III support