?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sh_eth: fix EESIPR values for SH77{34|63}
[linux/fpc-iii.git] / drivers / clk / meson / gxbb.c
blob9d9af446bafc942db897159f2e077eb5d2440693
1 /*
2 * AmLogic S905 / GXBB Clock Controller Driver
3 *
4 * Copyright (c) 2016 AmLogic, Inc.
5 * Michael Turquette <mturquette@baylibre.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <linux/clk.h>
21 #include <linux/clk-provider.h>
22 #include <linux/of_address.h>
23 #include <linux/platform_device.h>
24 #include <linux/init.h>
25
26 #include "clkc.h"
27 #include "gxbb.h"
28
29 static DEFINE_SPINLOCK(clk_lock);
30
31 static const struct pll_rate_table sys_pll_rate_table[] = {
32 PLL_RATE(24000000, 56, 1, 2),
33 PLL_RATE(48000000, 64, 1, 2),
34 PLL_RATE(72000000, 72, 1, 2),
35 PLL_RATE(96000000, 64, 1, 2),
36 PLL_RATE(120000000, 80, 1, 2),
37 PLL_RATE(144000000, 96, 1, 2),
38 PLL_RATE(168000000, 56, 1, 1),
39 PLL_RATE(192000000, 64, 1, 1),
40 PLL_RATE(216000000, 72, 1, 1),
41 PLL_RATE(240000000, 80, 1, 1),
42 PLL_RATE(264000000, 88, 1, 1),
43 PLL_RATE(288000000, 96, 1, 1),
44 PLL_RATE(312000000, 52, 1, 2),
45 PLL_RATE(336000000, 56, 1, 2),
46 PLL_RATE(360000000, 60, 1, 2),
47 PLL_RATE(384000000, 64, 1, 2),
48 PLL_RATE(408000000, 68, 1, 2),
49 PLL_RATE(432000000, 72, 1, 2),
50 PLL_RATE(456000000, 76, 1, 2),
51 PLL_RATE(480000000, 80, 1, 2),
52 PLL_RATE(504000000, 84, 1, 2),
53 PLL_RATE(528000000, 88, 1, 2),
54 PLL_RATE(552000000, 92, 1, 2),
55 PLL_RATE(576000000, 96, 1, 2),
56 PLL_RATE(600000000, 50, 1, 1),
57 PLL_RATE(624000000, 52, 1, 1),
58 PLL_RATE(648000000, 54, 1, 1),
59 PLL_RATE(672000000, 56, 1, 1),
60 PLL_RATE(696000000, 58, 1, 1),
61 PLL_RATE(720000000, 60, 1, 1),
62 PLL_RATE(744000000, 62, 1, 1),
63 PLL_RATE(768000000, 64, 1, 1),
64 PLL_RATE(792000000, 66, 1, 1),
65 PLL_RATE(816000000, 68, 1, 1),
66 PLL_RATE(840000000, 70, 1, 1),
67 PLL_RATE(864000000, 72, 1, 1),
68 PLL_RATE(888000000, 74, 1, 1),
69 PLL_RATE(912000000, 76, 1, 1),
70 PLL_RATE(936000000, 78, 1, 1),
71 PLL_RATE(960000000, 80, 1, 1),
72 PLL_RATE(984000000, 82, 1, 1),
73 PLL_RATE(1008000000, 84, 1, 1),
74 PLL_RATE(1032000000, 86, 1, 1),
75 PLL_RATE(1056000000, 88, 1, 1),
76 PLL_RATE(1080000000, 90, 1, 1),
77 PLL_RATE(1104000000, 92, 1, 1),
78 PLL_RATE(1128000000, 94, 1, 1),
79 PLL_RATE(1152000000, 96, 1, 1),
80 PLL_RATE(1176000000, 98, 1, 1),
81 PLL_RATE(1200000000, 50, 1, 0),
82 PLL_RATE(1224000000, 51, 1, 0),
83 PLL_RATE(1248000000, 52, 1, 0),
84 PLL_RATE(1272000000, 53, 1, 0),
85 PLL_RATE(1296000000, 54, 1, 0),
86 PLL_RATE(1320000000, 55, 1, 0),
87 PLL_RATE(1344000000, 56, 1, 0),
88 PLL_RATE(1368000000, 57, 1, 0),
89 PLL_RATE(1392000000, 58, 1, 0),
90 PLL_RATE(1416000000, 59, 1, 0),
91 PLL_RATE(1440000000, 60, 1, 0),
92 PLL_RATE(1464000000, 61, 1, 0),
93 PLL_RATE(1488000000, 62, 1, 0),
94 PLL_RATE(1512000000, 63, 1, 0),
95 PLL_RATE(1536000000, 64, 1, 0),
96 PLL_RATE(1560000000, 65, 1, 0),
97 PLL_RATE(1584000000, 66, 1, 0),
98 PLL_RATE(1608000000, 67, 1, 0),
99 PLL_RATE(1632000000, 68, 1, 0),
100 PLL_RATE(1656000000, 68, 1, 0),
101 PLL_RATE(1680000000, 68, 1, 0),
102 PLL_RATE(1704000000, 68, 1, 0),
103 PLL_RATE(1728000000, 69, 1, 0),
104 PLL_RATE(1752000000, 69, 1, 0),
105 PLL_RATE(1776000000, 69, 1, 0),
106 PLL_RATE(1800000000, 69, 1, 0),
107 PLL_RATE(1824000000, 70, 1, 0),
108 PLL_RATE(1848000000, 70, 1, 0),
109 PLL_RATE(1872000000, 70, 1, 0),
110 PLL_RATE(1896000000, 70, 1, 0),
111 PLL_RATE(1920000000, 71, 1, 0),
112 PLL_RATE(1944000000, 71, 1, 0),
113 PLL_RATE(1968000000, 71, 1, 0),
114 PLL_RATE(1992000000, 71, 1, 0),
115 PLL_RATE(2016000000, 72, 1, 0),
116 PLL_RATE(2040000000, 72, 1, 0),
117 PLL_RATE(2064000000, 72, 1, 0),
118 PLL_RATE(2088000000, 72, 1, 0),
119 PLL_RATE(2112000000, 73, 1, 0),
120 { /* sentinel */ },
121 };
122
123 static const struct pll_rate_table gp0_pll_rate_table[] = {
124 PLL_RATE(96000000, 32, 1, 3),
125 PLL_RATE(99000000, 33, 1, 3),
126 PLL_RATE(102000000, 34, 1, 3),
127 PLL_RATE(105000000, 35, 1, 3),
128 PLL_RATE(108000000, 36, 1, 3),
129 PLL_RATE(111000000, 37, 1, 3),
130 PLL_RATE(114000000, 38, 1, 3),
131 PLL_RATE(117000000, 39, 1, 3),
132 PLL_RATE(120000000, 40, 1, 3),
133 PLL_RATE(123000000, 41, 1, 3),
134 PLL_RATE(126000000, 42, 1, 3),
135 PLL_RATE(129000000, 43, 1, 3),
136 PLL_RATE(132000000, 44, 1, 3),
137 PLL_RATE(135000000, 45, 1, 3),
138 PLL_RATE(138000000, 46, 1, 3),
139 PLL_RATE(141000000, 47, 1, 3),
140 PLL_RATE(144000000, 48, 1, 3),
141 PLL_RATE(147000000, 49, 1, 3),
142 PLL_RATE(150000000, 50, 1, 3),
143 PLL_RATE(153000000, 51, 1, 3),
144 PLL_RATE(156000000, 52, 1, 3),
145 PLL_RATE(159000000, 53, 1, 3),
146 PLL_RATE(162000000, 54, 1, 3),
147 PLL_RATE(165000000, 55, 1, 3),
148 PLL_RATE(168000000, 56, 1, 3),
149 PLL_RATE(171000000, 57, 1, 3),
150 PLL_RATE(174000000, 58, 1, 3),
151 PLL_RATE(177000000, 59, 1, 3),
152 PLL_RATE(180000000, 60, 1, 3),
153 PLL_RATE(183000000, 61, 1, 3),
154 PLL_RATE(186000000, 62, 1, 3),
155 PLL_RATE(192000000, 32, 1, 2),
156 PLL_RATE(198000000, 33, 1, 2),
157 PLL_RATE(204000000, 34, 1, 2),
158 PLL_RATE(210000000, 35, 1, 2),
159 PLL_RATE(216000000, 36, 1, 2),
160 PLL_RATE(222000000, 37, 1, 2),
161 PLL_RATE(228000000, 38, 1, 2),
162 PLL_RATE(234000000, 39, 1, 2),
163 PLL_RATE(240000000, 40, 1, 2),
164 PLL_RATE(246000000, 41, 1, 2),
165 PLL_RATE(252000000, 42, 1, 2),
166 PLL_RATE(258000000, 43, 1, 2),
167 PLL_RATE(264000000, 44, 1, 2),
168 PLL_RATE(270000000, 45, 1, 2),
169 PLL_RATE(276000000, 46, 1, 2),
170 PLL_RATE(282000000, 47, 1, 2),
171 PLL_RATE(288000000, 48, 1, 2),
172 PLL_RATE(294000000, 49, 1, 2),
173 PLL_RATE(300000000, 50, 1, 2),
174 PLL_RATE(306000000, 51, 1, 2),
175 PLL_RATE(312000000, 52, 1, 2),
176 PLL_RATE(318000000, 53, 1, 2),
177 PLL_RATE(324000000, 54, 1, 2),
178 PLL_RATE(330000000, 55, 1, 2),
179 PLL_RATE(336000000, 56, 1, 2),
180 PLL_RATE(342000000, 57, 1, 2),
181 PLL_RATE(348000000, 58, 1, 2),
182 PLL_RATE(354000000, 59, 1, 2),
183 PLL_RATE(360000000, 60, 1, 2),
184 PLL_RATE(366000000, 61, 1, 2),
185 PLL_RATE(372000000, 62, 1, 2),
186 PLL_RATE(384000000, 32, 1, 1),
187 PLL_RATE(396000000, 33, 1, 1),
188 PLL_RATE(408000000, 34, 1, 1),
189 PLL_RATE(420000000, 35, 1, 1),
190 PLL_RATE(432000000, 36, 1, 1),
191 PLL_RATE(444000000, 37, 1, 1),
192 PLL_RATE(456000000, 38, 1, 1),
193 PLL_RATE(468000000, 39, 1, 1),
194 PLL_RATE(480000000, 40, 1, 1),
195 PLL_RATE(492000000, 41, 1, 1),
196 PLL_RATE(504000000, 42, 1, 1),
197 PLL_RATE(516000000, 43, 1, 1),
198 PLL_RATE(528000000, 44, 1, 1),
199 PLL_RATE(540000000, 45, 1, 1),
200 PLL_RATE(552000000, 46, 1, 1),
201 PLL_RATE(564000000, 47, 1, 1),
202 PLL_RATE(576000000, 48, 1, 1),
203 PLL_RATE(588000000, 49, 1, 1),
204 PLL_RATE(600000000, 50, 1, 1),
205 PLL_RATE(612000000, 51, 1, 1),
206 PLL_RATE(624000000, 52, 1, 1),
207 PLL_RATE(636000000, 53, 1, 1),
208 PLL_RATE(648000000, 54, 1, 1),
209 PLL_RATE(660000000, 55, 1, 1),
210 PLL_RATE(672000000, 56, 1, 1),
211 PLL_RATE(684000000, 57, 1, 1),
212 PLL_RATE(696000000, 58, 1, 1),
213 PLL_RATE(708000000, 59, 1, 1),
214 PLL_RATE(720000000, 60, 1, 1),
215 PLL_RATE(732000000, 61, 1, 1),
216 PLL_RATE(744000000, 62, 1, 1),
217 PLL_RATE(768000000, 32, 1, 0),
218 PLL_RATE(792000000, 33, 1, 0),
219 PLL_RATE(816000000, 34, 1, 0),
220 PLL_RATE(840000000, 35, 1, 0),
221 PLL_RATE(864000000, 36, 1, 0),
222 PLL_RATE(888000000, 37, 1, 0),
223 PLL_RATE(912000000, 38, 1, 0),
224 PLL_RATE(936000000, 39, 1, 0),
225 PLL_RATE(960000000, 40, 1, 0),
226 PLL_RATE(984000000, 41, 1, 0),
227 PLL_RATE(1008000000, 42, 1, 0),
228 PLL_RATE(1032000000, 43, 1, 0),
229 PLL_RATE(1056000000, 44, 1, 0),
230 PLL_RATE(1080000000, 45, 1, 0),
231 PLL_RATE(1104000000, 46, 1, 0),
232 PLL_RATE(1128000000, 47, 1, 0),
233 PLL_RATE(1152000000, 48, 1, 0),
234 PLL_RATE(1176000000, 49, 1, 0),
235 PLL_RATE(1200000000, 50, 1, 0),
236 PLL_RATE(1224000000, 51, 1, 0),
237 PLL_RATE(1248000000, 52, 1, 0),
238 PLL_RATE(1272000000, 53, 1, 0),
239 PLL_RATE(1296000000, 54, 1, 0),
240 PLL_RATE(1320000000, 55, 1, 0),
241 PLL_RATE(1344000000, 56, 1, 0),
242 PLL_RATE(1368000000, 57, 1, 0),
243 PLL_RATE(1392000000, 58, 1, 0),
244 PLL_RATE(1416000000, 59, 1, 0),
245 PLL_RATE(1440000000, 60, 1, 0),
246 PLL_RATE(1464000000, 61, 1, 0),
247 PLL_RATE(1488000000, 62, 1, 0),
248 { /* sentinel */ },
249 };
250
251 static const struct clk_div_table cpu_div_table[] = {
252 { .val = 1, .div = 1 },
253 { .val = 2, .div = 2 },
254 { .val = 3, .div = 3 },
255 { .val = 2, .div = 4 },
256 { .val = 3, .div = 6 },
257 { .val = 4, .div = 8 },
258 { .val = 5, .div = 10 },
259 { .val = 6, .div = 12 },
260 { .val = 7, .div = 14 },
261 { .val = 8, .div = 16 },
262 { /* sentinel */ },
263 };
264
265 static struct meson_clk_pll gxbb_fixed_pll = {
266 .m = {
267 .reg_off = HHI_MPLL_CNTL,
268 .shift = 0,
269 .width = 9,
270 },
271 .n = {
272 .reg_off = HHI_MPLL_CNTL,
273 .shift = 9,
274 .width = 5,
275 },
276 .od = {
277 .reg_off = HHI_MPLL_CNTL,
278 .shift = 16,
279 .width = 2,
280 },
281 .lock = &clk_lock,
282 .hw.init = &(struct clk_init_data){
283 .name = "fixed_pll",
284 .ops = &meson_clk_pll_ro_ops,
285 .parent_names = (const char *[]){ "xtal" },
286 .num_parents = 1,
287 .flags = CLK_GET_RATE_NOCACHE,
288 },
289 };
290
291 static struct meson_clk_pll gxbb_hdmi_pll = {
292 .m = {
293 .reg_off = HHI_HDMI_PLL_CNTL,
294 .shift = 0,
295 .width = 9,
296 },
297 .n = {
298 .reg_off = HHI_HDMI_PLL_CNTL,
299 .shift = 9,
300 .width = 5,
301 },
302 .frac = {
303 .reg_off = HHI_HDMI_PLL_CNTL2,
304 .shift = 0,
305 .width = 12,
306 },
307 .od = {
308 .reg_off = HHI_HDMI_PLL_CNTL2,
309 .shift = 16,
310 .width = 2,
311 },
312 .od2 = {
313 .reg_off = HHI_HDMI_PLL_CNTL2,
314 .shift = 22,
315 .width = 2,
316 },
317 .lock = &clk_lock,
318 .hw.init = &(struct clk_init_data){
319 .name = "hdmi_pll",
320 .ops = &meson_clk_pll_ro_ops,
321 .parent_names = (const char *[]){ "xtal" },
322 .num_parents = 1,
323 .flags = CLK_GET_RATE_NOCACHE,
324 },
325 };
326
327 static struct meson_clk_pll gxbb_sys_pll = {
328 .m = {
329 .reg_off = HHI_SYS_PLL_CNTL,
330 .shift = 0,
331 .width = 9,
332 },
333 .n = {
334 .reg_off = HHI_SYS_PLL_CNTL,
335 .shift = 9,
336 .width = 5,
337 },
338 .od = {
339 .reg_off = HHI_SYS_PLL_CNTL,
340 .shift = 10,
341 .width = 2,
342 },
343 .rate_table = sys_pll_rate_table,
344 .rate_count = ARRAY_SIZE(sys_pll_rate_table),
345 .lock = &clk_lock,
346 .hw.init = &(struct clk_init_data){
347 .name = "sys_pll",
348 .ops = &meson_clk_pll_ro_ops,
349 .parent_names = (const char *[]){ "xtal" },
350 .num_parents = 1,
351 .flags = CLK_GET_RATE_NOCACHE,
352 },
353 };
354
355 static struct meson_clk_pll gxbb_gp0_pll = {
356 .m = {
357 .reg_off = HHI_GP0_PLL_CNTL,
358 .shift = 0,
359 .width = 9,
360 },
361 .n = {
362 .reg_off = HHI_GP0_PLL_CNTL,
363 .shift = 9,
364 .width = 5,
365 },
366 .od = {
367 .reg_off = HHI_GP0_PLL_CNTL,
368 .shift = 16,
369 .width = 2,
370 },
371 .rate_table = gp0_pll_rate_table,
372 .rate_count = ARRAY_SIZE(gp0_pll_rate_table),
373 .lock = &clk_lock,
374 .hw.init = &(struct clk_init_data){
375 .name = "gp0_pll",
376 .ops = &meson_clk_pll_ops,
377 .parent_names = (const char *[]){ "xtal" },
378 .num_parents = 1,
379 .flags = CLK_GET_RATE_NOCACHE,
380 },
381 };
382
383 static struct clk_fixed_factor gxbb_fclk_div2 = {
384 .mult = 1,
385 .div = 2,
386 .hw.init = &(struct clk_init_data){
387 .name = "fclk_div2",
388 .ops = &clk_fixed_factor_ops,
389 .parent_names = (const char *[]){ "fixed_pll" },
390 .num_parents = 1,
391 },
392 };
393
394 static struct clk_fixed_factor gxbb_fclk_div3 = {
395 .mult = 1,
396 .div = 3,
397 .hw.init = &(struct clk_init_data){
398 .name = "fclk_div3",
399 .ops = &clk_fixed_factor_ops,
400 .parent_names = (const char *[]){ "fixed_pll" },
401 .num_parents = 1,
402 },
403 };
404
405 static struct clk_fixed_factor gxbb_fclk_div4 = {
406 .mult = 1,
407 .div = 4,
408 .hw.init = &(struct clk_init_data){
409 .name = "fclk_div4",
410 .ops = &clk_fixed_factor_ops,
411 .parent_names = (const char *[]){ "fixed_pll" },
412 .num_parents = 1,
413 },
414 };
415
416 static struct clk_fixed_factor gxbb_fclk_div5 = {
417 .mult = 1,
418 .div = 5,
419 .hw.init = &(struct clk_init_data){
420 .name = "fclk_div5",
421 .ops = &clk_fixed_factor_ops,
422 .parent_names = (const char *[]){ "fixed_pll" },
423 .num_parents = 1,
424 },
425 };
426
427 static struct clk_fixed_factor gxbb_fclk_div7 = {
428 .mult = 1,
429 .div = 7,
430 .hw.init = &(struct clk_init_data){
431 .name = "fclk_div7",
432 .ops = &clk_fixed_factor_ops,
433 .parent_names = (const char *[]){ "fixed_pll" },
434 .num_parents = 1,
435 },
436 };
437
438 static struct meson_clk_mpll gxbb_mpll0 = {
439 .sdm = {
440 .reg_off = HHI_MPLL_CNTL7,
441 .shift = 0,
442 .width = 14,
443 },
444 .n2 = {
445 .reg_off = HHI_MPLL_CNTL7,
446 .shift = 16,
447 .width = 9,
448 },
449 .lock = &clk_lock,
450 .hw.init = &(struct clk_init_data){
451 .name = "mpll0",
452 .ops = &meson_clk_mpll_ro_ops,
453 .parent_names = (const char *[]){ "fixed_pll" },
454 .num_parents = 1,
455 },
456 };
457
458 static struct meson_clk_mpll gxbb_mpll1 = {
459 .sdm = {
460 .reg_off = HHI_MPLL_CNTL8,
461 .shift = 0,
462 .width = 14,
463 },
464 .n2 = {
465 .reg_off = HHI_MPLL_CNTL8,
466 .shift = 16,
467 .width = 9,
468 },
469 .lock = &clk_lock,
470 .hw.init = &(struct clk_init_data){
471 .name = "mpll1",
472 .ops = &meson_clk_mpll_ro_ops,
473 .parent_names = (const char *[]){ "fixed_pll" },
474 .num_parents = 1,
475 },
476 };
477
478 static struct meson_clk_mpll gxbb_mpll2 = {
479 .sdm = {
480 .reg_off = HHI_MPLL_CNTL9,
481 .shift = 0,
482 .width = 14,
483 },
484 .n2 = {
485 .reg_off = HHI_MPLL_CNTL9,
486 .shift = 16,
487 .width = 9,
488 },
489 .lock = &clk_lock,
490 .hw.init = &(struct clk_init_data){
491 .name = "mpll2",
492 .ops = &meson_clk_mpll_ro_ops,
493 .parent_names = (const char *[]){ "fixed_pll" },
494 .num_parents = 1,
495 },
496 };
497
498 /*
499 * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
500 * post-dividers and should be modeled with their respective PLLs via the
501 * forthcoming coordinated clock rates feature
502 */
503 static struct meson_clk_cpu gxbb_cpu_clk = {
504 .reg_off = HHI_SYS_CPU_CLK_CNTL1,
505 .div_table = cpu_div_table,
506 .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
507 .hw.init = &(struct clk_init_data){
508 .name = "cpu_clk",
509 .ops = &meson_clk_cpu_ops,
510 .parent_names = (const char *[]){ "sys_pll" },
511 .num_parents = 1,
512 },
513 };
514
515 static u32 mux_table_clk81[] = { 6, 5, 7 };
516
517 static struct clk_mux gxbb_mpeg_clk_sel = {
518 .reg = (void *)HHI_MPEG_CLK_CNTL,
519 .mask = 0x7,
520 .shift = 12,
521 .flags = CLK_MUX_READ_ONLY,
522 .table = mux_table_clk81,
523 .lock = &clk_lock,
524 .hw.init = &(struct clk_init_data){
525 .name = "mpeg_clk_sel",
526 .ops = &clk_mux_ro_ops,
527 /*
528 * FIXME bits 14:12 selects from 8 possible parents:
529 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
530 * fclk_div4, fclk_div3, fclk_div5
531 */
532 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
533 "fclk_div5" },
534 .num_parents = 3,
535 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
536 },
537 };
538
539 static struct clk_divider gxbb_mpeg_clk_div = {
540 .reg = (void *)HHI_MPEG_CLK_CNTL,
541 .shift = 0,
542 .width = 7,
543 .lock = &clk_lock,
544 .hw.init = &(struct clk_init_data){
545 .name = "mpeg_clk_div",
546 .ops = &clk_divider_ops,
547 .parent_names = (const char *[]){ "mpeg_clk_sel" },
548 .num_parents = 1,
549 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
550 },
551 };
552
553 /* the mother of dragons^W gates */
554 static struct clk_gate gxbb_clk81 = {
555 .reg = (void *)HHI_MPEG_CLK_CNTL,
556 .bit_idx = 7,
557 .lock = &clk_lock,
558 .hw.init = &(struct clk_init_data){
559 .name = "clk81",
560 .ops = &clk_gate_ops,
561 .parent_names = (const char *[]){ "mpeg_clk_div" },
562 .num_parents = 1,
563 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL),
564 },
565 };
566
567 /* Everything Else (EE) domain gates */
568 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
569 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
570 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
571 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
572 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
573 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
574 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
575 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10);
576 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
577 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
578 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
579 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
580 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
581 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
582 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
583 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
584 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
585 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
586 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
587 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
588 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
589 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
590
591 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
592 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
593 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
594 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
595 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
596 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
597 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
598 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
599 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
600 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
601 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
602 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
603 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
604 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
605 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
606 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
607 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
608 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
609 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
610 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
611 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
612 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
613 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
614 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
615 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
616
617 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
618 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
619 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
620 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
621 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
622 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
623 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
624 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
625 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
626 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22);
627 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
628 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
629 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
630
631 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
632 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
633 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
634 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
635 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
636 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
637 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
638 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
639 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
640 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
641 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
642 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
643 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
644 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
645 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
646 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
647
648 /* Always On (AO) domain gates */
649
650 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
651 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
652 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
653 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
654 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
655
656 /* Array of all clocks provided by this provider */
657
658 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
659 .hws = {
660 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
661 [CLKID_CPUCLK] = &gxbb_cpu_clk.hw,
662 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
663 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
664 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
665 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
666 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
667 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
668 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
669 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
670 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
671 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
672 [CLKID_CLK81] = &gxbb_clk81.hw,
673 [CLKID_MPLL0] = &gxbb_mpll0.hw,
674 [CLKID_MPLL1] = &gxbb_mpll1.hw,
675 [CLKID_MPLL2] = &gxbb_mpll2.hw,
676 [CLKID_DDR] = &gxbb_ddr.hw,
677 [CLKID_DOS] = &gxbb_dos.hw,
678 [CLKID_ISA] = &gxbb_isa.hw,
679 [CLKID_PL301] = &gxbb_pl301.hw,
680 [CLKID_PERIPHS] = &gxbb_periphs.hw,
681 [CLKID_SPICC] = &gxbb_spicc.hw,
682 [CLKID_I2C] = &gxbb_i2c.hw,
683 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
684 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
685 [CLKID_RNG0] = &gxbb_rng0.hw,
686 [CLKID_UART0] = &gxbb_uart0.hw,
687 [CLKID_SDHC] = &gxbb_sdhc.hw,
688 [CLKID_STREAM] = &gxbb_stream.hw,
689 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
690 [CLKID_SDIO] = &gxbb_sdio.hw,
691 [CLKID_ABUF] = &gxbb_abuf.hw,
692 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
693 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
694 [CLKID_SPI] = &gxbb_spi.hw,
695 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
696 [CLKID_ETH] = &gxbb_eth.hw,
697 [CLKID_DEMUX] = &gxbb_demux.hw,
698 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
699 [CLKID_IEC958] = &gxbb_iec958.hw,
700 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
701 [CLKID_AMCLK] = &gxbb_amclk.hw,
702 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
703 [CLKID_MIXER] = &gxbb_mixer.hw,
704 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
705 [CLKID_ADC] = &gxbb_adc.hw,
706 [CLKID_BLKMV] = &gxbb_blkmv.hw,
707 [CLKID_AIU] = &gxbb_aiu.hw,
708 [CLKID_UART1] = &gxbb_uart1.hw,
709 [CLKID_G2D] = &gxbb_g2d.hw,
710 [CLKID_USB0] = &gxbb_usb0.hw,
711 [CLKID_USB1] = &gxbb_usb1.hw,
712 [CLKID_RESET] = &gxbb_reset.hw,
713 [CLKID_NAND] = &gxbb_nand.hw,
714 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
715 [CLKID_USB] = &gxbb_usb.hw,
716 [CLKID_VDIN1] = &gxbb_vdin1.hw,
717 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
718 [CLKID_EFUSE] = &gxbb_efuse.hw,
719 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
720 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
721 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
722 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
723 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
724 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
725 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
726 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
727 [CLKID_DVIN] = &gxbb_dvin.hw,
728 [CLKID_UART2] = &gxbb_uart2.hw,
729 [CLKID_SANA] = &gxbb_sana.hw,
730 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
731 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
732 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
733 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
734 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
735 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
736 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
737 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
738 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
739 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
740 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
741 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
742 [CLKID_ENC480P] = &gxbb_enc480p.hw,
743 [CLKID_RNG1] = &gxbb_rng1.hw,
744 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
745 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
746 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
747 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
748 [CLKID_EDP] = &gxbb_edp.hw,
749 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
750 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
751 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
752 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
753 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
754 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
755 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
756 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
757 },
758 .num = NR_CLKS,
759 };
760
761 /* Convenience tables to populate base addresses in .probe */
762
763 static struct meson_clk_pll *const gxbb_clk_plls[] = {
764 &gxbb_fixed_pll,
765 &gxbb_hdmi_pll,
766 &gxbb_sys_pll,
767 &gxbb_gp0_pll,
768 };
769
770 static struct meson_clk_mpll *const gxbb_clk_mplls[] = {
771 &gxbb_mpll0,
772 &gxbb_mpll1,
773 &gxbb_mpll2,
774 };
775
776 static struct clk_gate *gxbb_clk_gates[] = {
777 &gxbb_clk81,
778 &gxbb_ddr,
779 &gxbb_dos,
780 &gxbb_isa,
781 &gxbb_pl301,
782 &gxbb_periphs,
783 &gxbb_spicc,
784 &gxbb_i2c,
785 &gxbb_sar_adc,
786 &gxbb_smart_card,
787 &gxbb_rng0,
788 &gxbb_uart0,
789 &gxbb_sdhc,
790 &gxbb_stream,
791 &gxbb_async_fifo,
792 &gxbb_sdio,
793 &gxbb_abuf,
794 &gxbb_hiu_iface,
795 &gxbb_assist_misc,
796 &gxbb_spi,
797 &gxbb_i2s_spdif,
798 &gxbb_eth,
799 &gxbb_demux,
800 &gxbb_aiu_glue,
801 &gxbb_iec958,
802 &gxbb_i2s_out,
803 &gxbb_amclk,
804 &gxbb_aififo2,
805 &gxbb_mixer,
806 &gxbb_mixer_iface,
807 &gxbb_adc,
808 &gxbb_blkmv,
809 &gxbb_aiu,
810 &gxbb_uart1,
811 &gxbb_g2d,
812 &gxbb_usb0,
813 &gxbb_usb1,
814 &gxbb_reset,
815 &gxbb_nand,
816 &gxbb_dos_parser,
817 &gxbb_usb,
818 &gxbb_vdin1,
819 &gxbb_ahb_arb0,
820 &gxbb_efuse,
821 &gxbb_boot_rom,
822 &gxbb_ahb_data_bus,
823 &gxbb_ahb_ctrl_bus,
824 &gxbb_hdmi_intr_sync,
825 &gxbb_hdmi_pclk,
826 &gxbb_usb1_ddr_bridge,
827 &gxbb_usb0_ddr_bridge,
828 &gxbb_mmc_pclk,
829 &gxbb_dvin,
830 &gxbb_uart2,
831 &gxbb_sana,
832 &gxbb_vpu_intr,
833 &gxbb_sec_ahb_ahb3_bridge,
834 &gxbb_clk81_a53,
835 &gxbb_vclk2_venci0,
836 &gxbb_vclk2_venci1,
837 &gxbb_vclk2_vencp0,
838 &gxbb_vclk2_vencp1,
839 &gxbb_gclk_venci_int0,
840 &gxbb_gclk_vencp_int,
841 &gxbb_dac_clk,
842 &gxbb_aoclk_gate,
843 &gxbb_iec958_gate,
844 &gxbb_enc480p,
845 &gxbb_rng1,
846 &gxbb_gclk_venci_int1,
847 &gxbb_vclk2_venclmcc,
848 &gxbb_vclk2_vencl,
849 &gxbb_vclk_other,
850 &gxbb_edp,
851 &gxbb_ao_media_cpu,
852 &gxbb_ao_ahb_sram,
853 &gxbb_ao_ahb_bus,
854 &gxbb_ao_iface,
855 &gxbb_ao_i2c,
856 &gxbb_emmc_a,
857 &gxbb_emmc_b,
858 &gxbb_emmc_c,
859 };
860
861 static int gxbb_clkc_probe(struct platform_device *pdev)
862 {
863 void __iomem *clk_base;
864 int ret, clkid, i;
865 struct clk_hw *parent_hw;
866 struct clk *parent_clk;
867 struct device *dev = &pdev->dev;
868
869 /* Generic clocks and PLLs */
870 clk_base = of_iomap(dev->of_node, 0);
871 if (!clk_base) {
872 pr_err("%s: Unable to map clk base\n", __func__);
873 return -ENXIO;
874 }
875
876 /* Populate base address for PLLs */
877 for (i = 0; i < ARRAY_SIZE(gxbb_clk_plls); i++)
878 gxbb_clk_plls[i]->base = clk_base;
879
880 /* Populate base address for MPLLs */
881 for (i = 0; i < ARRAY_SIZE(gxbb_clk_mplls); i++)
882 gxbb_clk_mplls[i]->base = clk_base;
883
884 /* Populate the base address for CPU clk */
885 gxbb_cpu_clk.base = clk_base;
886
887 /* Populate the base address for the MPEG clks */
888 gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
889 gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
890
891 /* Populate base address for gates */
892 for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
893 gxbb_clk_gates[i]->reg = clk_base +
894 (u64)gxbb_clk_gates[i]->reg;
895
896 /*
897 * register all clks
898 */
899 for (clkid = 0; clkid < NR_CLKS; clkid++) {
900 ret = devm_clk_hw_register(dev, gxbb_hw_onecell_data.hws[clkid]);
901 if (ret)
902 goto iounmap;
903 }
904
905 /*
906 * Register CPU clk notifier
907 *
908 * FIXME this is wrong for a lot of reasons. First, the muxes should be
909 * struct clk_hw objects. Second, we shouldn't program the muxes in
910 * notifier handlers. The tricky programming sequence will be handled
911 * by the forthcoming coordinated clock rates mechanism once that
912 * feature is released.
913 *
914 * Furthermore, looking up the parent this way is terrible. At some
915 * point we will stop allocating a default struct clk when registering
916 * a new clk_hw, and this hack will no longer work. Releasing the ccr
917 * feature before that time solves the problem :-)
918 */
919 parent_hw = clk_hw_get_parent(&gxbb_cpu_clk.hw);
920 parent_clk = parent_hw->clk;
921 ret = clk_notifier_register(parent_clk, &gxbb_cpu_clk.clk_nb);
922 if (ret) {
923 pr_err("%s: failed to register clock notifier for cpu_clk\n",
924 __func__);
925 goto iounmap;
926 }
927
928 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
929 &gxbb_hw_onecell_data);
930
931 iounmap:
932 iounmap(clk_base);
933 return ret;
934 }
935
936 static const struct of_device_id gxbb_clkc_match_table[] = {
937 { .compatible = "amlogic,gxbb-clkc" },
938 { }
939 };
940
941 static struct platform_driver gxbb_driver = {
942 .probe = gxbb_clkc_probe,
943 .driver = {
944 .name = "gxbb-clkc",
945 .of_match_table = gxbb_clkc_match_table,
946 },
947 };
948
949 builtin_platform_driver(gxbb_driver);
Linux with added FPC-III support