drivers/clk/meson/meson8b.c

   1 /*
   2  * AmLogic S805 / Meson8b Clock Controller Driver
   3  *
   4  * Copyright (c) 2015 Endless Mobile, Inc.
   5  * Author: Carlo Caione <carlo@endlessm.com>
   6  *
   7  * Copyright (c) 2016 BayLibre, Inc.
   8  * Michael Turquette <mturquette@baylibre.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms and conditions of the GNU General Public License,
  12  * version 2, as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/clk.h>
  24 #include <linux/clk-provider.h>
  25 #include <linux/of_address.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/init.h>
  28
  29 #include "clkc.h"
  30 #include "meson8b.h"
  31
  32 static DEFINE_SPINLOCK(clk_lock);
  33
  34 static const struct pll_rate_table sys_pll_rate_table[] = {
  35         PLL_RATE(312000000, 52, 1, 2),
  36         PLL_RATE(336000000, 56, 1, 2),
  37         PLL_RATE(360000000, 60, 1, 2),
  38         PLL_RATE(384000000, 64, 1, 2),
  39         PLL_RATE(408000000, 68, 1, 2),
  40         PLL_RATE(432000000, 72, 1, 2),
  41         PLL_RATE(456000000, 76, 1, 2),
  42         PLL_RATE(480000000, 80, 1, 2),
  43         PLL_RATE(504000000, 84, 1, 2),
  44         PLL_RATE(528000000, 88, 1, 2),
  45         PLL_RATE(552000000, 92, 1, 2),
  46         PLL_RATE(576000000, 96, 1, 2),
  47         PLL_RATE(600000000, 50, 1, 1),
  48         PLL_RATE(624000000, 52, 1, 1),
  49         PLL_RATE(648000000, 54, 1, 1),
  50         PLL_RATE(672000000, 56, 1, 1),
  51         PLL_RATE(696000000, 58, 1, 1),
  52         PLL_RATE(720000000, 60, 1, 1),
  53         PLL_RATE(744000000, 62, 1, 1),
  54         PLL_RATE(768000000, 64, 1, 1),
  55         PLL_RATE(792000000, 66, 1, 1),
  56         PLL_RATE(816000000, 68, 1, 1),
  57         PLL_RATE(840000000, 70, 1, 1),
  58         PLL_RATE(864000000, 72, 1, 1),
  59         PLL_RATE(888000000, 74, 1, 1),
  60         PLL_RATE(912000000, 76, 1, 1),
  61         PLL_RATE(936000000, 78, 1, 1),
  62         PLL_RATE(960000000, 80, 1, 1),
  63         PLL_RATE(984000000, 82, 1, 1),
  64         PLL_RATE(1008000000, 84, 1, 1),
  65         PLL_RATE(1032000000, 86, 1, 1),
  66         PLL_RATE(1056000000, 88, 1, 1),
  67         PLL_RATE(1080000000, 90, 1, 1),
  68         PLL_RATE(1104000000, 92, 1, 1),
  69         PLL_RATE(1128000000, 94, 1, 1),
  70         PLL_RATE(1152000000, 96, 1, 1),
  71         PLL_RATE(1176000000, 98, 1, 1),
  72         PLL_RATE(1200000000, 50, 1, 0),
  73         PLL_RATE(1224000000, 51, 1, 0),
  74         PLL_RATE(1248000000, 52, 1, 0),
  75         PLL_RATE(1272000000, 53, 1, 0),
  76         PLL_RATE(1296000000, 54, 1, 0),
  77         PLL_RATE(1320000000, 55, 1, 0),
  78         PLL_RATE(1344000000, 56, 1, 0),
  79         PLL_RATE(1368000000, 57, 1, 0),
  80         PLL_RATE(1392000000, 58, 1, 0),
  81         PLL_RATE(1416000000, 59, 1, 0),
  82         PLL_RATE(1440000000, 60, 1, 0),
  83         PLL_RATE(1464000000, 61, 1, 0),
  84         PLL_RATE(1488000000, 62, 1, 0),
  85         PLL_RATE(1512000000, 63, 1, 0),
  86         PLL_RATE(1536000000, 64, 1, 0),
  87         { /* sentinel */ },
  88 };
  89
  90 static const struct clk_div_table cpu_div_table[] = {
  91         { .val = 1, .div = 1 },
  92         { .val = 2, .div = 2 },
  93         { .val = 3, .div = 3 },
  94         { .val = 2, .div = 4 },
  95         { .val = 3, .div = 6 },
  96         { .val = 4, .div = 8 },
  97         { .val = 5, .div = 10 },
  98         { .val = 6, .div = 12 },
  99         { .val = 7, .div = 14 },
 100         { .val = 8, .div = 16 },
 101         { /* sentinel */ },
 102 };
 103
 104 static struct clk_fixed_rate meson8b_xtal = {
 105         .fixed_rate = 24000000,
 106         .hw.init = &(struct clk_init_data){
 107                 .name = "xtal",
 108                 .num_parents = 0,
 109                 .ops = &clk_fixed_rate_ops,
 110         },
 111 };
 112
 113 static struct meson_clk_pll meson8b_fixed_pll = {
 114         .m = {
 115                 .reg_off = HHI_MPLL_CNTL,
 116                 .shift   = 0,
 117                 .width   = 9,
 118         },
 119         .n = {
 120                 .reg_off = HHI_MPLL_CNTL,
 121                 .shift   = 9,
 122                 .width   = 5,
 123         },
 124         .od = {
 125                 .reg_off = HHI_MPLL_CNTL,
 126                 .shift   = 16,
 127                 .width   = 2,
 128         },
 129         .lock = &clk_lock,
 130         .hw.init = &(struct clk_init_data){
 131                 .name = "fixed_pll",
 132                 .ops = &meson_clk_pll_ro_ops,
 133                 .parent_names = (const char *[]){ "xtal" },
 134                 .num_parents = 1,
 135                 .flags = CLK_GET_RATE_NOCACHE,
 136         },
 137 };
 138
 139 static struct meson_clk_pll meson8b_vid_pll = {
 140         .m = {
 141                 .reg_off = HHI_VID_PLL_CNTL,
 142                 .shift   = 0,
 143                 .width   = 9,
 144         },
 145         .n = {
 146                 .reg_off = HHI_VID_PLL_CNTL,
 147                 .shift   = 9,
 148                 .width   = 5,
 149         },
 150         .od = {
 151                 .reg_off = HHI_VID_PLL_CNTL,
 152                 .shift   = 16,
 153                 .width   = 2,
 154         },
 155         .lock = &clk_lock,
 156         .hw.init = &(struct clk_init_data){
 157                 .name = "vid_pll",
 158                 .ops = &meson_clk_pll_ro_ops,
 159                 .parent_names = (const char *[]){ "xtal" },
 160                 .num_parents = 1,
 161                 .flags = CLK_GET_RATE_NOCACHE,
 162         },
 163 };
 164
 165 static struct meson_clk_pll meson8b_sys_pll = {
 166         .m = {
 167                 .reg_off = HHI_SYS_PLL_CNTL,
 168                 .shift   = 0,
 169                 .width   = 9,
 170         },
 171         .n = {
 172                 .reg_off = HHI_SYS_PLL_CNTL,
 173                 .shift   = 9,
 174                 .width   = 5,
 175         },
 176         .od = {
 177                 .reg_off = HHI_SYS_PLL_CNTL,
 178                 .shift   = 16,
 179                 .width   = 2,
 180         },
 181         .rate_table = sys_pll_rate_table,
 182         .rate_count = ARRAY_SIZE(sys_pll_rate_table),
 183         .lock = &clk_lock,
 184         .hw.init = &(struct clk_init_data){
 185                 .name = "sys_pll",
 186                 .ops = &meson_clk_pll_ops,
 187                 .parent_names = (const char *[]){ "xtal" },
 188                 .num_parents = 1,
 189                 .flags = CLK_GET_RATE_NOCACHE,
 190         },
 191 };
 192
 193 static struct clk_fixed_factor meson8b_fclk_div2 = {
 194         .mult = 1,
 195         .div = 2,
 196         .hw.init = &(struct clk_init_data){
 197                 .name = "fclk_div2",
 198                 .ops = &clk_fixed_factor_ops,
 199                 .parent_names = (const char *[]){ "fixed_pll" },
 200                 .num_parents = 1,
 201         },
 202 };
 203
 204 static struct clk_fixed_factor meson8b_fclk_div3 = {
 205         .mult = 1,
 206         .div = 3,
 207         .hw.init = &(struct clk_init_data){
 208                 .name = "fclk_div3",
 209                 .ops = &clk_fixed_factor_ops,
 210                 .parent_names = (const char *[]){ "fixed_pll" },
 211                 .num_parents = 1,
 212         },
 213 };
 214
 215 static struct clk_fixed_factor meson8b_fclk_div4 = {
 216         .mult = 1,
 217         .div = 4,
 218         .hw.init = &(struct clk_init_data){
 219                 .name = "fclk_div4",
 220                 .ops = &clk_fixed_factor_ops,
 221                 .parent_names = (const char *[]){ "fixed_pll" },
 222                 .num_parents = 1,
 223         },
 224 };
 225
 226 static struct clk_fixed_factor meson8b_fclk_div5 = {
 227         .mult = 1,
 228         .div = 5,
 229         .hw.init = &(struct clk_init_data){
 230                 .name = "fclk_div5",
 231                 .ops = &clk_fixed_factor_ops,
 232                 .parent_names = (const char *[]){ "fixed_pll" },
 233                 .num_parents = 1,
 234         },
 235 };
 236
 237 static struct clk_fixed_factor meson8b_fclk_div7 = {
 238         .mult = 1,
 239         .div = 7,
 240         .hw.init = &(struct clk_init_data){
 241                 .name = "fclk_div7",
 242                 .ops = &clk_fixed_factor_ops,
 243                 .parent_names = (const char *[]){ "fixed_pll" },
 244                 .num_parents = 1,
 245         },
 246 };
 247
 248 /*
 249  * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
 250  * post-dividers and should be modeled with their respective PLLs via the
 251  * forthcoming coordinated clock rates feature
 252  */
 253 static struct meson_clk_cpu meson8b_cpu_clk = {
 254         .reg_off = HHI_SYS_CPU_CLK_CNTL1,
 255         .div_table = cpu_div_table,
 256         .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
 257         .hw.init = &(struct clk_init_data){
 258                 .name = "cpu_clk",
 259                 .ops = &meson_clk_cpu_ops,
 260                 .parent_names = (const char *[]){ "sys_pll" },
 261                 .num_parents = 1,
 262         },
 263 };
 264
 265 static u32 mux_table_clk81[]    = { 6, 5, 7 };
 266
 267 struct clk_mux meson8b_mpeg_clk_sel = {
 268         .reg = (void *)HHI_MPEG_CLK_CNTL,
 269         .mask = 0x7,
 270         .shift = 12,
 271         .flags = CLK_MUX_READ_ONLY,
 272         .table = mux_table_clk81,
 273         .lock = &clk_lock,
 274         .hw.init = &(struct clk_init_data){
 275                 .name = "mpeg_clk_sel",
 276                 .ops = &clk_mux_ro_ops,
 277                 /*
 278                  * FIXME bits 14:12 selects from 8 possible parents:
 279                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 280                  * fclk_div4, fclk_div3, fclk_div5
 281                  */
 282                 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
 283                         "fclk_div5" },
 284                 .num_parents = 3,
 285                 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
 286         },
 287 };
 288
 289 struct clk_divider meson8b_mpeg_clk_div = {
 290         .reg = (void *)HHI_MPEG_CLK_CNTL,
 291         .shift = 0,
 292         .width = 7,
 293         .lock = &clk_lock,
 294         .hw.init = &(struct clk_init_data){
 295                 .name = "mpeg_clk_div",
 296                 .ops = &clk_divider_ops,
 297                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
 298                 .num_parents = 1,
 299                 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
 300         },
 301 };
 302
 303 struct clk_gate meson8b_clk81 = {
 304         .reg = (void *)HHI_MPEG_CLK_CNTL,
 305         .bit_idx = 7,
 306         .lock = &clk_lock,
 307         .hw.init = &(struct clk_init_data){
 308                 .name = "clk81",
 309                 .ops = &clk_gate_ops,
 310                 .parent_names = (const char *[]){ "mpeg_clk_div" },
 311                 .num_parents = 1,
 312                 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
 313         },
 314 };
 315
 316 /* Everything Else (EE) domain gates */
 317
 318 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
 319 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
 320 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
 321 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
 322 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
 323 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
 324 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
 325 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
 326 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
 327 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
 328 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
 329 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
 330 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
 331 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
 332 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
 333 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
 334 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
 335 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
 336 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
 337
 338 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
 339 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
 340 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
 341 static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
 342 static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
 343 static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
 344 static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
 345 static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
 346 static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
 347 static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
 348 static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
 349 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
 350 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
 351 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
 352 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
 353 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
 354 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
 355 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
 356 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
 357 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
 358 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
 359 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
 360 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
 361 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
 362 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
 363
 364 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
 365 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
 366 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
 367 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
 368 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
 369 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
 370 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
 371 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
 372 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
 373 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
 374 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
 375 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
 376 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
 377
 378 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
 379 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
 380 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
 381 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
 382 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
 383 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
 384 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
 385 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
 386 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
 387 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
 388 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
 389 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
 390 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
 391 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
 392 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
 393 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
 394
 395 /* Always On (AO) domain gates */
 396
 397 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
 398 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
 399 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
 400 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
 401
 402 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
 403         .hws = {
 404                 [CLKID_XTAL] = &meson8b_xtal.hw,
 405                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
 406                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
 407                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
 408                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
 409                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
 410                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
 411                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
 412                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
 413                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
 414                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
 415                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
 416                 [CLKID_CLK81] = &meson8b_clk81.hw,
 417                 [CLKID_DDR]                 = &meson8b_ddr.hw,
 418                 [CLKID_DOS]                 = &meson8b_dos.hw,
 419                 [CLKID_ISA]                 = &meson8b_isa.hw,
 420                 [CLKID_PL301]               = &meson8b_pl301.hw,
 421                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
 422                 [CLKID_SPICC]               = &meson8b_spicc.hw,
 423                 [CLKID_I2C]                 = &meson8b_i2c.hw,
 424                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
 425                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
 426                 [CLKID_RNG0]                = &meson8b_rng0.hw,
 427                 [CLKID_UART0]               = &meson8b_uart0.hw,
 428                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
 429                 [CLKID_STREAM]              = &meson8b_stream.hw,
 430                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
 431                 [CLKID_SDIO]                = &meson8b_sdio.hw,
 432                 [CLKID_ABUF]                = &meson8b_abuf.hw,
 433                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
 434                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
 435                 [CLKID_SPI]                 = &meson8b_spi.hw,
 436                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
 437                 [CLKID_ETH]                 = &meson8b_eth.hw,
 438                 [CLKID_DEMUX]               = &meson8b_demux.hw,
 439                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
 440                 [CLKID_IEC958]              = &meson8b_iec958.hw,
 441                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
 442                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
 443                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
 444                 [CLKID_MIXER]               = &meson8b_mixer.hw,
 445                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
 446                 [CLKID_ADC]                 = &meson8b_adc.hw,
 447                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
 448                 [CLKID_AIU]                 = &meson8b_aiu.hw,
 449                 [CLKID_UART1]               = &meson8b_uart1.hw,
 450                 [CLKID_G2D]                 = &meson8b_g2d.hw,
 451                 [CLKID_USB0]                = &meson8b_usb0.hw,
 452                 [CLKID_USB1]                = &meson8b_usb1.hw,
 453                 [CLKID_RESET]               = &meson8b_reset.hw,
 454                 [CLKID_NAND]                = &meson8b_nand.hw,
 455                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
 456                 [CLKID_USB]                 = &meson8b_usb.hw,
 457                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
 458                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
 459                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
 460                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
 461                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
 462                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
 463                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
 464                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
 465                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
 466                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
 467                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
 468                 [CLKID_DVIN]                = &meson8b_dvin.hw,
 469                 [CLKID_UART2]               = &meson8b_uart2.hw,
 470                 [CLKID_SANA]                = &meson8b_sana.hw,
 471                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
 472                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
 473                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
 474                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
 475                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
 476                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
 477                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
 478                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
 479                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
 480                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
 481                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
 482                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
 483                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
 484                 [CLKID_RNG1]                = &meson8b_rng1.hw,
 485                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
 486                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
 487                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
 488                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
 489                 [CLKID_EDP]                 = &meson8b_edp.hw,
 490                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
 491                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
 492                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
 493                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
 494         },
 495         .num = CLK_NR_CLKS,
 496 };
 497
 498 static struct meson_clk_pll *const meson8b_clk_plls[] = {
 499         &meson8b_fixed_pll,
 500         &meson8b_vid_pll,
 501         &meson8b_sys_pll,
 502 };
 503
 504 static struct clk_gate *meson8b_clk_gates[] = {
 505         &meson8b_clk81,
 506         &meson8b_ddr,
 507         &meson8b_dos,
 508         &meson8b_isa,
 509         &meson8b_pl301,
 510         &meson8b_periphs,
 511         &meson8b_spicc,
 512         &meson8b_i2c,
 513         &meson8b_sar_adc,
 514         &meson8b_smart_card,
 515         &meson8b_rng0,
 516         &meson8b_uart0,
 517         &meson8b_sdhc,
 518         &meson8b_stream,
 519         &meson8b_async_fifo,
 520         &meson8b_sdio,
 521         &meson8b_abuf,
 522         &meson8b_hiu_iface,
 523         &meson8b_assist_misc,
 524         &meson8b_spi,
 525         &meson8b_i2s_spdif,
 526         &meson8b_eth,
 527         &meson8b_demux,
 528         &meson8b_aiu_glue,
 529         &meson8b_iec958,
 530         &meson8b_i2s_out,
 531         &meson8b_amclk,
 532         &meson8b_aififo2,
 533         &meson8b_mixer,
 534         &meson8b_mixer_iface,
 535         &meson8b_adc,
 536         &meson8b_blkmv,
 537         &meson8b_aiu,
 538         &meson8b_uart1,
 539         &meson8b_g2d,
 540         &meson8b_usb0,
 541         &meson8b_usb1,
 542         &meson8b_reset,
 543         &meson8b_nand,
 544         &meson8b_dos_parser,
 545         &meson8b_usb,
 546         &meson8b_vdin1,
 547         &meson8b_ahb_arb0,
 548         &meson8b_efuse,
 549         &meson8b_boot_rom,
 550         &meson8b_ahb_data_bus,
 551         &meson8b_ahb_ctrl_bus,
 552         &meson8b_hdmi_intr_sync,
 553         &meson8b_hdmi_pclk,
 554         &meson8b_usb1_ddr_bridge,
 555         &meson8b_usb0_ddr_bridge,
 556         &meson8b_mmc_pclk,
 557         &meson8b_dvin,
 558         &meson8b_uart2,
 559         &meson8b_sana,
 560         &meson8b_vpu_intr,
 561         &meson8b_sec_ahb_ahb3_bridge,
 562         &meson8b_clk81_a9,
 563         &meson8b_vclk2_venci0,
 564         &meson8b_vclk2_venci1,
 565         &meson8b_vclk2_vencp0,
 566         &meson8b_vclk2_vencp1,
 567         &meson8b_gclk_venci_int,
 568         &meson8b_gclk_vencp_int,
 569         &meson8b_dac_clk,
 570         &meson8b_aoclk_gate,
 571         &meson8b_iec958_gate,
 572         &meson8b_enc480p,
 573         &meson8b_rng1,
 574         &meson8b_gclk_vencl_int,
 575         &meson8b_vclk2_venclmcc,
 576         &meson8b_vclk2_vencl,
 577         &meson8b_vclk2_other,
 578         &meson8b_edp,
 579         &meson8b_ao_media_cpu,
 580         &meson8b_ao_ahb_sram,
 581         &meson8b_ao_ahb_bus,
 582         &meson8b_ao_iface,
 583 };
 584
 585 static int meson8b_clkc_probe(struct platform_device *pdev)
 586 {
 587         void __iomem *clk_base;
 588         int ret, clkid, i;
 589         struct clk_hw *parent_hw;
 590         struct clk *parent_clk;
 591         struct device *dev = &pdev->dev;
 592
 593         /*  Generic clocks and PLLs */
 594         clk_base = of_iomap(dev->of_node, 1);
 595         if (!clk_base) {
 596                 pr_err("%s: Unable to map clk base\n", __func__);
 597                 return -ENXIO;
 598         }
 599
 600         /* Populate base address for PLLs */
 601         for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
 602                 meson8b_clk_plls[i]->base = clk_base;
 603
 604         /* Populate the base address for CPU clk */
 605         meson8b_cpu_clk.base = clk_base;
 606
 607         /* Populate the base address for the MPEG clks */
 608         meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg;
 609         meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
 610         meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
 611
 612         /* Populate base address for gates */
 613         for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
 614                 meson8b_clk_gates[i]->reg = clk_base +
 615                         (u32)meson8b_clk_gates[i]->reg;
 616
 617         /*
 618          * register all clks
 619          * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
 620          */
 621         for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) {
 622                 /* array might be sparse */
 623                 if (!meson8b_hw_onecell_data.hws[clkid])
 624                         continue;
 625
 626                 /* FIXME convert to devm_clk_register */
 627                 ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
 628                 if (ret)
 629                         goto iounmap;
 630         }
 631
 632         /*
 633          * Register CPU clk notifier
 634          *
 635          * FIXME this is wrong for a lot of reasons. First, the muxes should be
 636          * struct clk_hw objects. Second, we shouldn't program the muxes in
 637          * notifier handlers. The tricky programming sequence will be handled
 638          * by the forthcoming coordinated clock rates mechanism once that
 639          * feature is released.
 640          *
 641          * Furthermore, looking up the parent this way is terrible. At some
 642          * point we will stop allocating a default struct clk when registering
 643          * a new clk_hw, and this hack will no longer work. Releasing the ccr
 644          * feature before that time solves the problem :-)
 645          */
 646         parent_hw = clk_hw_get_parent(&meson8b_cpu_clk.hw);
 647         parent_clk = parent_hw->clk;
 648         ret = clk_notifier_register(parent_clk, &meson8b_cpu_clk.clk_nb);
 649         if (ret) {
 650                 pr_err("%s: failed to register clock notifier for cpu_clk\n",
 651                                 __func__);
 652                 goto iounmap;
 653         }
 654
 655         return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
 656                         &meson8b_hw_onecell_data);
 657
 658 iounmap:
 659         iounmap(clk_base);
 660         return ret;
 661 }
 662
 663 static const struct of_device_id meson8b_clkc_match_table[] = {
 664         { .compatible = "amlogic,meson8b-clkc" },
 665         { }
 666 };
 667
 668 static struct platform_driver meson8b_driver = {
 669         .probe          = meson8b_clkc_probe,
 670         .driver         = {
 671                 .name   = "meson8b-clkc",
 672                 .of_match_table = meson8b_clkc_match_table,
 673         },
 674 };
 675
 676 builtin_platform_driver(meson8b_driver);