drivers/clk/mmp/clk-mmp2.c

   1 /*
   2  * mmp2 clock framework source file
   3  *
   4  * Copyright (C) 2012 Marvell
   5  * Chao Xie <xiechao.mail@gmail.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/io.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/clk/mmp.h>
  20
  21 #include "clk.h"
  22
  23 #define APBC_RTC        0x0
  24 #define APBC_TWSI0      0x4
  25 #define APBC_TWSI1      0x8
  26 #define APBC_TWSI2      0xc
  27 #define APBC_TWSI3      0x10
  28 #define APBC_TWSI4      0x7c
  29 #define APBC_TWSI5      0x80
  30 #define APBC_KPC        0x18
  31 #define APBC_UART0      0x2c
  32 #define APBC_UART1      0x30
  33 #define APBC_UART2      0x34
  34 #define APBC_UART3      0x88
  35 #define APBC_GPIO       0x38
  36 #define APBC_PWM0       0x3c
  37 #define APBC_PWM1       0x40
  38 #define APBC_PWM2       0x44
  39 #define APBC_PWM3       0x48
  40 #define APBC_SSP0       0x50
  41 #define APBC_SSP1       0x54
  42 #define APBC_SSP2       0x58
  43 #define APBC_SSP3       0x5c
  44 #define APMU_SDH0       0x54
  45 #define APMU_SDH1       0x58
  46 #define APMU_SDH2       0xe8
  47 #define APMU_SDH3       0xec
  48 #define APMU_USB        0x5c
  49 #define APMU_DISP0      0x4c
  50 #define APMU_DISP1      0x110
  51 #define APMU_CCIC0      0x50
  52 #define APMU_CCIC1      0xf4
  53 #define MPMU_UART_PLL   0x14
  54
  55 static DEFINE_SPINLOCK(clk_lock);
  56
  57 static struct mmp_clk_factor_masks uart_factor_masks = {
  58         .factor = 2,
  59         .num_mask = 0x1fff,
  60         .den_mask = 0x1fff,
  61         .num_shift = 16,
  62         .den_shift = 0,
  63 };
  64
  65 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
  66         {.num = 8125, .den = 1536},     /*14.745MHZ */
  67         {.num = 3521, .den = 689},      /*19.23MHZ */
  68 };
  69
  70 static const char *uart_parent[] = {"uart_pll", "vctcxo"};
  71 static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
  72 static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
  73 static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
  74 static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
  75
  76 void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
  77                           phys_addr_t apbc_phys)
  78 {
  79         struct clk *clk;
  80         struct clk *vctcxo;
  81         void __iomem *mpmu_base;
  82         void __iomem *apmu_base;
  83         void __iomem *apbc_base;
  84
  85         mpmu_base = ioremap(mpmu_phys, SZ_4K);
  86         if (mpmu_base == NULL) {
  87                 pr_err("error to ioremap MPMU base\n");
  88                 return;
  89         }
  90
  91         apmu_base = ioremap(apmu_phys, SZ_4K);
  92         if (apmu_base == NULL) {
  93                 pr_err("error to ioremap APMU base\n");
  94                 return;
  95         }
  96
  97         apbc_base = ioremap(apbc_phys, SZ_4K);
  98         if (apbc_base == NULL) {
  99                 pr_err("error to ioremap APBC base\n");
 100                 return;
 101         }
 102
 103         clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200);
 104         clk_register_clkdev(clk, "clk32", NULL);
 105
 106         vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000);
 107         clk_register_clkdev(vctcxo, "vctcxo", NULL);
 108
 109         clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000);
 110         clk_register_clkdev(clk, "pll1", NULL);
 111
 112         clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000);
 113         clk_register_clkdev(clk, "usb_pll", NULL);
 114
 115         clk = clk_register_fixed_rate(NULL, "pll2", NULL, 0, 960000000);
 116         clk_register_clkdev(clk, "pll2", NULL);
 117
 118         clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
 119                                 CLK_SET_RATE_PARENT, 1, 2);
 120         clk_register_clkdev(clk, "pll1_2", NULL);
 121
 122         clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
 123                                 CLK_SET_RATE_PARENT, 1, 2);
 124         clk_register_clkdev(clk, "pll1_4", NULL);
 125
 126         clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
 127                                 CLK_SET_RATE_PARENT, 1, 2);
 128         clk_register_clkdev(clk, "pll1_8", NULL);
 129
 130         clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
 131                                 CLK_SET_RATE_PARENT, 1, 2);
 132         clk_register_clkdev(clk, "pll1_16", NULL);
 133
 134         clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
 135                                 CLK_SET_RATE_PARENT, 1, 5);
 136         clk_register_clkdev(clk, "pll1_20", NULL);
 137
 138         clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
 139                                 CLK_SET_RATE_PARENT, 1, 3);
 140         clk_register_clkdev(clk, "pll1_3", NULL);
 141
 142         clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
 143                                 CLK_SET_RATE_PARENT, 1, 2);
 144         clk_register_clkdev(clk, "pll1_6", NULL);
 145
 146         clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
 147                                 CLK_SET_RATE_PARENT, 1, 2);
 148         clk_register_clkdev(clk, "pll1_12", NULL);
 149
 150         clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
 151                                 CLK_SET_RATE_PARENT, 1, 2);
 152         clk_register_clkdev(clk, "pll2_2", NULL);
 153
 154         clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
 155                                 CLK_SET_RATE_PARENT, 1, 2);
 156         clk_register_clkdev(clk, "pll2_4", NULL);
 157
 158         clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
 159                                 CLK_SET_RATE_PARENT, 1, 2);
 160         clk_register_clkdev(clk, "pll2_8", NULL);
 161
 162         clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
 163                                 CLK_SET_RATE_PARENT, 1, 2);
 164         clk_register_clkdev(clk, "pll2_16", NULL);
 165
 166         clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
 167                                 CLK_SET_RATE_PARENT, 1, 3);
 168         clk_register_clkdev(clk, "pll2_3", NULL);
 169
 170         clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
 171                                 CLK_SET_RATE_PARENT, 1, 2);
 172         clk_register_clkdev(clk, "pll2_6", NULL);
 173
 174         clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
 175                                 CLK_SET_RATE_PARENT, 1, 2);
 176         clk_register_clkdev(clk, "pll2_12", NULL);
 177
 178         clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
 179                                 CLK_SET_RATE_PARENT, 1, 2);
 180         clk_register_clkdev(clk, "vctcxo_2", NULL);
 181
 182         clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
 183                                 CLK_SET_RATE_PARENT, 1, 2);
 184         clk_register_clkdev(clk, "vctcxo_4", NULL);
 185
 186         clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
 187                                 mpmu_base + MPMU_UART_PLL,
 188                                 &uart_factor_masks, uart_factor_tbl,
 189                                 ARRAY_SIZE(uart_factor_tbl), &clk_lock);
 190         clk_set_rate(clk, 14745600);
 191         clk_register_clkdev(clk, "uart_pll", NULL);
 192
 193         clk = mmp_clk_register_apbc("twsi0", "vctcxo",
 194                                 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
 195         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
 196
 197         clk = mmp_clk_register_apbc("twsi1", "vctcxo",
 198                                 apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
 199         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
 200
 201         clk = mmp_clk_register_apbc("twsi2", "vctcxo",
 202                                 apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
 203         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
 204
 205         clk = mmp_clk_register_apbc("twsi3", "vctcxo",
 206                                 apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
 207         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
 208
 209         clk = mmp_clk_register_apbc("twsi4", "vctcxo",
 210                                 apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
 211         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
 212
 213         clk = mmp_clk_register_apbc("twsi5", "vctcxo",
 214                                 apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
 215         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
 216
 217         clk = mmp_clk_register_apbc("gpio", "vctcxo",
 218                                 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
 219         clk_register_clkdev(clk, NULL, "mmp2-gpio");
 220
 221         clk = mmp_clk_register_apbc("kpc", "clk32",
 222                                 apbc_base + APBC_KPC, 10, 0, &clk_lock);
 223         clk_register_clkdev(clk, NULL, "pxa27x-keypad");
 224
 225         clk = mmp_clk_register_apbc("rtc", "clk32",
 226                                 apbc_base + APBC_RTC, 10, 0, &clk_lock);
 227         clk_register_clkdev(clk, NULL, "mmp-rtc");
 228
 229         clk = mmp_clk_register_apbc("pwm0", "vctcxo",
 230                                 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
 231         clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
 232
 233         clk = mmp_clk_register_apbc("pwm1", "vctcxo",
 234                                 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
 235         clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
 236
 237         clk = mmp_clk_register_apbc("pwm2", "vctcxo",
 238                                 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
 239         clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
 240
 241         clk = mmp_clk_register_apbc("pwm3", "vctcxo",
 242                                 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
 243         clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
 244
 245         clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
 246                                 ARRAY_SIZE(uart_parent),
 247                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 248                                 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
 249         clk_set_parent(clk, vctcxo);
 250         clk_register_clkdev(clk, "uart_mux.0", NULL);
 251
 252         clk = mmp_clk_register_apbc("uart0", "uart0_mux",
 253                                 apbc_base + APBC_UART0, 10, 0, &clk_lock);
 254         clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
 255
 256         clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
 257                                 ARRAY_SIZE(uart_parent),
 258                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 259                                 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
 260         clk_set_parent(clk, vctcxo);
 261         clk_register_clkdev(clk, "uart_mux.1", NULL);
 262
 263         clk = mmp_clk_register_apbc("uart1", "uart1_mux",
 264                                 apbc_base + APBC_UART1, 10, 0, &clk_lock);
 265         clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
 266
 267         clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
 268                                 ARRAY_SIZE(uart_parent),
 269                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 270                                 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
 271         clk_set_parent(clk, vctcxo);
 272         clk_register_clkdev(clk, "uart_mux.2", NULL);
 273
 274         clk = mmp_clk_register_apbc("uart2", "uart2_mux",
 275                                 apbc_base + APBC_UART2, 10, 0, &clk_lock);
 276         clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
 277
 278         clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
 279                                 ARRAY_SIZE(uart_parent),
 280                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 281                                 apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
 282         clk_set_parent(clk, vctcxo);
 283         clk_register_clkdev(clk, "uart_mux.3", NULL);
 284
 285         clk = mmp_clk_register_apbc("uart3", "uart3_mux",
 286                                 apbc_base + APBC_UART3, 10, 0, &clk_lock);
 287         clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
 288
 289         clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
 290                                 ARRAY_SIZE(ssp_parent),
 291                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 292                                 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
 293         clk_register_clkdev(clk, "uart_mux.0", NULL);
 294
 295         clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
 296                                 apbc_base + APBC_SSP0, 10, 0, &clk_lock);
 297         clk_register_clkdev(clk, NULL, "mmp-ssp.0");
 298
 299         clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
 300                                 ARRAY_SIZE(ssp_parent),
 301                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 302                                 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
 303         clk_register_clkdev(clk, "ssp_mux.1", NULL);
 304
 305         clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
 306                                 apbc_base + APBC_SSP1, 10, 0, &clk_lock);
 307         clk_register_clkdev(clk, NULL, "mmp-ssp.1");
 308
 309         clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
 310                                 ARRAY_SIZE(ssp_parent),
 311                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 312                                 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
 313         clk_register_clkdev(clk, "ssp_mux.2", NULL);
 314
 315         clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
 316                                 apbc_base + APBC_SSP2, 10, 0, &clk_lock);
 317         clk_register_clkdev(clk, NULL, "mmp-ssp.2");
 318
 319         clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
 320                                 ARRAY_SIZE(ssp_parent),
 321                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 322                                 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
 323         clk_register_clkdev(clk, "ssp_mux.3", NULL);
 324
 325         clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
 326                                 apbc_base + APBC_SSP3, 10, 0, &clk_lock);
 327         clk_register_clkdev(clk, NULL, "mmp-ssp.3");
 328
 329         clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
 330                                 ARRAY_SIZE(sdh_parent),
 331                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 332                                 apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
 333         clk_register_clkdev(clk, "sdh_mux", NULL);
 334
 335         clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
 336                                 CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
 337                                 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 338         clk_register_clkdev(clk, "sdh_div", NULL);
 339
 340         clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
 341                                 0x1b, &clk_lock);
 342         clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
 343
 344         clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
 345                                 0x1b, &clk_lock);
 346         clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
 347
 348         clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
 349                                 0x1b, &clk_lock);
 350         clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
 351
 352         clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
 353                                 0x1b, &clk_lock);
 354         clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
 355
 356         clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
 357                                 0x9, &clk_lock);
 358         clk_register_clkdev(clk, "usb_clk", NULL);
 359
 360         clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
 361                                 ARRAY_SIZE(disp_parent),
 362                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 363                                 apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
 364         clk_register_clkdev(clk, "disp_mux.0", NULL);
 365
 366         clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
 367                                 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
 368                                 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 369         clk_register_clkdev(clk, "disp_div.0", NULL);
 370
 371         clk = mmp_clk_register_apmu("disp0", "disp0_div",
 372                                 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
 373         clk_register_clkdev(clk, NULL, "mmp-disp.0");
 374
 375         clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
 376                                 apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
 377         clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
 378
 379         clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
 380                                 apmu_base + APMU_DISP0, 0x1024, &clk_lock);
 381         clk_register_clkdev(clk, "disp_sphy.0", NULL);
 382
 383         clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
 384                                 ARRAY_SIZE(disp_parent),
 385                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 386                                 apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
 387         clk_register_clkdev(clk, "disp_mux.1", NULL);
 388
 389         clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
 390                                 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
 391                                 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 392         clk_register_clkdev(clk, "disp_div.1", NULL);
 393
 394         clk = mmp_clk_register_apmu("disp1", "disp1_div",
 395                                 apmu_base + APMU_DISP1, 0x1b, &clk_lock);
 396         clk_register_clkdev(clk, NULL, "mmp-disp.1");
 397
 398         clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
 399                                 apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
 400         clk_register_clkdev(clk, "ccic_arbiter", NULL);
 401
 402         clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
 403                                 ARRAY_SIZE(ccic_parent),
 404                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 405                                 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
 406         clk_register_clkdev(clk, "ccic_mux.0", NULL);
 407
 408         clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
 409                                 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
 410                                 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 411         clk_register_clkdev(clk, "ccic_div.0", NULL);
 412
 413         clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
 414                                 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
 415         clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
 416
 417         clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
 418                                 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
 419         clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
 420
 421         clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
 422                                 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
 423                                 10, 5, 0, &clk_lock);
 424         clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
 425
 426         clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
 427                                 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
 428         clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
 429
 430         clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
 431                                 ARRAY_SIZE(ccic_parent),
 432                                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 433                                 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
 434         clk_register_clkdev(clk, "ccic_mux.1", NULL);
 435
 436         clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
 437                                 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
 438                                 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 439         clk_register_clkdev(clk, "ccic_div.1", NULL);
 440
 441         clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
 442                                 apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
 443         clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
 444
 445         clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
 446                                 apmu_base + APMU_CCIC1, 0x24, &clk_lock);
 447         clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
 448
 449         clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
 450                                 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
 451                                 10, 5, 0, &clk_lock);
 452         clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
 453
 454         clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
 455                                 apmu_base + APMU_CCIC1, 0x300, &clk_lock);
 456         clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
 457 }