drivers/clk/qcom/gcc-ipq4019.c

   1 /*
   2  * Copyright (c) 2015 The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/err.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/regmap.h>
  22 #include <linux/reset-controller.h>
  23
  24 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
  25
  26 #include "common.h"
  27 #include "clk-regmap.h"
  28 #include "clk-rcg.h"
  29 #include "clk-branch.h"
  30 #include "reset.h"
  31
  32 enum {
  33         P_XO,
  34         P_FEPLL200,
  35         P_FEPLL500,
  36         P_DDRPLL,
  37         P_FEPLLWCSS2G,
  38         P_FEPLLWCSS5G,
  39         P_FEPLL125DLY,
  40         P_DDRPLLAPSS,
  41 };
  42
  43 static struct parent_map gcc_xo_200_500_map[] = {
  44         { P_XO, 0 },
  45         { P_FEPLL200, 1 },
  46         { P_FEPLL500, 2 },
  47 };
  48
  49 static const char * const gcc_xo_200_500[] = {
  50         "xo",
  51         "fepll200",
  52         "fepll500",
  53 };
  54
  55 static struct parent_map gcc_xo_200_map[] = {
  56         {  P_XO, 0 },
  57         {  P_FEPLL200, 1 },
  58 };
  59
  60 static const char * const gcc_xo_200[] = {
  61         "xo",
  62         "fepll200",
  63 };
  64
  65 static struct parent_map gcc_xo_200_spi_map[] = {
  66         {  P_XO, 0 },
  67         {  P_FEPLL200, 2 },
  68 };
  69
  70 static const char * const gcc_xo_200_spi[] = {
  71         "xo",
  72         "fepll200",
  73 };
  74
  75 static struct parent_map gcc_xo_sdcc1_500_map[] = {
  76         {  P_XO, 0 },
  77         {  P_DDRPLL, 1 },
  78         {  P_FEPLL500, 2 },
  79 };
  80
  81 static const char * const gcc_xo_sdcc1_500[] = {
  82         "xo",
  83         "ddrpll",
  84         "fepll500",
  85 };
  86
  87 static struct parent_map gcc_xo_wcss2g_map[] = {
  88         {  P_XO, 0 },
  89         {  P_FEPLLWCSS2G, 1 },
  90 };
  91
  92 static const char * const gcc_xo_wcss2g[] = {
  93         "xo",
  94         "fepllwcss2g",
  95 };
  96
  97 static struct parent_map gcc_xo_wcss5g_map[] = {
  98         {  P_XO, 0 },
  99         {  P_FEPLLWCSS5G, 1 },
 100 };
 101
 102 static const char * const gcc_xo_wcss5g[] = {
 103         "xo",
 104         "fepllwcss5g",
 105 };
 106
 107 static struct parent_map gcc_xo_125_dly_map[] = {
 108         {  P_XO, 0 },
 109         {  P_FEPLL125DLY, 1 },
 110 };
 111
 112 static const char * const gcc_xo_125_dly[] = {
 113         "xo",
 114         "fepll125dly",
 115 };
 116
 117 static struct parent_map gcc_xo_ddr_500_200_map[] = {
 118         {  P_XO, 0 },
 119         {  P_FEPLL200, 3 },
 120         {  P_FEPLL500, 2 },
 121         {  P_DDRPLLAPSS, 1 },
 122 };
 123
 124 static const char * const gcc_xo_ddr_500_200[] = {
 125         "xo",
 126         "fepll200",
 127         "fepll500",
 128         "ddrpllapss",
 129 };
 130
 131 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 132
 133 static const struct freq_tbl ftbl_gcc_audio_pwm_clk[] = {
 134         F(48000000, P_XO, 1, 0, 0),
 135         F(200000000, P_FEPLL200, 1, 0, 0),
 136         { }
 137 };
 138
 139 static struct clk_rcg2 audio_clk_src = {
 140         .cmd_rcgr = 0x1b000,
 141         .hid_width = 5,
 142         .parent_map = gcc_xo_200_map,
 143         .freq_tbl = ftbl_gcc_audio_pwm_clk,
 144         .clkr.hw.init = &(struct clk_init_data){
 145                 .name = "audio_clk_src",
 146                 .parent_names = gcc_xo_200,
 147                 .num_parents = 2,
 148                 .ops = &clk_rcg2_ops,
 149
 150         },
 151 };
 152
 153 static struct clk_branch gcc_audio_ahb_clk = {
 154         .halt_reg = 0x1b010,
 155         .clkr = {
 156                 .enable_reg = 0x1b010,
 157                 .enable_mask = BIT(0),
 158                 .hw.init = &(struct clk_init_data){
 159                         .name = "gcc_audio_ahb_clk",
 160                         .parent_names = (const char *[]){
 161                                 "pcnoc_clk_src",
 162                         },
 163                         .flags = CLK_SET_RATE_PARENT,
 164                         .num_parents = 1,
 165                         .ops = &clk_branch2_ops,
 166                 },
 167         },
 168 };
 169
 170 static struct clk_branch gcc_audio_pwm_clk = {
 171         .halt_reg = 0x1b00C,
 172         .clkr = {
 173                 .enable_reg = 0x1b00C,
 174                 .enable_mask = BIT(0),
 175                 .hw.init = &(struct clk_init_data){
 176                         .name = "gcc_audio_pwm_clk",
 177                         .parent_names = (const char *[]){
 178                                 "audio_clk_src",
 179                         },
 180                         .flags = CLK_SET_RATE_PARENT,
 181                         .num_parents = 1,
 182                         .ops = &clk_branch2_ops,
 183                 },
 184         },
 185 };
 186
 187 static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_i2c_apps_clk[] = {
 188         F(19050000, P_FEPLL200, 10.5, 1, 1),
 189         { }
 190 };
 191
 192 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 193         .cmd_rcgr = 0x200c,
 194         .hid_width = 5,
 195         .parent_map = gcc_xo_200_map,
 196         .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk,
 197         .clkr.hw.init = &(struct clk_init_data){
 198                 .name = "blsp1_qup1_i2c_apps_clk_src",
 199                 .parent_names = gcc_xo_200,
 200                 .num_parents = 2,
 201                 .ops = &clk_rcg2_ops,
 202         },
 203 };
 204
 205 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
 206         .halt_reg = 0x2008,
 207         .clkr = {
 208                 .enable_reg = 0x2008,
 209                 .enable_mask = BIT(0),
 210                 .hw.init = &(struct clk_init_data){
 211                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
 212                         .parent_names = (const char *[]){
 213                                 "blsp1_qup1_i2c_apps_clk_src",
 214                         },
 215                         .num_parents = 1,
 216                         .ops = &clk_branch2_ops,
 217                         .flags = CLK_SET_RATE_PARENT,
 218                 },
 219         },
 220 };
 221
 222 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 223         .cmd_rcgr = 0x3000,
 224         .hid_width = 5,
 225         .parent_map = gcc_xo_200_map,
 226         .freq_tbl = ftbl_gcc_blsp1_qup1_2_i2c_apps_clk,
 227         .clkr.hw.init = &(struct clk_init_data){
 228                 .name = "blsp1_qup2_i2c_apps_clk_src",
 229                 .parent_names = gcc_xo_200,
 230                 .num_parents = 2,
 231                 .ops = &clk_rcg2_ops,
 232         },
 233 };
 234
 235 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
 236         .halt_reg = 0x3010,
 237         .clkr = {
 238                 .enable_reg = 0x3010,
 239                 .enable_mask = BIT(0),
 240                 .hw.init = &(struct clk_init_data){
 241                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
 242                         .parent_names = (const char *[]){
 243                                 "blsp1_qup2_i2c_apps_clk_src",
 244                         },
 245                         .num_parents = 1,
 246                         .ops = &clk_branch2_ops,
 247                         .flags = CLK_SET_RATE_PARENT,
 248                 },
 249         },
 250 };
 251
 252 static const struct freq_tbl ftbl_gcc_blsp1_qup1_2_spi_apps_clk[] = {
 253         F(960000, P_XO, 12, 1, 4),
 254         F(4800000, P_XO, 1, 1, 10),
 255         F(9600000, P_XO, 1, 1, 5),
 256         F(15000000, P_XO, 1, 1, 3),
 257         F(19200000, P_XO, 1, 2, 5),
 258         F(24000000, P_XO, 1, 1, 2),
 259         F(48000000, P_XO, 1, 0, 0),
 260         { }
 261 };
 262
 263 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 264         .cmd_rcgr = 0x2024,
 265         .mnd_width = 8,
 266         .hid_width = 5,
 267         .parent_map = gcc_xo_200_spi_map,
 268         .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk,
 269         .clkr.hw.init = &(struct clk_init_data){
 270                 .name = "blsp1_qup1_spi_apps_clk_src",
 271                 .parent_names = gcc_xo_200_spi,
 272                 .num_parents = 2,
 273                 .ops = &clk_rcg2_ops,
 274         },
 275 };
 276
 277 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
 278         .halt_reg = 0x2004,
 279         .clkr = {
 280                 .enable_reg = 0x2004,
 281                 .enable_mask = BIT(0),
 282                 .hw.init = &(struct clk_init_data){
 283                         .name = "gcc_blsp1_qup1_spi_apps_clk",
 284                         .parent_names = (const char *[]){
 285                                 "blsp1_qup1_spi_apps_clk_src",
 286                         },
 287                         .num_parents = 1,
 288                         .ops = &clk_branch2_ops,
 289                         .flags = CLK_SET_RATE_PARENT,
 290                 },
 291         },
 292 };
 293
 294 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 295         .cmd_rcgr = 0x3014,
 296         .mnd_width = 8,
 297         .hid_width = 5,
 298         .freq_tbl = ftbl_gcc_blsp1_qup1_2_spi_apps_clk,
 299         .parent_map = gcc_xo_200_spi_map,
 300         .clkr.hw.init = &(struct clk_init_data){
 301                 .name = "blsp1_qup2_spi_apps_clk_src",
 302                 .parent_names = gcc_xo_200_spi,
 303                 .num_parents = 2,
 304                 .ops = &clk_rcg2_ops,
 305         },
 306 };
 307
 308 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
 309         .halt_reg = 0x300c,
 310         .clkr = {
 311                 .enable_reg = 0x300c,
 312                 .enable_mask = BIT(0),
 313                 .hw.init = &(struct clk_init_data){
 314                         .name = "gcc_blsp1_qup2_spi_apps_clk",
 315                         .parent_names = (const char *[]){
 316                                 "blsp1_qup2_spi_apps_clk_src",
 317                         },
 318                         .num_parents = 1,
 319                         .ops = &clk_branch2_ops,
 320                         .flags = CLK_SET_RATE_PARENT,
 321                 },
 322         },
 323 };
 324
 325 static const struct freq_tbl ftbl_gcc_blsp1_uart1_2_apps_clk[] = {
 326         F(1843200, P_FEPLL200, 1, 144, 15625),
 327         F(3686400, P_FEPLL200, 1, 288, 15625),
 328         F(7372800, P_FEPLL200, 1, 576, 15625),
 329         F(14745600, P_FEPLL200, 1, 1152, 15625),
 330         F(16000000, P_FEPLL200, 1, 2, 25),
 331         F(24000000, P_XO, 1, 1, 2),
 332         F(32000000, P_FEPLL200, 1, 4, 25),
 333         F(40000000, P_FEPLL200, 1, 1, 5),
 334         F(46400000, P_FEPLL200, 1, 29, 125),
 335         F(48000000, P_XO, 1, 0, 0),
 336         { }
 337 };
 338
 339 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 340         .cmd_rcgr = 0x2044,
 341         .mnd_width = 16,
 342         .hid_width = 5,
 343         .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk,
 344         .parent_map = gcc_xo_200_spi_map,
 345         .clkr.hw.init = &(struct clk_init_data){
 346                 .name = "blsp1_uart1_apps_clk_src",
 347                 .parent_names = gcc_xo_200_spi,
 348                 .num_parents = 2,
 349                 .ops = &clk_rcg2_ops,
 350         },
 351 };
 352
 353 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
 354         .halt_reg = 0x203c,
 355         .clkr = {
 356                 .enable_reg = 0x203c,
 357                 .enable_mask = BIT(0),
 358                 .hw.init = &(struct clk_init_data){
 359                         .name = "gcc_blsp1_uart1_apps_clk",
 360                         .parent_names = (const char *[]){
 361                                 "blsp1_uart1_apps_clk_src",
 362                         },
 363                         .flags = CLK_SET_RATE_PARENT,
 364                         .num_parents = 1,
 365                         .ops = &clk_branch2_ops,
 366                 },
 367         },
 368 };
 369
 370 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 371         .cmd_rcgr = 0x3034,
 372         .mnd_width = 16,
 373         .hid_width = 5,
 374         .freq_tbl = ftbl_gcc_blsp1_uart1_2_apps_clk,
 375         .parent_map = gcc_xo_200_spi_map,
 376         .clkr.hw.init = &(struct clk_init_data){
 377                 .name = "blsp1_uart2_apps_clk_src",
 378                 .parent_names = gcc_xo_200_spi,
 379                 .num_parents = 2,
 380                 .ops = &clk_rcg2_ops,
 381         },
 382 };
 383
 384 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
 385         .halt_reg = 0x302c,
 386         .clkr = {
 387                 .enable_reg = 0x302c,
 388                 .enable_mask = BIT(0),
 389                 .hw.init = &(struct clk_init_data){
 390                         .name = "gcc_blsp1_uart2_apps_clk",
 391                         .parent_names = (const char *[]){
 392                                 "blsp1_uart2_apps_clk_src",
 393                         },
 394                         .num_parents = 1,
 395                         .ops = &clk_branch2_ops,
 396                         .flags = CLK_SET_RATE_PARENT,
 397                 },
 398         },
 399 };
 400
 401 static const struct freq_tbl ftbl_gcc_gp_clk[] = {
 402         F(1250000,  P_FEPLL200, 1, 16, 0),
 403         F(2500000,  P_FEPLL200, 1,  8, 0),
 404         F(5000000,  P_FEPLL200, 1,  4, 0),
 405         { }
 406 };
 407
 408 static struct clk_rcg2 gp1_clk_src = {
 409         .cmd_rcgr = 0x8004,
 410         .mnd_width = 8,
 411         .hid_width = 5,
 412         .freq_tbl = ftbl_gcc_gp_clk,
 413         .parent_map = gcc_xo_200_map,
 414         .clkr.hw.init = &(struct clk_init_data){
 415                 .name = "gp1_clk_src",
 416                 .parent_names = gcc_xo_200,
 417                 .num_parents = 2,
 418                 .ops = &clk_rcg2_ops,
 419         },
 420 };
 421
 422 static struct clk_branch gcc_gp1_clk = {
 423         .halt_reg = 0x8000,
 424         .clkr = {
 425                 .enable_reg = 0x8000,
 426                 .enable_mask = BIT(0),
 427                 .hw.init = &(struct clk_init_data){
 428                         .name = "gcc_gp1_clk",
 429                         .parent_names = (const char *[]){
 430                                 "gp1_clk_src",
 431                         },
 432                         .num_parents = 1,
 433                         .ops = &clk_branch2_ops,
 434                         .flags = CLK_SET_RATE_PARENT,
 435                 },
 436         },
 437 };
 438
 439 static struct clk_rcg2 gp2_clk_src = {
 440         .cmd_rcgr = 0x9004,
 441         .mnd_width = 8,
 442         .hid_width = 5,
 443         .freq_tbl = ftbl_gcc_gp_clk,
 444         .parent_map = gcc_xo_200_map,
 445         .clkr.hw.init = &(struct clk_init_data){
 446                 .name = "gp2_clk_src",
 447                 .parent_names = gcc_xo_200,
 448                 .num_parents = 2,
 449                 .ops = &clk_rcg2_ops,
 450         },
 451 };
 452
 453 static struct clk_branch gcc_gp2_clk = {
 454         .halt_reg = 0x9000,
 455         .clkr = {
 456                 .enable_reg = 0x9000,
 457                 .enable_mask = BIT(0),
 458                 .hw.init = &(struct clk_init_data){
 459                         .name = "gcc_gp2_clk",
 460                         .parent_names = (const char *[]){
 461                                 "gp2_clk_src",
 462                         },
 463                         .num_parents = 1,
 464                         .ops = &clk_branch2_ops,
 465                         .flags = CLK_SET_RATE_PARENT,
 466                 },
 467         },
 468 };
 469
 470 static struct clk_rcg2 gp3_clk_src = {
 471         .cmd_rcgr = 0xa004,
 472         .mnd_width = 8,
 473         .hid_width = 5,
 474         .freq_tbl = ftbl_gcc_gp_clk,
 475         .parent_map = gcc_xo_200_map,
 476         .clkr.hw.init = &(struct clk_init_data){
 477                 .name = "gp3_clk_src",
 478                 .parent_names = gcc_xo_200,
 479                 .num_parents = 2,
 480                 .ops = &clk_rcg2_ops,
 481         },
 482 };
 483
 484 static struct clk_branch gcc_gp3_clk = {
 485         .halt_reg = 0xa000,
 486         .clkr = {
 487                 .enable_reg = 0xa000,
 488                 .enable_mask = BIT(0),
 489                 .hw.init = &(struct clk_init_data){
 490                         .name = "gcc_gp3_clk",
 491                         .parent_names = (const char *[]){
 492                                 "gp3_clk_src",
 493                         },
 494                         .num_parents = 1,
 495                         .ops = &clk_branch2_ops,
 496                         .flags = CLK_SET_RATE_PARENT,
 497                 },
 498         },
 499 };
 500
 501 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
 502         F(144000,    P_XO,                      1,  3, 240),
 503         F(400000,    P_XO,                      1,  1, 0),
 504         F(20000000,  P_FEPLL500,                1,  1, 25),
 505         F(25000000,  P_FEPLL500,                1,  1, 20),
 506         F(50000000,  P_FEPLL500,                1,  1, 10),
 507         F(100000000, P_FEPLL500,                1,  1, 5),
 508         F(193000000, P_DDRPLL,          1,  0, 0),
 509         { }
 510 };
 511
 512 static struct clk_rcg2  sdcc1_apps_clk_src = {
 513         .cmd_rcgr = 0x18004,
 514         .hid_width = 5,
 515         .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
 516         .parent_map = gcc_xo_sdcc1_500_map,
 517         .clkr.hw.init = &(struct clk_init_data){
 518                 .name = "sdcc1_apps_clk_src",
 519                 .parent_names = gcc_xo_sdcc1_500,
 520                 .num_parents = 3,
 521                 .ops = &clk_rcg2_ops,
 522                 .flags = CLK_SET_RATE_PARENT,
 523         },
 524 };
 525
 526 static const struct freq_tbl ftbl_gcc_apps_clk[] = {
 527         F(48000000, P_XO,          1, 0, 0),
 528         F(200000000, P_FEPLL200,   1, 0, 0),
 529         F(500000000, P_FEPLL500,   1, 0, 0),
 530         F(626000000, P_DDRPLLAPSS, 1, 0, 0),
 531         { }
 532 };
 533
 534 static struct clk_rcg2 apps_clk_src = {
 535         .cmd_rcgr = 0x1900c,
 536         .hid_width = 5,
 537         .freq_tbl = ftbl_gcc_apps_clk,
 538         .parent_map = gcc_xo_ddr_500_200_map,
 539         .clkr.hw.init = &(struct clk_init_data){
 540                 .name = "apps_clk_src",
 541                 .parent_names = gcc_xo_ddr_500_200,
 542                 .num_parents = 4,
 543                 .ops = &clk_rcg2_ops,
 544         },
 545 };
 546
 547 static const struct freq_tbl ftbl_gcc_apps_ahb_clk[] = {
 548         F(48000000, P_XO,          1, 0, 0),
 549         F(100000000, P_FEPLL200,   2, 0, 0),
 550         { }
 551 };
 552
 553 static struct clk_rcg2 apps_ahb_clk_src = {
 554         .cmd_rcgr = 0x19014,
 555         .hid_width = 5,
 556         .parent_map = gcc_xo_200_500_map,
 557         .freq_tbl = ftbl_gcc_apps_ahb_clk,
 558         .clkr.hw.init = &(struct clk_init_data){
 559                 .name = "apps_ahb_clk_src",
 560                 .parent_names = gcc_xo_200_500,
 561                 .num_parents = 3,
 562                 .ops = &clk_rcg2_ops,
 563         },
 564 };
 565
 566 static struct clk_branch gcc_apss_ahb_clk = {
 567         .halt_reg = 0x19004,
 568         .halt_check = BRANCH_HALT_VOTED,
 569         .clkr = {
 570                 .enable_reg = 0x6000,
 571                 .enable_mask = BIT(14),
 572                 .hw.init = &(struct clk_init_data){
 573                         .name = "gcc_apss_ahb_clk",
 574                         .parent_names = (const char *[]){
 575                                 "apps_ahb_clk_src",
 576                         },
 577                         .num_parents = 1,
 578                         .ops = &clk_branch2_ops,
 579                         .flags = CLK_SET_RATE_PARENT,
 580                 },
 581         },
 582 };
 583
 584 static struct clk_branch gcc_blsp1_ahb_clk = {
 585         .halt_reg = 0x1008,
 586         .halt_check = BRANCH_HALT_VOTED,
 587         .clkr = {
 588                 .enable_reg = 0x6000,
 589                 .enable_mask = BIT(10),
 590                 .hw.init = &(struct clk_init_data){
 591                         .name = "gcc_blsp1_ahb_clk",
 592                         .parent_names = (const char *[]){
 593                                 "pcnoc_clk_src",
 594                         },
 595                         .num_parents = 1,
 596                         .ops = &clk_branch2_ops,
 597                 },
 598         },
 599 };
 600
 601 static struct clk_branch gcc_dcd_xo_clk = {
 602         .halt_reg = 0x2103c,
 603         .clkr = {
 604                 .enable_reg = 0x2103c,
 605                 .enable_mask = BIT(0),
 606                 .hw.init = &(struct clk_init_data){
 607                         .name = "gcc_dcd_xo_clk",
 608                         .parent_names = (const char *[]){
 609                                 "xo",
 610                         },
 611                         .num_parents = 1,
 612                         .ops = &clk_branch2_ops,
 613                 },
 614         },
 615 };
 616
 617 static struct clk_branch gcc_boot_rom_ahb_clk = {
 618         .halt_reg = 0x1300c,
 619         .clkr = {
 620                 .enable_reg = 0x1300c,
 621                 .enable_mask = BIT(0),
 622                 .hw.init = &(struct clk_init_data){
 623                         .name = "gcc_boot_rom_ahb_clk",
 624                         .parent_names = (const char *[]){
 625                                 "pcnoc_clk_src",
 626                         },
 627                         .num_parents = 1,
 628                         .ops = &clk_branch2_ops,
 629                         .flags = CLK_SET_RATE_PARENT,
 630                 },
 631         },
 632 };
 633
 634 static struct clk_branch gcc_crypto_ahb_clk = {
 635         .halt_reg = 0x16024,
 636         .halt_check = BRANCH_HALT_VOTED,
 637         .clkr = {
 638                 .enable_reg = 0x6000,
 639                 .enable_mask = BIT(0),
 640                 .hw.init = &(struct clk_init_data){
 641                         .name = "gcc_crypto_ahb_clk",
 642                         .parent_names = (const char *[]){
 643                                 "pcnoc_clk_src",
 644                         },
 645                         .num_parents = 1,
 646                         .ops = &clk_branch2_ops,
 647                 },
 648         },
 649 };
 650
 651 static struct clk_branch gcc_crypto_axi_clk = {
 652         .halt_reg = 0x16020,
 653         .halt_check = BRANCH_HALT_VOTED,
 654         .clkr = {
 655                 .enable_reg = 0x6000,
 656                 .enable_mask = BIT(1),
 657                 .hw.init = &(struct clk_init_data){
 658                         .name = "gcc_crypto_axi_clk",
 659                         .parent_names = (const char *[]){
 660                                 "fepll125",
 661                         },
 662                         .num_parents = 1,
 663                         .ops = &clk_branch2_ops,
 664                 },
 665         },
 666 };
 667
 668 static struct clk_branch gcc_crypto_clk = {
 669         .halt_reg = 0x1601c,
 670         .halt_check = BRANCH_HALT_VOTED,
 671         .clkr = {
 672                 .enable_reg = 0x6000,
 673                 .enable_mask = BIT(2),
 674                 .hw.init = &(struct clk_init_data){
 675                         .name = "gcc_crypto_clk",
 676                         .parent_names = (const char *[]){
 677                                 "fepll125",
 678                         },
 679                         .num_parents = 1,
 680                         .ops = &clk_branch2_ops,
 681                 },
 682         },
 683 };
 684
 685 static struct clk_branch gcc_ess_clk = {
 686         .halt_reg = 0x12010,
 687         .clkr = {
 688                 .enable_reg = 0x12010,
 689                 .enable_mask = BIT(0),
 690                 .hw.init = &(struct clk_init_data){
 691                         .name = "gcc_ess_clk",
 692                         .parent_names = (const char *[]){
 693                                 "fephy_125m_dly_clk_src",
 694                         },
 695                         .num_parents = 1,
 696                         .ops = &clk_branch2_ops,
 697                         .flags = CLK_SET_RATE_PARENT,
 698                 },
 699         },
 700 };
 701
 702 static struct clk_branch gcc_imem_axi_clk = {
 703         .halt_reg = 0xe004,
 704         .halt_check = BRANCH_HALT_VOTED,
 705         .clkr = {
 706                 .enable_reg = 0x6000,
 707                 .enable_mask = BIT(17),
 708                 .hw.init = &(struct clk_init_data){
 709                         .name = "gcc_imem_axi_clk",
 710                         .parent_names = (const char *[]){
 711                                 "fepll200",
 712                         },
 713                         .num_parents = 1,
 714                         .ops = &clk_branch2_ops,
 715                 },
 716         },
 717 };
 718
 719 static struct clk_branch gcc_imem_cfg_ahb_clk = {
 720         .halt_reg = 0xe008,
 721         .clkr = {
 722                 .enable_reg = 0xe008,
 723                 .enable_mask = BIT(0),
 724                 .hw.init = &(struct clk_init_data){
 725                         .name = "gcc_imem_cfg_ahb_clk",
 726                         .parent_names = (const char *[]){
 727                                 "pcnoc_clk_src",
 728                         },
 729                         .num_parents = 1,
 730                         .ops = &clk_branch2_ops,
 731                 },
 732         },
 733 };
 734
 735 static struct clk_branch gcc_pcie_ahb_clk = {
 736         .halt_reg = 0x1d00c,
 737         .clkr = {
 738                 .enable_reg = 0x1d00c,
 739                 .enable_mask = BIT(0),
 740                 .hw.init = &(struct clk_init_data){
 741                         .name = "gcc_pcie_ahb_clk",
 742                         .parent_names = (const char *[]){
 743                                 "pcnoc_clk_src",
 744                         },
 745                         .num_parents = 1,
 746                         .ops = &clk_branch2_ops,
 747                 },
 748         },
 749 };
 750
 751 static struct clk_branch gcc_pcie_axi_m_clk = {
 752         .halt_reg = 0x1d004,
 753         .clkr = {
 754                 .enable_reg = 0x1d004,
 755                 .enable_mask = BIT(0),
 756                 .hw.init = &(struct clk_init_data){
 757                         .name = "gcc_pcie_axi_m_clk",
 758                         .parent_names = (const char *[]){
 759                                 "fepll200",
 760                         },
 761                         .num_parents = 1,
 762                         .ops = &clk_branch2_ops,
 763                 },
 764         },
 765 };
 766
 767 static struct clk_branch gcc_pcie_axi_s_clk = {
 768         .halt_reg = 0x1d008,
 769         .clkr = {
 770                 .enable_reg = 0x1d008,
 771                 .enable_mask = BIT(0),
 772                 .hw.init = &(struct clk_init_data){
 773                         .name = "gcc_pcie_axi_s_clk",
 774                         .parent_names = (const char *[]){
 775                                 "fepll200",
 776                         },
 777                         .num_parents = 1,
 778                         .ops = &clk_branch2_ops,
 779                 },
 780         },
 781 };
 782
 783 static struct clk_branch gcc_prng_ahb_clk = {
 784         .halt_reg = 0x13004,
 785         .halt_check = BRANCH_HALT_VOTED,
 786         .clkr = {
 787                 .enable_reg = 0x6000,
 788                 .enable_mask = BIT(8),
 789                 .hw.init = &(struct clk_init_data){
 790                         .name = "gcc_prng_ahb_clk",
 791                         .parent_names = (const char *[]){
 792                                 "pcnoc_clk_src",
 793                         },
 794                         .num_parents = 1,
 795                         .ops = &clk_branch2_ops,
 796                 },
 797         },
 798 };
 799
 800 static struct clk_branch gcc_qpic_ahb_clk = {
 801         .halt_reg = 0x1c008,
 802         .clkr = {
 803                 .enable_reg = 0x1c008,
 804                 .enable_mask = BIT(0),
 805                 .hw.init = &(struct clk_init_data){
 806                         .name = "gcc_qpic_ahb_clk",
 807                         .parent_names = (const char *[]){
 808                                 "pcnoc_clk_src",
 809                         },
 810                         .num_parents = 1,
 811                         .ops = &clk_branch2_ops,
 812                 },
 813         },
 814 };
 815
 816 static struct clk_branch gcc_qpic_clk = {
 817         .halt_reg = 0x1c004,
 818         .clkr = {
 819                 .enable_reg = 0x1c004,
 820                 .enable_mask = BIT(0),
 821                 .hw.init = &(struct clk_init_data){
 822                         .name = "gcc_qpic_clk",
 823                         .parent_names = (const char *[]){
 824                                 "pcnoc_clk_src",
 825                         },
 826                         .num_parents = 1,
 827                         .ops = &clk_branch2_ops,
 828                 },
 829         },
 830 };
 831
 832 static struct clk_branch gcc_sdcc1_ahb_clk = {
 833         .halt_reg = 0x18010,
 834         .clkr = {
 835                 .enable_reg = 0x18010,
 836                 .enable_mask = BIT(0),
 837                 .hw.init = &(struct clk_init_data){
 838                         .name = "gcc_sdcc1_ahb_clk",
 839                         .parent_names = (const char *[]){
 840                                 "pcnoc_clk_src",
 841                         },
 842                         .num_parents = 1,
 843                         .ops = &clk_branch2_ops,
 844                 },
 845         },
 846 };
 847
 848 static struct clk_branch gcc_sdcc1_apps_clk = {
 849         .halt_reg = 0x1800c,
 850         .clkr = {
 851                 .enable_reg = 0x1800c,
 852                 .enable_mask = BIT(0),
 853                 .hw.init = &(struct clk_init_data){
 854                         .name = "gcc_sdcc1_apps_clk",
 855                         .parent_names = (const char *[]){
 856                                 "sdcc1_apps_clk_src",
 857                         },
 858                         .num_parents = 1,
 859                         .ops = &clk_branch2_ops,
 860                         .flags = CLK_SET_RATE_PARENT,
 861                 },
 862         },
 863 };
 864
 865 static struct clk_branch gcc_tlmm_ahb_clk = {
 866         .halt_reg = 0x5004,
 867         .halt_check = BRANCH_HALT_VOTED,
 868         .clkr = {
 869                 .enable_reg = 0x6000,
 870                 .enable_mask = BIT(5),
 871                 .hw.init = &(struct clk_init_data){
 872                         .name = "gcc_tlmm_ahb_clk",
 873                         .parent_names = (const char *[]){
 874                                 "pcnoc_clk_src",
 875                         },
 876                         .num_parents = 1,
 877                         .ops = &clk_branch2_ops,
 878                 },
 879         },
 880 };
 881
 882 static struct clk_branch gcc_usb2_master_clk = {
 883         .halt_reg = 0x1e00c,
 884         .clkr = {
 885                 .enable_reg = 0x1e00c,
 886                 .enable_mask = BIT(0),
 887                 .hw.init = &(struct clk_init_data){
 888                         .name = "gcc_usb2_master_clk",
 889                         .parent_names = (const char *[]){
 890                                 "pcnoc_clk_src",
 891                         },
 892                         .num_parents = 1,
 893                         .ops = &clk_branch2_ops,
 894                 },
 895         },
 896 };
 897
 898 static struct clk_branch gcc_usb2_sleep_clk = {
 899         .halt_reg = 0x1e010,
 900         .clkr = {
 901                 .enable_reg = 0x1e010,
 902                 .enable_mask = BIT(0),
 903                 .hw.init = &(struct clk_init_data){
 904                         .name = "gcc_usb2_sleep_clk",
 905                         .parent_names = (const char *[]){
 906                                 "gcc_sleep_clk_src",
 907                         },
 908                         .num_parents = 1,
 909                         .ops = &clk_branch2_ops,
 910                 },
 911         },
 912 };
 913
 914 static struct clk_branch gcc_usb2_mock_utmi_clk = {
 915         .halt_reg = 0x1e014,
 916         .clkr = {
 917                 .enable_reg = 0x1e014,
 918                 .enable_mask = BIT(0),
 919                 .hw.init = &(struct clk_init_data){
 920                         .name = "gcc_usb2_mock_utmi_clk",
 921                         .parent_names = (const char *[]){
 922                                 "usb30_mock_utmi_clk_src",
 923                         },
 924                         .num_parents = 1,
 925                         .ops = &clk_branch2_ops,
 926                         .flags = CLK_SET_RATE_PARENT,
 927                 },
 928         },
 929 };
 930
 931 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
 932         F(2000000, P_FEPLL200, 10, 0, 0),
 933         { }
 934 };
 935
 936 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 937         .cmd_rcgr = 0x1e000,
 938         .hid_width = 5,
 939         .parent_map = gcc_xo_200_map,
 940         .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
 941         .clkr.hw.init = &(struct clk_init_data){
 942                 .name = "usb30_mock_utmi_clk_src",
 943                 .parent_names = gcc_xo_200,
 944                 .num_parents = 2,
 945                 .ops = &clk_rcg2_ops,
 946         },
 947 };
 948
 949 static struct clk_branch gcc_usb3_master_clk = {
 950         .halt_reg = 0x1e028,
 951         .clkr = {
 952                 .enable_reg = 0x1e028,
 953                 .enable_mask = BIT(0),
 954                 .hw.init = &(struct clk_init_data){
 955                         .name = "gcc_usb3_master_clk",
 956                         .parent_names = (const char *[]){
 957                                 "fepll125",
 958                         },
 959                         .num_parents = 1,
 960                         .ops = &clk_branch2_ops,
 961                 },
 962         },
 963 };
 964
 965 static struct clk_branch gcc_usb3_sleep_clk = {
 966         .halt_reg = 0x1e02C,
 967         .clkr = {
 968                 .enable_reg = 0x1e02C,
 969                 .enable_mask = BIT(0),
 970                 .hw.init = &(struct clk_init_data){
 971                         .name = "gcc_usb3_sleep_clk",
 972                         .parent_names = (const char *[]){
 973                                 "gcc_sleep_clk_src",
 974                         },
 975                         .num_parents = 1,
 976                         .ops = &clk_branch2_ops,
 977                 },
 978         },
 979 };
 980
 981 static struct clk_branch gcc_usb3_mock_utmi_clk = {
 982         .halt_reg = 0x1e030,
 983         .clkr = {
 984                 .enable_reg = 0x1e030,
 985                 .enable_mask = BIT(0),
 986                 .hw.init = &(struct clk_init_data){
 987                         .name = "gcc_usb3_mock_utmi_clk",
 988                         .parent_names = (const char *[]){
 989                                 "usb30_mock_utmi_clk_src",
 990                         },
 991                         .num_parents = 1,
 992                         .ops = &clk_branch2_ops,
 993                         .flags = CLK_SET_RATE_PARENT,
 994                 },
 995         },
 996 };
 997
 998 static const struct freq_tbl ftbl_gcc_fephy_dly_clk[] = {
 999         F(125000000, P_FEPLL125DLY, 1, 0, 0),
1000         { }
1001 };
1002
1003 static struct clk_rcg2 fephy_125m_dly_clk_src = {
1004         .cmd_rcgr = 0x12000,
1005         .hid_width = 5,
1006         .parent_map = gcc_xo_125_dly_map,
1007         .freq_tbl = ftbl_gcc_fephy_dly_clk,
1008         .clkr.hw.init = &(struct clk_init_data){
1009                 .name = "fephy_125m_dly_clk_src",
1010                 .parent_names = gcc_xo_125_dly,
1011                 .num_parents = 2,
1012                 .ops = &clk_rcg2_ops,
1013         },
1014 };
1015
1016
1017 static const struct freq_tbl ftbl_gcc_wcss2g_clk[] = {
1018         F(48000000, P_XO, 1, 0, 0),
1019         F(250000000, P_FEPLLWCSS2G, 1, 0, 0),
1020         { }
1021 };
1022
1023 static struct clk_rcg2 wcss2g_clk_src = {
1024         .cmd_rcgr = 0x1f000,
1025         .hid_width = 5,
1026         .freq_tbl = ftbl_gcc_wcss2g_clk,
1027         .parent_map = gcc_xo_wcss2g_map,
1028         .clkr.hw.init = &(struct clk_init_data){
1029                 .name = "wcss2g_clk_src",
1030                 .parent_names = gcc_xo_wcss2g,
1031                 .num_parents = 2,
1032                 .ops = &clk_rcg2_ops,
1033                 .flags = CLK_SET_RATE_PARENT,
1034         },
1035 };
1036
1037 static struct clk_branch gcc_wcss2g_clk = {
1038         .halt_reg = 0x1f00C,
1039         .clkr = {
1040                 .enable_reg = 0x1f00C,
1041                 .enable_mask = BIT(0),
1042                 .hw.init = &(struct clk_init_data){
1043                         .name = "gcc_wcss2g_clk",
1044                         .parent_names = (const char *[]){
1045                                 "wcss2g_clk_src",
1046                         },
1047                         .num_parents = 1,
1048                         .ops = &clk_branch2_ops,
1049                         .flags = CLK_SET_RATE_PARENT,
1050                 },
1051         },
1052 };
1053
1054 static struct clk_branch gcc_wcss2g_ref_clk = {
1055         .halt_reg = 0x1f00C,
1056         .clkr = {
1057                 .enable_reg = 0x1f00C,
1058                 .enable_mask = BIT(0),
1059                 .hw.init = &(struct clk_init_data){
1060                         .name = "gcc_wcss2g_ref_clk",
1061                         .parent_names = (const char *[]){
1062                                 "xo",
1063                         },
1064                         .num_parents = 1,
1065                         .ops = &clk_branch2_ops,
1066                         .flags = CLK_SET_RATE_PARENT,
1067                 },
1068         },
1069 };
1070
1071 static struct clk_branch gcc_wcss2g_rtc_clk = {
1072         .halt_reg = 0x1f010,
1073         .clkr = {
1074                 .enable_reg = 0x1f010,
1075                 .enable_mask = BIT(0),
1076                 .hw.init = &(struct clk_init_data){
1077                         .name = "gcc_wcss2g_rtc_clk",
1078                         .parent_names = (const char *[]){
1079                                 "gcc_sleep_clk_src",
1080                         },
1081                         .num_parents = 1,
1082                         .ops = &clk_branch2_ops,
1083                 },
1084         },
1085 };
1086
1087 static const struct freq_tbl ftbl_gcc_wcss5g_clk[] = {
1088         F(48000000, P_XO, 1, 0, 0),
1089         F(250000000, P_FEPLLWCSS5G, 1, 0, 0),
1090         { }
1091 };
1092
1093 static struct clk_rcg2 wcss5g_clk_src = {
1094         .cmd_rcgr = 0x20000,
1095         .hid_width = 5,
1096         .parent_map = gcc_xo_wcss5g_map,
1097         .freq_tbl = ftbl_gcc_wcss5g_clk,
1098         .clkr.hw.init = &(struct clk_init_data){
1099                 .name = "wcss5g_clk_src",
1100                 .parent_names = gcc_xo_wcss5g,
1101                 .num_parents = 2,
1102                 .ops = &clk_rcg2_ops,
1103         },
1104 };
1105
1106 static struct clk_branch gcc_wcss5g_clk = {
1107         .halt_reg = 0x2000c,
1108         .clkr = {
1109                 .enable_reg = 0x2000c,
1110                 .enable_mask = BIT(0),
1111                 .hw.init = &(struct clk_init_data){
1112                         .name = "gcc_wcss5g_clk",
1113                         .parent_names = (const char *[]){
1114                                 "wcss5g_clk_src",
1115                         },
1116                         .num_parents = 1,
1117                         .ops = &clk_branch2_ops,
1118                         .flags = CLK_SET_RATE_PARENT,
1119                 },
1120         },
1121 };
1122
1123 static struct clk_branch gcc_wcss5g_ref_clk = {
1124         .halt_reg = 0x2000c,
1125         .clkr = {
1126                 .enable_reg = 0x2000c,
1127                 .enable_mask = BIT(0),
1128                 .hw.init = &(struct clk_init_data){
1129                         .name = "gcc_wcss5g_ref_clk",
1130                         .parent_names = (const char *[]){
1131                                 "xo",
1132                         },
1133                         .num_parents = 1,
1134                         .ops = &clk_branch2_ops,
1135                         .flags = CLK_SET_RATE_PARENT,
1136                 },
1137         },
1138 };
1139
1140 static struct clk_branch gcc_wcss5g_rtc_clk = {
1141         .halt_reg = 0x20010,
1142         .clkr = {
1143                 .enable_reg = 0x20010,
1144                 .enable_mask = BIT(0),
1145                 .hw.init = &(struct clk_init_data){
1146                         .name = "gcc_wcss5g_rtc_clk",
1147                         .parent_names = (const char *[]){
1148                                 "gcc_sleep_clk_src",
1149                         },
1150                         .num_parents = 1,
1151                         .ops = &clk_branch2_ops,
1152                         .flags = CLK_SET_RATE_PARENT,
1153                 },
1154         },
1155 };
1156
1157 static struct clk_regmap *gcc_ipq4019_clocks[] = {
1158         [AUDIO_CLK_SRC] = &audio_clk_src.clkr,
1159         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
1160         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
1161         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
1162         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
1163         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
1164         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
1165         [GCC_USB3_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
1166         [GCC_APPS_CLK_SRC] = &apps_clk_src.clkr,
1167         [GCC_APPS_AHB_CLK_SRC] = &apps_ahb_clk_src.clkr,
1168         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
1169         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
1170         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
1171         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
1172         [FEPHY_125M_DLY_CLK_SRC] = &fephy_125m_dly_clk_src.clkr,
1173         [WCSS2G_CLK_SRC] = &wcss2g_clk_src.clkr,
1174         [WCSS5G_CLK_SRC] = &wcss5g_clk_src.clkr,
1175         [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
1176         [GCC_AUDIO_AHB_CLK] = &gcc_audio_ahb_clk.clkr,
1177         [GCC_AUDIO_PWM_CLK] = &gcc_audio_pwm_clk.clkr,
1178         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
1179         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
1180         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
1181         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
1182         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
1183         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
1184         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
1185         [GCC_DCD_XO_CLK] = &gcc_dcd_xo_clk.clkr,
1186         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
1187         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
1188         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
1189         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
1190         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
1191         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
1192         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
1193         [GCC_ESS_CLK] = &gcc_ess_clk.clkr,
1194         [GCC_IMEM_AXI_CLK] = &gcc_imem_axi_clk.clkr,
1195         [GCC_IMEM_CFG_AHB_CLK] = &gcc_imem_cfg_ahb_clk.clkr,
1196         [GCC_PCIE_AHB_CLK] = &gcc_pcie_ahb_clk.clkr,
1197         [GCC_PCIE_AXI_M_CLK] = &gcc_pcie_axi_m_clk.clkr,
1198         [GCC_PCIE_AXI_S_CLK] = &gcc_pcie_axi_s_clk.clkr,
1199         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
1200         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
1201         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
1202         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
1203         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
1204         [GCC_TLMM_AHB_CLK] = &gcc_tlmm_ahb_clk.clkr,
1205         [GCC_USB2_MASTER_CLK] = &gcc_usb2_master_clk.clkr,
1206         [GCC_USB2_SLEEP_CLK] = &gcc_usb2_sleep_clk.clkr,
1207         [GCC_USB2_MOCK_UTMI_CLK] = &gcc_usb2_mock_utmi_clk.clkr,
1208         [GCC_USB3_MASTER_CLK] = &gcc_usb3_master_clk.clkr,
1209         [GCC_USB3_SLEEP_CLK] = &gcc_usb3_sleep_clk.clkr,
1210         [GCC_USB3_MOCK_UTMI_CLK] = &gcc_usb3_mock_utmi_clk.clkr,
1211         [GCC_WCSS2G_CLK] = &gcc_wcss2g_clk.clkr,
1212         [GCC_WCSS2G_REF_CLK] = &gcc_wcss2g_ref_clk.clkr,
1213         [GCC_WCSS2G_RTC_CLK] = &gcc_wcss2g_rtc_clk.clkr,
1214         [GCC_WCSS5G_CLK] = &gcc_wcss5g_clk.clkr,
1215         [GCC_WCSS5G_REF_CLK] = &gcc_wcss5g_ref_clk.clkr,
1216         [GCC_WCSS5G_RTC_CLK] = &gcc_wcss5g_rtc_clk.clkr,
1217 };
1218
1219 static const struct qcom_reset_map gcc_ipq4019_resets[] = {
1220         [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
1221         [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
1222         [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
1223         [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
1224         [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
1225         [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
1226         [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
1227         [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
1228         [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
1229         [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
1230         [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
1231         [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
1232         [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
1233         [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
1234         [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
1235         [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
1236         [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
1237         [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
1238         [PCIE_AHB_ARES] = { 0x1d010, 10 },
1239         [PCIE_PWR_ARES] = { 0x1d010, 9 },
1240         [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
1241         [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
1242         [PCIE_PHY_ARES] = { 0x1d010, 6 },
1243         [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
1244         [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
1245         [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
1246         [PCIE_PIPE_ARES] = { 0x1d010, 2 },
1247         [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
1248         [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
1249         [ESS_RESET] = { 0x12008, 0},
1250         [GCC_BLSP1_BCR] = {0x01000, 0},
1251         [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
1252         [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
1253         [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
1254         [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
1255         [GCC_BIMC_BCR] = {0x04000, 0},
1256         [GCC_TLMM_BCR] = {0x05000, 0},
1257         [GCC_IMEM_BCR] = {0x0E000, 0},
1258         [GCC_ESS_BCR] = {0x12008, 0},
1259         [GCC_PRNG_BCR] = {0x13000, 0},
1260         [GCC_BOOT_ROM_BCR] = {0x13008, 0},
1261         [GCC_CRYPTO_BCR] = {0x16000, 0},
1262         [GCC_SDCC1_BCR] = {0x18000, 0},
1263         [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
1264         [GCC_AUDIO_BCR] = {0x1B008, 0},
1265         [GCC_QPIC_BCR] = {0x1C000, 0},
1266         [GCC_PCIE_BCR] = {0x1D000, 0},
1267         [GCC_USB2_BCR] = {0x1E008, 0},
1268         [GCC_USB2_PHY_BCR] = {0x1E018, 0},
1269         [GCC_USB3_BCR] = {0x1E024, 0},
1270         [GCC_USB3_PHY_BCR] = {0x1E034, 0},
1271         [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
1272         [GCC_PCNOC_BCR] = {0x2102C, 0},
1273         [GCC_DCD_BCR] = {0x21038, 0},
1274         [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
1275         [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
1276         [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
1277         [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
1278         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
1279         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
1280         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
1281         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
1282         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
1283         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
1284         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
1285         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
1286         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
1287         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
1288         [GCC_TCSR_BCR] = {0x22000, 0},
1289         [GCC_MPM_BCR] = {0x24000, 0},
1290         [GCC_SPDM_BCR] = {0x25000, 0},
1291 };
1292
1293 static const struct regmap_config gcc_ipq4019_regmap_config = {
1294         .reg_bits       = 32,
1295         .reg_stride     = 4,
1296         .val_bits       = 32,
1297         .max_register   = 0x2dfff,
1298         .fast_io        = true,
1299 };
1300
1301 static const struct qcom_cc_desc gcc_ipq4019_desc = {
1302         .config = &gcc_ipq4019_regmap_config,
1303         .clks = gcc_ipq4019_clocks,
1304         .num_clks = ARRAY_SIZE(gcc_ipq4019_clocks),
1305         .resets = gcc_ipq4019_resets,
1306         .num_resets = ARRAY_SIZE(gcc_ipq4019_resets),
1307 };
1308
1309 static const struct of_device_id gcc_ipq4019_match_table[] = {
1310         { .compatible = "qcom,gcc-ipq4019" },
1311         { }
1312 };
1313 MODULE_DEVICE_TABLE(of, gcc_ipq4019_match_table);
1314
1315 static int gcc_ipq4019_probe(struct platform_device *pdev)
1316 {
1317         struct device *dev = &pdev->dev;
1318
1319         clk_register_fixed_rate(dev, "fepll125", "xo", 0, 200000000);
1320         clk_register_fixed_rate(dev, "fepll125dly", "xo", 0, 200000000);
1321         clk_register_fixed_rate(dev, "fepllwcss2g", "xo", 0, 200000000);
1322         clk_register_fixed_rate(dev, "fepllwcss5g", "xo", 0, 200000000);
1323         clk_register_fixed_rate(dev, "fepll200", "xo", 0, 200000000);
1324         clk_register_fixed_rate(dev, "fepll500", "xo", 0, 200000000);
1325         clk_register_fixed_rate(dev, "ddrpllapss", "xo", 0, 666000000);
1326
1327         return qcom_cc_probe(pdev, &gcc_ipq4019_desc);
1328 }
1329
1330 static struct platform_driver gcc_ipq4019_driver = {
1331         .probe          = gcc_ipq4019_probe,
1332         .driver         = {
1333                 .name   = "qcom,gcc-ipq4019",
1334                 .of_match_table = gcc_ipq4019_match_table,
1335         },
1336 };
1337
1338 static int __init gcc_ipq4019_init(void)
1339 {
1340         return platform_driver_register(&gcc_ipq4019_driver);
1341 }
1342 core_initcall(gcc_ipq4019_init);
1343
1344 static void __exit gcc_ipq4019_exit(void)
1345 {
1346         platform_driver_unregister(&gcc_ipq4019_driver);
1347 }
1348 module_exit(gcc_ipq4019_exit);
1349
1350 MODULE_ALIAS("platform:gcc-ipq4019");
1351 MODULE_LICENSE("GPL v2");
1352 MODULE_DESCRIPTION("QCOM GCC IPQ4019 driver");