drivers/clk/qcom/gdsc.c

   1 /*
   2  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/bitops.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/kernel.h>
  19 #include <linux/ktime.h>
  20 #include <linux/pm_domain.h>
  21 #include <linux/regmap.h>
  22 #include <linux/reset-controller.h>
  23 #include <linux/slab.h>
  24 #include "gdsc.h"
  25
  26 #define PWR_ON_MASK             BIT(31)
  27 #define EN_REST_WAIT_MASK       GENMASK_ULL(23, 20)
  28 #define EN_FEW_WAIT_MASK        GENMASK_ULL(19, 16)
  29 #define CLK_DIS_WAIT_MASK       GENMASK_ULL(15, 12)
  30 #define SW_OVERRIDE_MASK        BIT(2)
  31 #define HW_CONTROL_MASK         BIT(1)
  32 #define SW_COLLAPSE_MASK        BIT(0)
  33 #define GMEM_CLAMP_IO_MASK      BIT(0)
  34
  35 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
  36 #define EN_REST_WAIT_VAL        (0x2 << 20)
  37 #define EN_FEW_WAIT_VAL         (0x8 << 16)
  38 #define CLK_DIS_WAIT_VAL        (0x2 << 12)
  39
  40 #define RETAIN_MEM              BIT(14)
  41 #define RETAIN_PERIPH           BIT(13)
  42
  43 #define TIMEOUT_US              100
  44
  45 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
  46
  47 static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
  48 {
  49         u32 val;
  50         int ret;
  51
  52         ret = regmap_read(sc->regmap, reg, &val);
  53         if (ret)
  54                 return ret;
  55
  56         return !!(val & PWR_ON_MASK);
  57 }
  58
  59 static int gdsc_hwctrl(struct gdsc *sc, bool en)
  60 {
  61         u32 val = en ? HW_CONTROL_MASK : 0;
  62
  63         return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
  64 }
  65
  66 static int gdsc_toggle_logic(struct gdsc *sc, bool en)
  67 {
  68         int ret;
  69         u32 val = en ? 0 : SW_COLLAPSE_MASK;
  70         ktime_t start;
  71         unsigned int status_reg = sc->gdscr;
  72
  73         ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
  74         if (ret)
  75                 return ret;
  76
  77         /* If disabling votable gdscs, don't poll on status */
  78         if ((sc->flags & VOTABLE) && !en) {
  79                 /*
  80                  * Add a short delay here to ensure that an enable
  81                  * right after it was disabled does not put it in an
  82                  * unknown state
  83                  */
  84                 udelay(TIMEOUT_US);
  85                 return 0;
  86         }
  87
  88         if (sc->gds_hw_ctrl) {
  89                 status_reg = sc->gds_hw_ctrl;
  90                 /*
  91                  * The gds hw controller asserts/de-asserts the status bit soon
  92                  * after it receives a power on/off request from a master.
  93                  * The controller then takes around 8 xo cycles to start its
  94                  * internal state machine and update the status bit. During
  95                  * this time, the status bit does not reflect the true status
  96                  * of the core.
  97                  * Add a delay of 1 us between writing to the SW_COLLAPSE bit
  98                  * and polling the status bit.
  99                  */
 100                 udelay(1);
 101         }
 102
 103         start = ktime_get();
 104         do {
 105                 if (gdsc_is_enabled(sc, status_reg) == en)
 106                         return 0;
 107         } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
 108
 109         if (gdsc_is_enabled(sc, status_reg) == en)
 110                 return 0;
 111
 112         return -ETIMEDOUT;
 113 }
 114
 115 static inline int gdsc_deassert_reset(struct gdsc *sc)
 116 {
 117         int i;
 118
 119         for (i = 0; i < sc->reset_count; i++)
 120                 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
 121         return 0;
 122 }
 123
 124 static inline int gdsc_assert_reset(struct gdsc *sc)
 125 {
 126         int i;
 127
 128         for (i = 0; i < sc->reset_count; i++)
 129                 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
 130         return 0;
 131 }
 132
 133 static inline void gdsc_force_mem_on(struct gdsc *sc)
 134 {
 135         int i;
 136         u32 mask = RETAIN_MEM | RETAIN_PERIPH;
 137
 138         for (i = 0; i < sc->cxc_count; i++)
 139                 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
 140 }
 141
 142 static inline void gdsc_clear_mem_on(struct gdsc *sc)
 143 {
 144         int i;
 145         u32 mask = RETAIN_MEM | RETAIN_PERIPH;
 146
 147         for (i = 0; i < sc->cxc_count; i++)
 148                 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
 149 }
 150
 151 static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
 152 {
 153         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 154                            GMEM_CLAMP_IO_MASK, 0);
 155 }
 156
 157 static inline void gdsc_assert_clamp_io(struct gdsc *sc)
 158 {
 159         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 160                            GMEM_CLAMP_IO_MASK, 1);
 161 }
 162
 163 static int gdsc_enable(struct generic_pm_domain *domain)
 164 {
 165         struct gdsc *sc = domain_to_gdsc(domain);
 166         int ret;
 167
 168         if (sc->pwrsts == PWRSTS_ON)
 169                 return gdsc_deassert_reset(sc);
 170
 171         if (sc->flags & CLAMP_IO)
 172                 gdsc_deassert_clamp_io(sc);
 173
 174         ret = gdsc_toggle_logic(sc, true);
 175         if (ret)
 176                 return ret;
 177
 178         if (sc->pwrsts & PWRSTS_OFF)
 179                 gdsc_force_mem_on(sc);
 180
 181         /*
 182          * If clocks to this power domain were already on, they will take an
 183          * additional 4 clock cycles to re-enable after the power domain is
 184          * enabled. Delay to account for this. A delay is also needed to ensure
 185          * clocks are not enabled within 400ns of enabling power to the
 186          * memories.
 187          */
 188         udelay(1);
 189
 190         /* Turn on HW trigger mode if supported */
 191         if (sc->flags & HW_CTRL)
 192                 return gdsc_hwctrl(sc, true);
 193
 194         return 0;
 195 }
 196
 197 static int gdsc_disable(struct generic_pm_domain *domain)
 198 {
 199         struct gdsc *sc = domain_to_gdsc(domain);
 200         int ret;
 201
 202         if (sc->pwrsts == PWRSTS_ON)
 203                 return gdsc_assert_reset(sc);
 204
 205         /* Turn off HW trigger mode if supported */
 206         if (sc->flags & HW_CTRL) {
 207                 ret = gdsc_hwctrl(sc, false);
 208                 if (ret < 0)
 209                         return ret;
 210         }
 211
 212         if (sc->pwrsts & PWRSTS_OFF)
 213                 gdsc_clear_mem_on(sc);
 214
 215         ret = gdsc_toggle_logic(sc, false);
 216         if (ret)
 217                 return ret;
 218
 219         if (sc->flags & CLAMP_IO)
 220                 gdsc_assert_clamp_io(sc);
 221
 222         return 0;
 223 }
 224
 225 static int gdsc_init(struct gdsc *sc)
 226 {
 227         u32 mask, val;
 228         int on, ret;
 229         unsigned int reg;
 230
 231         /*
 232          * Disable HW trigger: collapse/restore occur based on registers writes.
 233          * Disable SW override: Use hardware state-machine for sequencing.
 234          * Configure wait time between states.
 235          */
 236         mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
 237                EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
 238         val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
 239         ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
 240         if (ret)
 241                 return ret;
 242
 243         /* Force gdsc ON if only ON state is supported */
 244         if (sc->pwrsts == PWRSTS_ON) {
 245                 ret = gdsc_toggle_logic(sc, true);
 246                 if (ret)
 247                         return ret;
 248         }
 249
 250         reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
 251         on = gdsc_is_enabled(sc, reg);
 252         if (on < 0)
 253                 return on;
 254
 255         /*
 256          * Votable GDSCs can be ON due to Vote from other masters.
 257          * If a Votable GDSC is ON, make sure we have a Vote.
 258          */
 259         if ((sc->flags & VOTABLE) && on)
 260                 gdsc_enable(&sc->pd);
 261
 262         if (on || (sc->pwrsts & PWRSTS_RET))
 263                 gdsc_force_mem_on(sc);
 264         else
 265                 gdsc_clear_mem_on(sc);
 266
 267         sc->pd.power_off = gdsc_disable;
 268         sc->pd.power_on = gdsc_enable;
 269         pm_genpd_init(&sc->pd, NULL, !on);
 270
 271         return 0;
 272 }
 273
 274 int gdsc_register(struct gdsc_desc *desc,
 275                   struct reset_controller_dev *rcdev, struct regmap *regmap)
 276 {
 277         int i, ret;
 278         struct genpd_onecell_data *data;
 279         struct device *dev = desc->dev;
 280         struct gdsc **scs = desc->scs;
 281         size_t num = desc->num;
 282
 283         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 284         if (!data)
 285                 return -ENOMEM;
 286
 287         data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
 288                                      GFP_KERNEL);
 289         if (!data->domains)
 290                 return -ENOMEM;
 291
 292         data->num_domains = num;
 293         for (i = 0; i < num; i++) {
 294                 if (!scs[i])
 295                         continue;
 296                 scs[i]->regmap = regmap;
 297                 scs[i]->rcdev = rcdev;
 298                 ret = gdsc_init(scs[i]);
 299                 if (ret)
 300                         return ret;
 301                 data->domains[i] = &scs[i]->pd;
 302         }
 303
 304         /* Add subdomains */
 305         for (i = 0; i < num; i++) {
 306                 if (!scs[i])
 307                         continue;
 308                 if (scs[i]->parent)
 309                         pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
 310         }
 311
 312         return of_genpd_add_provider_onecell(dev->of_node, data);
 313 }
 314
 315 void gdsc_unregister(struct gdsc_desc *desc)
 316 {
 317         int i;
 318         struct device *dev = desc->dev;
 319         struct gdsc **scs = desc->scs;
 320         size_t num = desc->num;
 321
 322         /* Remove subdomains */
 323         for (i = 0; i < num; i++) {
 324                 if (!scs[i])
 325                         continue;
 326                 if (scs[i]->parent)
 327                         pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
 328         }
 329         of_genpd_del_provider(dev->of_node);
 330 }