drivers/clk/renesas/rcar-gen3-cpg.c

   1 /*
   2  * R-Car Gen3 Clock Pulse Generator
   3  *
   4  * Copyright (C) 2015-2016 Glider bvba
   5  *
   6  * Based on clk-rcar-gen3.c
   7  *
   8  * Copyright (C) 2015 Renesas Electronics Corp.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; version 2 of the License.
  13  */
  14
  15 #include <linux/bug.h>
  16 #include <linux/clk.h>
  17 #include <linux/clk-provider.h>
  18 #include <linux/device.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/slab.h>
  23
  24 #include "renesas-cpg-mssr.h"
  25 #include "rcar-gen3-cpg.h"
  26
  27 #define CPG_PLL0CR              0x00d8
  28 #define CPG_PLL2CR              0x002c
  29 #define CPG_PLL4CR              0x01f4
  30
  31
  32 /*
  33  * SDn Clock
  34  */
  35 #define CPG_SD_STP_HCK          BIT(9)
  36 #define CPG_SD_STP_CK           BIT(8)
  37
  38 #define CPG_SD_STP_MASK         (CPG_SD_STP_HCK | CPG_SD_STP_CK)
  39 #define CPG_SD_FC_MASK          (0x7 << 2 | 0x3 << 0)
  40
  41 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
  42 { \
  43         .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
  44                ((stp_ck) ? CPG_SD_STP_CK : 0) | \
  45                ((sd_srcfc) << 2) | \
  46                ((sd_fc) << 0), \
  47         .div = (sd_div), \
  48 }
  49
  50 struct sd_div_table {
  51         u32 val;
  52         unsigned int div;
  53 };
  54
  55 struct sd_clock {
  56         struct clk_hw hw;
  57         void __iomem *reg;
  58         const struct sd_div_table *div_table;
  59         unsigned int div_num;
  60         unsigned int div_min;
  61         unsigned int div_max;
  62 };
  63
  64 /* SDn divider
  65  *                     sd_srcfc   sd_fc   div
  66  * stp_hck   stp_ck    (div)      (div)     = sd_srcfc x sd_fc
  67  *-------------------------------------------------------------------
  68  *  0         0         0 (1)      1 (4)      4
  69  *  0         0         1 (2)      1 (4)      8
  70  *  1         0         2 (4)      1 (4)     16
  71  *  1         0         3 (8)      1 (4)     32
  72  *  1         0         4 (16)     1 (4)     64
  73  *  0         0         0 (1)      0 (2)      2
  74  *  0         0         1 (2)      0 (2)      4
  75  *  1         0         2 (4)      0 (2)      8
  76  *  1         0         3 (8)      0 (2)     16
  77  *  1         0         4 (16)     0 (2)     32
  78  */
  79 static const struct sd_div_table cpg_sd_div_table[] = {
  80 /*      CPG_SD_DIV_TABLE_DATA(stp_hck,  stp_ck,   sd_srcfc,   sd_fc,  sd_div) */
  81         CPG_SD_DIV_TABLE_DATA(0,        0,        0,          1,        4),
  82         CPG_SD_DIV_TABLE_DATA(0,        0,        1,          1,        8),
  83         CPG_SD_DIV_TABLE_DATA(1,        0,        2,          1,       16),
  84         CPG_SD_DIV_TABLE_DATA(1,        0,        3,          1,       32),
  85         CPG_SD_DIV_TABLE_DATA(1,        0,        4,          1,       64),
  86         CPG_SD_DIV_TABLE_DATA(0,        0,        0,          0,        2),
  87         CPG_SD_DIV_TABLE_DATA(0,        0,        1,          0,        4),
  88         CPG_SD_DIV_TABLE_DATA(1,        0,        2,          0,        8),
  89         CPG_SD_DIV_TABLE_DATA(1,        0,        3,          0,       16),
  90         CPG_SD_DIV_TABLE_DATA(1,        0,        4,          0,       32),
  91 };
  92
  93 #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
  94
  95 static int cpg_sd_clock_enable(struct clk_hw *hw)
  96 {
  97         struct sd_clock *clock = to_sd_clock(hw);
  98         u32 val, sd_fc;
  99         unsigned int i;
 100
 101         val = readl(clock->reg);
 102
 103         sd_fc = val & CPG_SD_FC_MASK;
 104         for (i = 0; i < clock->div_num; i++)
 105                 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
 106                         break;
 107
 108         if (i >= clock->div_num)
 109                 return -EINVAL;
 110
 111         val &= ~(CPG_SD_STP_MASK);
 112         val |= clock->div_table[i].val & CPG_SD_STP_MASK;
 113
 114         writel(val, clock->reg);
 115
 116         return 0;
 117 }
 118
 119 static void cpg_sd_clock_disable(struct clk_hw *hw)
 120 {
 121         struct sd_clock *clock = to_sd_clock(hw);
 122
 123         writel(readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);
 124 }
 125
 126 static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
 127 {
 128         struct sd_clock *clock = to_sd_clock(hw);
 129
 130         return !(readl(clock->reg) & CPG_SD_STP_MASK);
 131 }
 132
 133 static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
 134                                                 unsigned long parent_rate)
 135 {
 136         struct sd_clock *clock = to_sd_clock(hw);
 137         unsigned long rate = parent_rate;
 138         u32 val, sd_fc;
 139         unsigned int i;
 140
 141         val = readl(clock->reg);
 142
 143         sd_fc = val & CPG_SD_FC_MASK;
 144         for (i = 0; i < clock->div_num; i++)
 145                 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
 146                         break;
 147
 148         if (i >= clock->div_num)
 149                 return -EINVAL;
 150
 151         return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div);
 152 }
 153
 154 static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
 155                                           unsigned long rate,
 156                                           unsigned long parent_rate)
 157 {
 158         unsigned int div;
 159
 160         if (!rate)
 161                 rate = 1;
 162
 163         div = DIV_ROUND_CLOSEST(parent_rate, rate);
 164
 165         return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
 166 }
 167
 168 static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
 169                                       unsigned long *parent_rate)
 170 {
 171         struct sd_clock *clock = to_sd_clock(hw);
 172         unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
 173
 174         return DIV_ROUND_CLOSEST(*parent_rate, div);
 175 }
 176
 177 static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
 178                                    unsigned long parent_rate)
 179 {
 180         struct sd_clock *clock = to_sd_clock(hw);
 181         unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
 182         u32 val;
 183         unsigned int i;
 184
 185         for (i = 0; i < clock->div_num; i++)
 186                 if (div == clock->div_table[i].div)
 187                         break;
 188
 189         if (i >= clock->div_num)
 190                 return -EINVAL;
 191
 192         val = readl(clock->reg);
 193         val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
 194         val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
 195         writel(val, clock->reg);
 196
 197         return 0;
 198 }
 199
 200 static const struct clk_ops cpg_sd_clock_ops = {
 201         .enable = cpg_sd_clock_enable,
 202         .disable = cpg_sd_clock_disable,
 203         .is_enabled = cpg_sd_clock_is_enabled,
 204         .recalc_rate = cpg_sd_clock_recalc_rate,
 205         .round_rate = cpg_sd_clock_round_rate,
 206         .set_rate = cpg_sd_clock_set_rate,
 207 };
 208
 209 static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
 210                                                void __iomem *base,
 211                                                const char *parent_name)
 212 {
 213         struct clk_init_data init;
 214         struct sd_clock *clock;
 215         struct clk *clk;
 216         unsigned int i;
 217
 218         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
 219         if (!clock)
 220                 return ERR_PTR(-ENOMEM);
 221
 222         init.name = core->name;
 223         init.ops = &cpg_sd_clock_ops;
 224         init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
 225         init.parent_names = &parent_name;
 226         init.num_parents = 1;
 227
 228         clock->reg = base + core->offset;
 229         clock->hw.init = &init;
 230         clock->div_table = cpg_sd_div_table;
 231         clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
 232
 233         clock->div_max = clock->div_table[0].div;
 234         clock->div_min = clock->div_max;
 235         for (i = 1; i < clock->div_num; i++) {
 236                 clock->div_max = max(clock->div_max, clock->div_table[i].div);
 237                 clock->div_min = min(clock->div_min, clock->div_table[i].div);
 238         }
 239
 240         clk = clk_register(NULL, &clock->hw);
 241         if (IS_ERR(clk))
 242                 kfree(clock);
 243
 244         return clk;
 245 }
 246
 247
 248 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
 249 static unsigned int cpg_clk_extalr __initdata;
 250
 251 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
 252         const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
 253         struct clk **clks, void __iomem *base)
 254 {
 255         const struct clk *parent;
 256         unsigned int mult = 1;
 257         unsigned int div = 1;
 258         u32 value;
 259
 260         parent = clks[core->parent];
 261         if (IS_ERR(parent))
 262                 return ERR_CAST(parent);
 263
 264         switch (core->type) {
 265         case CLK_TYPE_GEN3_MAIN:
 266                 div = cpg_pll_config->extal_div;
 267                 break;
 268
 269         case CLK_TYPE_GEN3_PLL0:
 270                 /*
 271                  * PLL0 is a configurable multiplier clock. Register it as a
 272                  * fixed factor clock for now as there's no generic multiplier
 273                  * clock implementation and we currently have no need to change
 274                  * the multiplier value.
 275                  */
 276                 value = readl(base + CPG_PLL0CR);
 277                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 278                 break;
 279
 280         case CLK_TYPE_GEN3_PLL1:
 281                 mult = cpg_pll_config->pll1_mult;
 282                 break;
 283
 284         case CLK_TYPE_GEN3_PLL2:
 285                 /*
 286                  * PLL2 is a configurable multiplier clock. Register it as a
 287                  * fixed factor clock for now as there's no generic multiplier
 288                  * clock implementation and we currently have no need to change
 289                  * the multiplier value.
 290                  */
 291                 value = readl(base + CPG_PLL2CR);
 292                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 293                 break;
 294
 295         case CLK_TYPE_GEN3_PLL3:
 296                 mult = cpg_pll_config->pll3_mult;
 297                 break;
 298
 299         case CLK_TYPE_GEN3_PLL4:
 300                 /*
 301                  * PLL4 is a configurable multiplier clock. Register it as a
 302                  * fixed factor clock for now as there's no generic multiplier
 303                  * clock implementation and we currently have no need to change
 304                  * the multiplier value.
 305                  */
 306                 value = readl(base + CPG_PLL4CR);
 307                 mult = (((value >> 24) & 0x7f) + 1) * 2;
 308                 break;
 309
 310         case CLK_TYPE_GEN3_SD:
 311                 return cpg_sd_clk_register(core, base, __clk_get_name(parent));
 312
 313         case CLK_TYPE_GEN3_R:
 314                 /*
 315                  * RINT is default.
 316                  * Only if EXTALR is populated, we switch to it.
 317                  */
 318                 value = readl(base + CPG_RCKCR) & 0x3f;
 319
 320                 if (clk_get_rate(clks[cpg_clk_extalr])) {
 321                         parent = clks[cpg_clk_extalr];
 322                         value |= BIT(15);
 323                 }
 324
 325                 writel(value, base + CPG_RCKCR);
 326                 break;
 327
 328         default:
 329                 return ERR_PTR(-EINVAL);
 330         }
 331
 332         return clk_register_fixed_factor(NULL, core->name,
 333                                          __clk_get_name(parent), 0, mult, div);
 334 }
 335
 336 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
 337                               unsigned int clk_extalr)
 338 {
 339         cpg_pll_config = config;
 340         cpg_clk_extalr = clk_extalr;
 341         return 0;
 342 }